playground-stm32/f407ve_hs_uart
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Initialize other pheripherals

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This commit is contained in:
Attila Body 2019-10-07 11:47:37 +02:00
parent ec4df11c61
commit ffec0e2b57
69 changed files with 25802 additions and 620 deletions
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12
lib/console_handler.c
View file

@ -9,19 +9,31 @@
#include "usart_handler.h"
#include "strutil.h"
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart) // debug usart
{
DIAG_INTERRUPT_IN();
if(*info->isReg & info->tcMask) { // DMA transfer complete
*info->ifcReg = info->tcMask;
LL_USART_EnableIT_TC(usart);
LL_DMA_DisableStream(info->dma, info->stream);
}
DIAG_INTERRUPT_OUT();
}
void HandleConsoleUsartIrq(USART_TypeDef *usart)
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_TC(usart) && LL_USART_IsEnabledIT_TC(usart)) // transmission complete
LL_USART_DisableIT_TC(usart);
DIAG_INTERRUPT_OUT();
}
#define ADDINFO(b,s,u) \

11
lib/crc_handler.c
View file

@ -19,6 +19,15 @@
# define DIAG_CRC_CALC_END()
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
void InitCrcStatus(struct crcstatus_t *st, DMA_TypeDef *dma, uint32_t stream)
{
InitDmaInfo(&st->dmaInfo, dma, stream);
@ -90,6 +99,7 @@ void StartNextCrcTask(struct crcstatus_t *status)
void HandleCrcDmaIrq(struct crcstatus_t *status)
{
DIAG_INTERRUPT_IN();
if(*status->dmaInfo.isReg & status->dmaInfo.tcMask) { // DMA transfer complete
*status->dmaInfo.ifcReg = status->dmaInfo.tcMask;
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
@ -118,5 +128,6 @@ void HandleCrcDmaIrq(struct crcstatus_t *status)
StartNextCrcTask(status);
}
}
DIAG_INTERRUPT_OUT();
}

203
lib/fault.c
View file

@ -9,82 +9,81 @@
//#include <core_cm4.h>
#include "stm32f4xx.h"
#include "strutil.h"
#define HARD_FAULT 1
#define MEMMANAGE_FAULT 2
#define BUS_FAULT 3
#define USAGE_FAULT 4
#include "fault.h"
typedef struct {
uint32_t R0;
uint32_t R1;
uint32_t R2;
uint32_t R3;
uint32_t R4;
uint32_t R5;
uint32_t R6;
uint32_t R7;
uint32_t R8;
uint32_t R9;
uint32_t R10;
uint32_t R11;
uint32_t R12;
uint32_t SP;
uint32_t LR;
uint32_t PC;
uint32_t xPSR;
uint32_t PSP;
uint32_t MSP;
uint32_t EXC_RETURN;
uint32_t CONTROL;
uint32_t R0;
uint32_t R1;
uint32_t R2;
uint32_t R3;
uint32_t R4;
uint32_t R5;
uint32_t R6;
uint32_t R7;
uint32_t R8;
uint32_t R9;
uint32_t R10;
uint32_t R11;
uint32_t R12;
uint32_t SP;
uint32_t LR;
uint32_t PC;
uint32_t xPSR;
uint32_t PSP;
uint32_t MSP;
uint32_t EXC_RETURN;
uint32_t CONTROL;
} fault_context_t;
fault_context_t g_faultContext;
void __attribute__((weak)) app_fault_callback(uint32_t reason)
{
}
void SwoSendStr(char const *str, uint8_t len, uint8_t port)
{
while(len) {
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && // ITM enabled
((ITM->TER & (1UL << port) ) != 0UL) ) // ITM Port enabled
{
// Wait until shift register is free
while (ITM->PORT[port].u32 == 0UL) {
__ASM volatile ("nop");
}
if(len >= 4) {
ITM->PORT[port].u32 = *(uint32_t*)(str);
str += 4;
len -= 4;
} else if(len >= 2) {
ITM->PORT[port].u16 = *(uint16_t*)(str);
str += 2;
len -= 2;
} else {
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && // ITM enabled
((ITM->TER & (1UL << port) ) != 0UL) ) // ITM Port enabled
{
// Wait until shift register is free
while (ITM->PORT[port].u32 == 0UL) {
__ASM volatile ("nop");
}
if(len >= 4) {
ITM->PORT[port].u32 = *(uint32_t*)(str);
str += 4;
len -= 4;
} else if(len >= 2) {
ITM->PORT[port].u16 = *(uint16_t*)(str);
str += 2;
len -= 2;
} else {
ITM->PORT[port].u8 = *(uint8_t*)(str);
++str;
--len;
}
} else
break;
}
} else
break;
}
}
void fault_print_str(char *fmtstr, uint32_t *values)
{
char hex_str[9]={0};
char *nextChunk = fmtstr;
char hex_str[9]={0};
char *nextChunk = fmtstr;
while(*fmtstr) {
if(*fmtstr == '%') {
SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
uitohex(hex_str, *values++, 8);
SwoSendStr(hex_str, 8, 0);
nextChunk = fmtstr +1;
}
++fmtstr;
}
if(nextChunk != fmtstr)
while(*fmtstr) {
if(*fmtstr == '%') {
SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
uitohex(hex_str, *values++, 8);
SwoSendStr(hex_str, 8, 0);
nextChunk = fmtstr +1;
}
++fmtstr;
}
if(nextChunk != fmtstr)
SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
}
@ -92,31 +91,31 @@ void fault_print_str(char *fmtstr, uint32_t *values)
__attribute__((noreturn)) void FaultHandler(uint32_t type, fault_context_t *context)
{
uint32_t FSR[9] = {
SCB->HFSR,
0xff & SCB->CFSR,
(0xff00 & SCB->CFSR) >> 8,
(0xffff0000 & SCB->CFSR) >> 16,
SCB->DFSR,
SCB->AFSR,
SCB->SHCSR,
SCB->MMFAR,
SCB->BFAR
};
uint32_t FSR[9] = {
SCB->HFSR,
0xff & SCB->CFSR,
(0xff00 & SCB->CFSR) >> 8,
(0xffff0000 & SCB->CFSR) >> 16,
SCB->DFSR,
SCB->AFSR,
SCB->SHCSR,
SCB->MMFAR,
SCB->BFAR
};
while(1) {
fault_print_str("\n++ Fault Handler ++\n\nFaultType: ",NULL);
switch( type ) {
case HARD_FAULT:
case FAULT_REASON_HARD_FAULT:
fault_print_str("HardFault",NULL);
break;
case MEMMANAGE_FAULT:
case FAULT_REASON_MEMMANAGE_FAULT:
fault_print_str("MemManageFault",NULL);
break;
case BUS_FAULT:
case FAULT_REASON_BUS_FAULT:
fault_print_str("BusFault",NULL);
break;
case USAGE_FAULT:
case FAULT_REASON_USAGE_FAULT:
fault_print_str("UsageFault",NULL);
break;
default:
@ -126,36 +125,42 @@ __attribute__((noreturn)) void FaultHandler(uint32_t type, fault_context_t *cont
fault_print_str("\n\nContext:",NULL);
fault_print_str( "\nR0 : %"
"\nR1 : %"
"\nR2 : %"
"\nR3 : %"
"\nR4 : %"
"\nR5 : %"
"\nR6 : %"
"\nR7 : %"
"\nR8 : %"
"\nR9 : %"
"\nR10 : %"
"\nR11 : %"
"\nR12 : %"
"\nSP : %"
"\nLR : %"
"\nPC : %"
"\nxPSR : %"
"\nPSP : %"
"\nMSP : %", (uint32_t *)context);
fault_print_str(
"\nR0 : %"
"\nR1 : %"
"\nR2 : %"
"\nR3 : %"
"\nR4 : %"
"\nR5 : %"
"\nR6 : %"
"\nR7 : %"
"\nR8 : %"
"\nR9 : %"
"\nR10 : %"
"\nR11 : %"
"\nR12 : %"
"\nSP : %"
"\nLR : %"
"\nPC : %"
"\nxPSR : %"
"\nPSP : %"
"\nMSP : %",
(uint32_t *)context);
//Capture CPUID to get core/cpu info
fault_print_str("\nCPUID: %",(uint32_t *)&SCB->CPUID);
fault_print_str("\nHFSR : %"
"\nMMFSR: %"
"\nBFSR : %"
"\nUFSR : %"
"\nDFSR : %"
"\nAFSR : %"
"\nSHCSR: %",FSR);
fault_print_str(
"\nHFSR : %"
"\nMMFSR: %"
"\nBFSR : %"
"\nUFSR : %"
"\nDFSR : %"
"\nAFSR : %"
"\nSHCSR: %",
FSR);
app_fault_callback(type);
}
}

11
lib/fault.h Normal file
View file

@ -0,0 +1,11 @@
#ifndef __FAULT_H
#define __FAULT_H
#define FAULT_REASON_HARD_FAULT 1
#define FAULT_REASON_MEMMANAGE_FAULT 2
#define FAULT_REASON_BUS_FAULT 3
#define FAULT_REASON_USAGE_FAULT 4
void app_fault_callback(uint32_t reason);
#endif /* __FAULT_H */

10
lib/memcpy_dma.c
View file

@ -7,6 +7,14 @@
#include "memcpy_dma.h"
#include "dma_helper.h"
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
volatile uint8_t g_memcpyDmaBusy = 0;
static DMAINFO g_memcpyDmaInfo;
@ -31,9 +39,11 @@ void * MemcpyDma(void *dst, void const *src, size_t length)
void HandleMemcpyDmaIrq()
{
DIAG_INTERRUPT_IN();
if(*g_memcpyDmaInfo.isReg & g_memcpyDmaInfo.tcMask) { // DMA transfer complete
*g_memcpyDmaInfo.ifcReg = g_memcpyDmaInfo.tcMask;
LL_DMA_DisableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
g_memcpyDmaBusy = 0;
}
DIAG_INTERRUPT_OUT();
}

13
lib/usart_handler.c
View file

@ -16,6 +16,12 @@
#ifndef DIAG_RX_BUFFER_SWITCH
# define DIAG_RX_BUFFER_SWITCH(x)
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
void InitUartStatus(
@ -140,6 +146,7 @@ void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t s
void HandleUsartRxDmaIrq(UARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
StatsIncRcvd(&status->stats);
if(*status->rxDmaInfo.isReg & status->rxDmaInfo.tcMask) {
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.tcMask;
@ -163,10 +170,12 @@ void HandleUsartRxDmaIrq(UARTSTATUS *status)
if(status->rxBuffers[status->activeRxBuf].busy)
StatsIncOverrun(&status->stats);
SetupReceive(status);
DIAG_INTERRUPT_OUT();
}
void HandleUsartTxDmaIrq(UARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
LL_USART_EnableIT_TC(status->uart);
@ -183,11 +192,12 @@ void HandleUsartTxDmaIrq(UARTSTATUS *status)
*status->txDmaInfo.ifcReg = status->txDmaInfo.htMask;
if(*status->txDmaInfo.isReg & status->txDmaInfo.dmeMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.dmeMask;
DIAG_INTERRUPT_OUT();
}
void HandleUsartIrq(UARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_IDLE(status->uart) && LL_USART_IsEnabledIT_IDLE(status->uart)) { // receiver idle
LL_USART_ClearFlag_IDLE(status->uart);
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
@ -210,5 +220,6 @@ void HandleUsartIrq(UARTSTATUS *status)
LL_USART_EnableDirectionTx(status->uart);
status->txBuffer.busy = 0;
}
DIAG_INTERRUPT_OUT();
}

2
lib/usart_handler.h
View file

@ -60,7 +60,7 @@ typedef struct {
UARTBUFFER rxBuffers[2];
} UARTSTATUS;
#define STARTMARKER 0xa5
#define STARTMARKER 0x95
void InitUartStatus(
UARTSTATUS *st, USART_TypeDef *uart, DMA_TypeDef *dma,