fault handler
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/* Private typedef -----------------------------------------------------------*/
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/* USER CODE BEGIN TD */
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#define HardFault_Handler(x) __attribute__((weak)) HardFault_Handler(x)
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#define MemManage_Handler(x) __attribute__((weak)) MemManage_Handler(x)
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#define BusFault_Handler(x) __attribute__((weak)) BusFault_Handler(x)
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#define UsageFault_Handler(x) __attribute__((weak)) UsageFault_Handler(x)
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/* USER CODE END TD */
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161
lib/fault.c
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161
lib/fault.c
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@ -0,0 +1,161 @@
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/*
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* fault.c
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*
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* Created on: Oct 1, 2019
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* Author: abody
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* -c "tpiu config internal <logfile_full_path> uart off <cpufreq>"
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*/
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#include <inttypes.h>
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//#include <core_cm4.h>
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#include "stm32f4xx.h"
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#include "strutil.h"
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#define HARD_FAULT 1
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#define MEMMANAGE_FAULT 2
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#define BUS_FAULT 3
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#define USAGE_FAULT 4
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typedef struct {
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uint32_t R0;
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uint32_t R1;
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uint32_t R2;
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uint32_t R3;
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uint32_t R4;
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uint32_t R5;
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uint32_t R6;
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uint32_t R7;
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uint32_t R8;
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uint32_t R9;
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uint32_t R10;
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uint32_t R11;
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uint32_t R12;
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uint32_t SP;
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uint32_t LR;
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uint32_t PC;
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uint32_t xPSR;
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uint32_t PSP;
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uint32_t MSP;
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uint32_t EXC_RETURN;
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uint32_t CONTROL;
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} fault_context_t;
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fault_context_t g_faultContext;
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void SwoSendStr(char const *str, uint8_t len, uint8_t port)
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{
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while(len) {
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if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && // ITM enabled
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((ITM->TER & (1UL << port) ) != 0UL) ) // ITM Port enabled
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{
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// Wait until shift register is free
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while (ITM->PORT[port].u32 == 0UL) {
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__ASM volatile ("nop");
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}
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if(len >= 4) {
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ITM->PORT[port].u32 = *(uint32_t*)(str);
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str += 4;
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len -= 4;
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} else if(len >= 2) {
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ITM->PORT[port].u16 = *(uint16_t*)(str);
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str += 2;
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len -= 2;
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} else {
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ITM->PORT[port].u8 = *(uint8_t*)(str);
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++str;
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--len;
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}
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} else
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break;
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}
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}
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void fault_print_str(char *fmtstr, uint32_t *values)
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{
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char hex_str[9]={0};
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char *nextChunk = fmtstr;
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while(*fmtstr) {
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if(*fmtstr == '%') {
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SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
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uitohex(hex_str, *values++, 8);
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SwoSendStr(hex_str, 8, 0);
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nextChunk = fmtstr +1;
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}
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++fmtstr;
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}
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if(nextChunk != fmtstr)
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SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
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}
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__attribute__((noreturn)) void FaultHandler(uint32_t type, fault_context_t *context)
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{
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uint32_t FSR[9] = {
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SCB->HFSR,
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0xff & SCB->CFSR,
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(0xff00 & SCB->CFSR) >> 8,
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(0xffff0000 & SCB->CFSR) >> 16,
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SCB->DFSR,
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SCB->AFSR,
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SCB->SHCSR,
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SCB->MMFAR,
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SCB->BFAR
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};
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while(1) {
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fault_print_str("\n++ Fault Handler ++\n\nFaultType: ",NULL);
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switch( type ) {
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case HARD_FAULT:
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fault_print_str("HardFault",NULL);
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break;
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case MEMMANAGE_FAULT:
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fault_print_str("MemManageFault",NULL);
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break;
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case BUS_FAULT:
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fault_print_str("BusFault",NULL);
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break;
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case USAGE_FAULT:
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fault_print_str("UsageFault",NULL);
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break;
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default:
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fault_print_str("Unknown Fault",NULL);
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break;
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}
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fault_print_str("\n\nContext:",NULL);
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fault_print_str( "\nR0 : %"
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"\nR1 : %"
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"\nR2 : %"
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"\nR3 : %"
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"\nR4 : %"
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"\nR5 : %"
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"\nR6 : %"
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"\nR7 : %"
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"\nR8 : %"
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"\nR9 : %"
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"\nR10 : %"
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"\nR11 : %"
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"\nR12 : %"
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"\nSP : %"
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"\nLR : %"
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"\nPC : %"
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"\nxPSR : %"
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"\nPSP : %"
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"\nMSP : %", (uint32_t *)context);
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//Capture CPUID to get core/cpu info
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fault_print_str("\nCPUID: %",(uint32_t *)&SCB->CPUID);
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fault_print_str("\nHFSR : %"
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"\nMMFSR: %"
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"\nBFSR : %"
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"\nUFSR : %"
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"\nDFSR : %"
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"\nAFSR : %"
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"\nSHCSR: %",FSR);
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}
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}
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190
lib/fault_asm.s
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190
lib/fault_asm.s
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@ -0,0 +1,190 @@
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/*
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* Copyright (c) 2014-2018 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Title: Cortex-M Fault Exception handlers ( Common for both ARMv7M and ARMV6M )
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*
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* -----------------------------------------------------------------------------
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*/
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#ifndef MBED_FAULT_HANDLER_DISABLED
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.file "fault_asm.S"
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.syntax unified
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.equ FAULT_TYPE_HARD_FAULT, 1
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.equ FAULT_TYPE_MEMMANAGE_FAULT, 2
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.equ FAULT_TYPE_BUS_FAULT, 3
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.equ FAULT_TYPE_USAGE_FAULT, 4
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.thumb
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.section ".text"
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.align 2
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//HardFault_Handler
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.thumb_func
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.type HardFault_Handler, %function
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.global HardFault_Handler
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.fnstart
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.cantunwind
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HardFault_Handler:
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LDR R3,=FAULT_TYPE_HARD_FAULT
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B Fault_Handler
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.fnend
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.size HardFault_Handler, .-HardFault_Handler
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//MemManage_Handler
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.thumb_func
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.type MemManage_Handler, %function
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.global MemManage_Handler
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.fnstart
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.cantunwind
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MemManage_Handler:
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LDR R3,=FAULT_TYPE_MEMMANAGE_FAULT
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B Fault_Handler
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.fnend
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.size MemManage_Handler, .-MemManage_Handler
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//BusFault_Handler
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.thumb_func
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.type BusFault_Handler, %function
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.global BusFault_Handler
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.fnstart
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.cantunwind
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BusFault_Handler:
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LDR R3,=FAULT_TYPE_BUS_FAULT
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B Fault_Handler
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.fnend
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.size BusFault_Handler, .-BusFault_Handler
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//UsageFault_Handler
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.thumb_func
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.type UsageFault_Handler, %function
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.global UsageFault_Handler
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.fnstart
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.cantunwind
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UsageFault_Handler:
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LDR R3,=FAULT_TYPE_USAGE_FAULT
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B Fault_Handler
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.fnend
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.size UsageFault_Handler, .-UsageFault_Handler
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//Common Fault_Handler to capture the context
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.thumb_func
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.type Fault_Handler, %function
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.global Fault_Handler
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.fnstart
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.cantunwind
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Fault_Handler:
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MRS R0,MSP
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LDR R1,=0x4
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MOV R2,LR
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TST R2,R1 // Check EXC_RETURN for bit 2
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BEQ Fault_Handler_Continue
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MRS R0,PSP
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Fault_Handler_Continue:
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MOV R12,R3
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LDR R1,=g_faultContext
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LDR R2,[R0] // Capture R0
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#4] // Capture R1
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#8] // Capture R2
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#12] // Capture R3
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STR R2,[R1]
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ADDS R1,#4
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STMIA R1!,{R4-R7} // Capture R4..R7
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MOV R7,R8 // Capture R8
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R9 // Capture R9
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R10 // Capture R10
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STR R7,[R1]
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ADDS R1,#4
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MOV R7,R11 // Capture R11
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STR R7,[R1]
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ADDS R1,#4
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LDR R2,[R0,#16] // Capture R12
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STR R2,[R1]
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ADDS R1,#8 // Add 8 here to capture LR next, we will capture SP later
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LDR R2,[R0,#20] // Capture LR
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#24] // Capture PC
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STR R2,[R1]
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ADDS R1,#4
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LDR R2,[R0,#28] // Capture xPSR
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STR R2,[R1]
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ADDS R1,#4
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// Adjust stack pointer to its original value and capture it
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MOV R3,R0
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ADDS R3,#0x20 // Add 0x20 to get the SP value prior to exception
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LDR R6,=0x200
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TST R2,R6 // Check for if STK was aligned by checking bit-9 in xPSR value
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BEQ Fault_Handler_Continue1
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ADDS R3,#0x4
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Fault_Handler_Continue1:
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MOV R5,LR
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LDR R6,=0x10 // Check for bit-4 to see if FP context was saved
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TST R5,R6
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BNE Fault_Handler_Continue2
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ADDS R3,#0x48 // 16 FP regs + FPCSR + 1 Reserved
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Fault_Handler_Continue2:
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MOV R4,R1
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SUBS R4,#0x10 // Set the location of SP in ctx
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STR R3,[R4] // Capture the adjusted SP
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MRS R2,PSP // Get PSP
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STR R2,[R1]
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ADDS R1,#4
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MRS R2,MSP // Get MSP
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STR R2,[R1]
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ADDS R1,#4
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MOV R2,LR // Get current LR(EXC_RETURN)
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STR R2,[R1]
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ADDS R1,#4
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MRS R2,CONTROL // Get CONTROL Reg
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STR R2,[R1]
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LDR R3,=FaultHandler // Load address of mbedFaultHandler
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MOV R0,R12
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LDR R1,=g_faultContext
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BLX R3
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B . // Just in case we come back here
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.fnend
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.size Fault_Handler, .-Fault_Handler
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#endif
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.end
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