playground-stm32/f407ve_hs_uart
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playground-stm32:tmp
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compare: playground-stm32:eaf7ebc1919533109b79e6dc9b9054bf992f0298
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playground-stm32:tmp

2 commits
a4e25d702b ... eaf7ebc191

Author SHA1 Message Date
Attila Body
eaf7ebc191
tmp 5 2025-06-08 23:15:46 +02:00
Attila Body
66c9d451ab
tmp 4 2025-06-08 21:25:05 +02:00
14 changed files with 254 additions and 257 deletions
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2
components/app/inc/globals.h
View file

@ -11,5 +11,5 @@
#include <f4ll/packet_usart.h> #include <f4ll/packet_usart.h>
#include <inttypes.h> #include <inttypes.h>
extern f4ll::PacketUsart *g_usarts[USARTCOUNT]; extern f4ll::packet_usart *g_usarts[USARTCOUNT];
extern uint8_t g_statsBuf[256]; extern uint8_t g_statsBuf[256];

2
components/app/src/globals.cpp
View file

@ -10,6 +10,6 @@
#include <f4ll/memcpy_dma.h> #include <f4ll/memcpy_dma.h>
#include <f4ll/packet_usart.h> #include <f4ll/packet_usart.h>
f4ll::PacketUsart *g_usarts[USARTCOUNT]; f4ll::packet_usart *g_usarts[USARTCOUNT];
uint8_t g_statsBuf[256]; uint8_t g_statsBuf[256];

24
components/app/src/irq_bridge.cpp
View file

@ -8,46 +8,46 @@
void usart1_rx_dma_isr(void) void usart1_rx_dma_isr(void)
{ {
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART1_OFFSET]); f4ll::packet_usart::rx_dma_isr(g_usarts[USART1_OFFSET]);
} }
void usart1_tx_dma_isr(void) void usart1_tx_dma_isr(void)
{ {
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART1_OFFSET]); f4ll::packet_usart::tx_dma_isr(g_usarts[USART1_OFFSET]);
} }
void usart1_isr(void) void usart1_isr(void)
{ {
f4ll::PacketUsart::usart_isr(g_usarts[USART1_OFFSET]); f4ll::packet_usart::usart_isr(g_usarts[USART1_OFFSET]);
} }
// //
void usart2_rx_dma_isr(void) void usart2_rx_dma_isr(void)
{ {
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART2_OFFSET]); f4ll::packet_usart::rx_dma_isr(g_usarts[USART2_OFFSET]);
} }
void usart2_tx_dma_isr(void) void usart2_tx_dma_isr(void)
{ {
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART2_OFFSET]); f4ll::packet_usart::tx_dma_isr(g_usarts[USART2_OFFSET]);
} }
void usart2_isr(void) void usart2_isr(void)
{ {
f4ll::PacketUsart::usart_isr(g_usarts[USART2_OFFSET]); f4ll::packet_usart::usart_isr(g_usarts[USART2_OFFSET]);
} }
// //
void usart3_rx_dma_isr(void) void usart3_rx_dma_isr(void)
{ {
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART3_OFFSET]); f4ll::packet_usart::rx_dma_isr(g_usarts[USART3_OFFSET]);
} }
void usart3_tx_dma_isr(void) void usart3_tx_dma_isr(void)
{ {
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART3_OFFSET]); f4ll::packet_usart::tx_dma_isr(g_usarts[USART3_OFFSET]);
} }
void usart3_isr(void) void usart3_isr(void)
{ {
f4ll::PacketUsart::usart_isr(g_usarts[USART3_OFFSET]); f4ll::packet_usart::usart_isr(g_usarts[USART3_OFFSET]);
} }
// //
@ -64,16 +64,16 @@ void usart4_isr(void)
// //
void usart6_rx_dma_isr(void) void usart6_rx_dma_isr(void)
{ {
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART6_OFFSET]); f4ll::packet_usart::rx_dma_isr(g_usarts[USART6_OFFSET]);
} }
void usart6_tx_dma_isr(void) void usart6_tx_dma_isr(void)
{ {
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART6_OFFSET]); f4ll::packet_usart::tx_dma_isr(g_usarts[USART6_OFFSET]);
} }
void usart6_isr(void) void usart6_isr(void)
{ {
f4ll::PacketUsart::usart_isr(g_usarts[USART6_OFFSET]); f4ll::packet_usart::usart_isr(g_usarts[USART6_OFFSET]);
} }
void m2m1_dma_isr(void) void m2m1_dma_isr(void)

24
components/f4ll/inc/f4ll/console_handler.h
View file

@ -18,22 +18,22 @@ class console_handler : public usart_core, public singleton<console_handler>
friend class singleton<console_handler>; friend class singleton<console_handler>;
public: public:
void PrintStats(uint8_t id, PacketUsart &usart); void PrintStats(uint8_t id, packet_usart &usart);
private: private:
console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx); console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
// LL_UsartCore pure virtual function implementations // LL_UsartCore pure virtual function implementations
virtual void receiver_idle(void); virtual void receiver_idle(void) override;
virtual void transmission_complete(void); virtual void transmission_complete(void) override;
virtual void framing_error(void); virtual void framing_error(void) override;
virtual void overrun(void); virtual void overrun(void) override;
virtual void rx_dma_transfer_complete(void); virtual void rx_dma_transfer_complete(void) override;
virtual void rx_dma_half_transfer(void); virtual void rx_dma_half_transfer(void) override;
virtual void rx_dma_error(dma_helper::dma_error_type reason); virtual void rx_dma_error(dma_helper::dma_error_type reason) override;
virtual void tx_dma_transfer_complete(void); virtual void tx_dma_transfer_complete(void) override;
virtual void tx_dma_half_transfer(void); virtual void tx_dma_half_transfer(void) override;
virtual void tx_dma_error(dma_helper::dma_error_type reason); virtual void tx_dma_error(dma_helper::dma_error_type reason) override;
char m_buffer[128]; char m_buffer[128];
uint16_t m_used = 0; uint16_t m_used = 0;

2
components/f4ll/inc/f4ll/crc_handler.h
View file

@ -84,7 +84,7 @@ private:
dma_helper m_dma; dma_helper m_dma;
slot_base volatile *m_first_slot = nullptr; slot_base volatile *m_first_slot = nullptr;
slot_base volatile *m_active_slot = nullptr; slot_base volatile *m_active_slot = nullptr;
int volatile m_activeTask; int volatile m_active_task;
}; };
} // namespace f4ll } // namespace f4ll

25
components/f4ll/inc/f4ll/dma_helper.h
View file

@ -29,11 +29,11 @@ public:
inline uint32_t get_ht_mask() const { return m_ht_masks[m_stream]; } inline uint32_t get_ht_mask() const { return m_ht_masks[m_stream]; }
inline uint32_t get_tc_mask() const { return m_tc_masks[m_stream]; } inline uint32_t get_tc_mask() const { return m_tc_masks[m_stream]; }
inline bool is_enabled_it_ht() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; } inline bool is_enabled_it_ht() const { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
inline bool is_enabled_it_te() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; } inline bool is_enabled_it_te() const { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
inline bool is_enabled_it_tc() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; } inline bool is_enabled_it_tc() const { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
inline bool is_enabled_it_dme() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; } inline bool is_enabled_it_dme() const { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
inline bool is_enabled_it_fe() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; } inline bool is_enabled_it_fe() const { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
enum class dma_error_type { transfer, direct_mode, fifo }; enum class dma_error_type { transfer, direct_mode, fifo };
@ -43,11 +43,16 @@ private:
volatile uint32_t *m_is_reg; volatile uint32_t *m_is_reg;
volatile uint32_t *m_ifc_reg; volatile uint32_t *m_ifc_reg;
static const uint32_t m_fe_masks[8]; static constexpr uint32_t const m_fe_masks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3,
static const uint32_t m_dme_masks[8]; DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
static const uint32_t m_te_masks[8]; static constexpr uint32_t const m_dme_masks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3,
static const uint32_t m_ht_masks[8]; DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
static const uint32_t m_tc_masks[8]; static constexpr uint32_t const m_te_masks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3,
DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
static constexpr uint32_t const m_ht_masks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3,
DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
static constexpr uint32_t const m_tc_masks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3,
DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
}; };
} /* namespace f4ll */ } /* namespace f4ll */

28
components/f4ll/inc/f4ll/fault.h
View file

@ -10,7 +10,35 @@
extern "C" { extern "C" {
#endif #endif
typedef struct
{
uint32_t R0;
uint32_t R1;
uint32_t R2;
uint32_t R3;
uint32_t R4;
uint32_t R5;
uint32_t R6;
uint32_t R7;
uint32_t R8;
uint32_t R9;
uint32_t R10;
uint32_t R11;
uint32_t R12;
uint32_t SP;
uint32_t LR;
uint32_t PC;
uint32_t xPSR;
uint32_t PSP;
uint32_t MSP;
uint32_t EXC_RETURN;
uint32_t CONTROL;
} fault_context_t;
extern fault_context_t g_fault_context;
void app_fault_callback(uint32_t reason); void app_fault_callback(uint32_t reason);
__attribute__((noreturn)) void fault_handler(uint32_t type, fault_context_t *context);
#ifdef __cplusplus #ifdef __cplusplus
} }

17
components/f4ll/inc/f4ll/irq_lock.h
View file

@ -6,22 +6,21 @@
namespace f4ll { namespace f4ll {
class IrqLock { class irq_lock
{
public: public:
inline IrqLock() : m_primask(__get_PRIMASK()) { inline irq_lock()
: m_primask(__get_PRIMASK())
{
__disable_irq(); __disable_irq();
} }
inline void Release() { inline void release() { __set_PRIMASK(m_primask); }
__set_PRIMASK(m_primask);
} inline ~irq_lock() { __set_PRIMASK(m_primask); }
inline ~IrqLock() {
__set_PRIMASK(m_primask);
}
private: private:
uint32_t m_primask; uint32_t m_primask;
}; };
} }
#endif // _IRQLOCK_H_INCLUDED #endif // _IRQLOCK_H_INCLUDED

106
components/f4ll/inc/f4ll/packet_usart.h
View file

@ -15,35 +15,35 @@ namespace f4ll {
struct DMAINFO; struct DMAINFO;
class PacketUsart : public crc_handler::icallback, public usart_core class packet_usart : public crc_handler::icallback, public usart_core
{ {
// friend class UsartCore; // friend class UsartCore;
public: public:
PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx); packet_usart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
struct PacketHeader struct packet_header
{ // !!! size should be multiple of 4 !!! { // !!! size should be multiple of 4 !!!
uint8_t startByte; uint8_t start_byte;
uint8_t serial; uint8_t serial;
uint8_t payloadLength; uint8_t payload_length;
uint8_t hash; uint8_t hash;
}; };
struct Packet struct packet
{ {
PacketHeader header; packet_header header;
uint8_t payload[256 + sizeof(uint32_t)]; // extra room for crc32 uint8_t payload[256 + sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned)); } __attribute__((aligned));
struct Stats struct stats
{ {
uint32_t overrun = 0; uint32_t overrun = 0;
uint32_t hdrError = 0; uint32_t hdr_error = 0;
uint32_t payloadErrror = 0; uint32_t payload_errror = 0;
uint32_t pep1 = 0; uint32_t pep1 = 0;
uint32_t pep2 = 0; uint32_t pep2 = 0;
uint32_t rxDmaError = 0; uint32_t rx_dma_error = 0;
uint32_t txDmaError = 0; uint32_t tx_dma_error = 0;
uint32_t rcvd = 0; uint32_t rcvd = 0;
uint32_t premature_hdr = 0; uint32_t premature_hdr = 0;
uint32_t premature_payload = 0; uint32_t premature_payload = 0;
@ -51,71 +51,71 @@ public:
uint32_t skiped = 0; uint32_t skiped = 0;
}; };
struct IHsUsartCallback struct ihs_usart_callback
{ {
virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0; virtual bool packet_received(packet_usart *caller, uintptr_t user_param, packet const &packet) = 0;
}; };
// crc_handler::ICallback interface functions // crc_handler::ICallback interface functions
virtual void crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t task); virtual void crc_succeeded(uintptr_t callback_param, uint32_t crc, uint8_t task) override;
virtual void crc_failed(uintptr_t callbackParam, uint32_t crc, uint8_t task); virtual void crc_failed(uintptr_t callback_param, uint32_t crc, uint8_t task) override;
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true); void post_packet(uint8_t const *payload, uint8_t length, bool wait_for_crc_queue = true);
void SetupReceive(void); void setup_receive(void);
void RxProcessed(bool second); void rx_processed(bool second);
// Getters // Getters
uint8_t *GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; } uint8_t *get_tx_packet_buffer(void) { return m_tx_buffer.pkt.payload; }
uint8_t const *GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; } uint8_t const *get_rx_packet_buffer(bool second) { return m_rx_buffers[second].pkt.payload; }
USART_TypeDef *GetUsart(void) const { return m_usart; } USART_TypeDef *get_usart(void) const { return m_usart; }
Stats const &GetStats(void) const { return m_stats; } stats const &get_stats(void) const { return m_stats; }
inline bool IsTxBusy(void) const { return m_txBuffer.busy; } inline bool is_tx_busy(void) const { return m_tx_buffer.busy; }
inline bool IsTxFailed(void) const { return m_txBuffer.error; } inline bool is_tx_failed(void) const { return m_tx_buffer.error; }
inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; } inline bool is_rx_busy(bool second) const { return m_rx_buffers[second].busy; }
inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; } inline bool is_rx_failed(bool second) const { return m_rx_buffers[second].error; }
void SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam); void set_callback(ihs_usart_callback *callback, uintptr_t callback_param);
private: private:
void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length); void build_header(packet &packet, uint8_t serial_nr, uint8_t length);
bool CheckHeader(PacketHeader &header); bool check_header(packet_header &header);
void SwitchRxBuffers(void); void switch_rx_buffers(void);
// UsartCore pure virtual function implementations // UsartCore pure virtual function implementations
virtual void receiver_idle(void); virtual void receiver_idle(void) override;
virtual void transmission_complete(void); virtual void transmission_complete(void) override;
virtual void framing_error(void); virtual void framing_error(void) override;
virtual void overrun(void); virtual void overrun(void) override;
virtual void rx_dma_transfer_complete(void); virtual void rx_dma_transfer_complete(void) override;
virtual void rx_dma_half_transfer(void); virtual void rx_dma_half_transfer(void) override;
virtual void rx_dma_error(dma_helper::dma_error_type reason); virtual void rx_dma_error(dma_helper::dma_error_type reason) override;
virtual void tx_dma_transfer_complete(void); virtual void tx_dma_transfer_complete(void) override;
virtual void tx_dma_half_transfer(void); virtual void tx_dma_half_transfer(void) override;
virtual void tx_dma_error(dma_helper::dma_error_type reason); virtual void tx_dma_error(dma_helper::dma_error_type reason) override;
struct Buffer struct Buffer
{ {
Packet packet; packet pkt;
// transfer area ends here // transfer area ends here
bool volatile busy = 0; bool volatile busy = 0;
bool volatile error = 0; bool volatile error = 0;
uint16_t requestedLength = 0; uint16_t requested_length = 0;
uint32_t errorInfo = 0; uint32_t error_info = 0;
}; };
static const uint8_t STARTMARKER = 0x95; static const uint8_t STARTMARKER = 0x95;
uint8_t m_rxSerialNo = -1; uint8_t m_rx_serial_nr = -1;
uint8_t m_txSerialNo = -1; uint8_t m_tx_serial_nr = -1;
Stats m_stats; stats m_stats;
bool m_rxBufferSelector = false; bool m_rx_buffer_selector = false;
crc_handler::slot<2> m_crcSlot; crc_handler::slot<2> m_crc_slot;
IHsUsartCallback *m_userCallback = nullptr; ihs_usart_callback *m_user_callback = nullptr;
uintptr_t m_userCallbackParam = 0; uintptr_t m_user_callback_param = 0;
Buffer m_txBuffer; Buffer m_tx_buffer;
Buffer m_rxBuffers[2]; Buffer m_rx_buffers[2];
}; };
} }

16
components/f4ll/src/console_handler.cpp
View file

@ -10,8 +10,8 @@
namespace f4ll { namespace f4ll {
console_handler::console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx) console_handler::console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx)
: usart_core(usart, dma, streamRx, streamTx) : usart_core(usart, dma, stream_rx, stream_tx)
{ {
} }
@ -49,11 +49,11 @@ void console_handler::tx_dma_error(dma_helper::dma_error_type reason)
b += strcpy_ex(b, s); \ b += strcpy_ex(b, s); \
b += uitodec(b, u); b += uitodec(b, u);
void console_handler::PrintStats(uint8_t id, PacketUsart &usart) void console_handler::PrintStats(uint8_t id, packet_usart &usart)
{ {
char ids[] = " : "; char ids[] = " : ";
char *buffer = m_buffer; char *buffer = m_buffer;
PacketUsart::Stats const &stats(usart.GetStats()); packet_usart::stats const &stats(usart.get_stats());
ids[0] = id + '0'; ids[0] = id + '0';
buffer += strcpy_ex(buffer, ids); buffer += strcpy_ex(buffer, ids);
@ -61,14 +61,14 @@ void console_handler::PrintStats(uint8_t id, PacketUsart &usart)
ADDINFO(buffer, " r: ", stats.rcvd); ADDINFO(buffer, " r: ", stats.rcvd);
ADDINFO(buffer, " sk: ", stats.skiped); ADDINFO(buffer, " sk: ", stats.skiped);
ADDINFO(buffer, " or: ", stats.overrun); ADDINFO(buffer, " or: ", stats.overrun);
ADDINFO(buffer, " he: ", stats.hdrError); ADDINFO(buffer, " he: ", stats.hdr_error);
ADDINFO(buffer, " pe: ", stats.payloadErrror); ADDINFO(buffer, " pe: ", stats.payload_errror);
buffer += strcpy_ex(buffer, ",0x"); buffer += strcpy_ex(buffer, ",0x");
buffer += uitohex(buffer, stats.pep1, 8); buffer += uitohex(buffer, stats.pep1, 8);
buffer += strcpy_ex(buffer, ",0x"); buffer += strcpy_ex(buffer, ",0x");
buffer += uitohex(buffer, stats.pep2, 8); buffer += uitohex(buffer, stats.pep2, 8);
ADDINFO(buffer, " rde: ", stats.rxDmaError); ADDINFO(buffer, " rde: ", stats.rx_dma_error);
ADDINFO(buffer, " tde: ", stats.txDmaError); ADDINFO(buffer, " tde: ", stats.tx_dma_error);
ADDINFO(buffer, " pmh: ", stats.premature_hdr); ADDINFO(buffer, " pmh: ", stats.premature_hdr);
ADDINFO(buffer, " pmp: ", stats.premature_payload); ADDINFO(buffer, " pmp: ", stats.premature_payload);
buffer += strcpy_ex(buffer, "\r\n"); buffer += strcpy_ex(buffer, "\r\n");

42
components/f4ll/src/crc_handler.cpp
View file

@ -32,7 +32,7 @@ void crc_handler::attach_slot(slot_base &slot)
__set_PRIMASK(prim); __set_PRIMASK(prim);
} }
bool crc_handler::enqueue(slot_base &slot, uint8_t task, void const *address, uint16_t len, icallback *cb, uintptr_t cbParam) bool crc_handler::enqueue(slot_base &slot, uint8_t task, void const *address, uint16_t len, icallback *cb, uintptr_t cb_param)
{ {
uint32_t prim = __get_PRIMASK(); uint32_t prim = __get_PRIMASK();
bool immediate; bool immediate;
@ -47,10 +47,10 @@ bool crc_handler::enqueue(slot_base &slot, uint8_t task, void const *address, ui
slot[task].m_address = (!immediate) ? address : nullptr; slot[task].m_address = (!immediate) ? address : nullptr;
slot[task].m_word_count = (len + 3) / 4; slot[task].m_word_count = (len + 3) / 4;
slot[task].m_callback = cb; slot[task].m_callback = cb;
slot[task].m_callback_param = cbParam; slot[task].m_callback_param = cb_param;
if (immediate) { if (immediate) {
m_active_slot = &slot; m_active_slot = &slot;
m_activeTask = task; m_active_task = task;
} }
__set_PRIMASK(prim); __set_PRIMASK(prim);
@ -84,44 +84,44 @@ void crc_handler::dma_transfer_completed(void)
*m_dma.get_ifc_reg() = m_dma.get_tc_mask(); *m_dma.get_ifc_reg() = m_dma.get_tc_mask();
LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream()); LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream());
if (m_active_slot) { if (m_active_slot) {
if ((*m_active_slot)[m_activeTask].m_callback) { if ((*m_active_slot)[m_active_task].m_callback) {
(*m_active_slot)[m_activeTask].m_callback->crc_succeeded( (*m_active_slot)[m_active_task].m_callback->crc_succeeded(
(*m_active_slot)[m_activeTask].m_callback_param, CRC->DR, m_activeTask); (*m_active_slot)[m_active_task].m_callback_param, CRC->DR, m_active_task);
} else if ((*m_active_slot)[m_activeTask].m_callback_param) { } else if ((*m_active_slot)[m_active_task].m_callback_param) {
*reinterpret_cast<uint32_t *>((*m_active_slot)[m_activeTask].m_callback_param) = CRC->DR; *reinterpret_cast<uint32_t *>((*m_active_slot)[m_active_task].m_callback_param) = CRC->DR;
} }
} }
} else if (*m_dma.get_is_reg() & m_dma.get_te_mask()) { // DMA transfer error } else if (*m_dma.get_is_reg() & m_dma.get_te_mask()) { // DMA transfer error
*m_dma.get_ifc_reg() = m_dma.get_te_mask(); *m_dma.get_ifc_reg() = m_dma.get_te_mask();
LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream()); LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream());
if (m_active_slot) { if (m_active_slot) {
if ((*m_active_slot)[m_activeTask].m_callback) { if ((*m_active_slot)[m_active_task].m_callback) {
(*m_active_slot)[m_activeTask].m_callback->crc_failed( (*m_active_slot)[m_active_task].m_callback->crc_failed(
(*m_active_slot)[m_activeTask].m_callback_param, CRC->DR, m_activeTask); (*m_active_slot)[m_active_task].m_callback_param, CRC->DR, m_active_task);
} else if ((*m_active_slot)[m_activeTask].m_callback_param) { } else if ((*m_active_slot)[m_active_task].m_callback_param) {
*reinterpret_cast<uint32_t *>((*m_active_slot)[m_activeTask].m_callback_param) = -1; *reinterpret_cast<uint32_t *>((*m_active_slot)[m_active_task].m_callback_param) = -1;
} }
} }
} }
(*m_active_slot)[m_activeTask].m_callback = nullptr; (*m_active_slot)[m_active_task].m_callback = nullptr;
(*m_active_slot)[m_activeTask].m_callback_param = 0; (*m_active_slot)[m_active_task].m_callback_param = 0;
(*m_active_slot)[m_activeTask].m_word_count = 0; (*m_active_slot)[m_active_task].m_word_count = 0;
start_next_task(); start_next_task();
} }
void crc_handler::start_next_task(void) void crc_handler::start_next_task(void)
{ {
bool moreTasks; bool more_tasks;
uint8_t index = 0; uint8_t index = 0;
do { do {
slot_base volatile *slot = m_first_slot; slot_base volatile *slot = m_first_slot;
moreTasks = false; more_tasks = false;
while (slot) { while (slot) {
if (index < slot->m_task_count) { if (index < slot->m_task_count) {
if ((*slot)[index].m_address) { if ((*slot)[index].m_address) {
m_active_slot = slot; m_active_slot = slot;
m_activeTask = index; m_active_task = index;
CRC->CR = 1; CRC->CR = 1;
LL_DMA_SetM2MSrcAddress(m_dma.get_dma(), m_dma.get_stream(), reinterpret_cast<uint32_t>((*slot)[index].m_address)); LL_DMA_SetM2MSrcAddress(m_dma.get_dma(), m_dma.get_stream(), reinterpret_cast<uint32_t>((*slot)[index].m_address));
LL_DMA_SetDataLength(m_dma.get_dma(), m_dma.get_stream(), (*slot)[index].m_word_count); LL_DMA_SetDataLength(m_dma.get_dma(), m_dma.get_stream(), (*slot)[index].m_word_count);
@ -130,13 +130,13 @@ void crc_handler::start_next_task(void)
return; return;
} }
if (index + 1 < slot->m_task_count) { if (index + 1 < slot->m_task_count) {
moreTasks = true; more_tasks = true;
} }
} }
slot = slot->m_next; slot = slot->m_next;
} }
++index; ++index;
} while (moreTasks); } while (more_tasks);
m_active_slot = nullptr; m_active_slot = nullptr;
} }

11
components/f4ll/src/dma_helper.cpp
View file

@ -9,17 +9,6 @@ q * ll_dmahelper.cpp
namespace f4ll { namespace f4ll {
const uint32_t dma_helper::m_fe_masks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3,
DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
const uint32_t dma_helper::m_dme_masks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3,
DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
const uint32_t dma_helper::m_te_masks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3,
DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
const uint32_t dma_helper::m_ht_masks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3,
DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
const uint32_t dma_helper::m_tc_masks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3,
DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
dma_helper::dma_helper(DMA_TypeDef *dma, uint32_t stream) dma_helper::dma_helper(DMA_TypeDef *dma, uint32_t stream)
: m_dma(dma), : m_dma(dma),
m_stream(stream), m_stream(stream),

45
components/f4ll/src/fault.cpp
View file

@ -15,38 +15,14 @@
extern "C" { extern "C" {
#endif #endif
typedef struct { fault_context_t g_fault_context;
uint32_t R0;
uint32_t R1;
uint32_t R2;
uint32_t R3;
uint32_t R4;
uint32_t R5;
uint32_t R6;
uint32_t R7;
uint32_t R8;
uint32_t R9;
uint32_t R10;
uint32_t R11;
uint32_t R12;
uint32_t SP;
uint32_t LR;
uint32_t PC;
uint32_t xPSR;
uint32_t PSP;
uint32_t MSP;
uint32_t EXC_RETURN;
uint32_t CONTROL;
} fault_context_t;
fault_context_t g_faultContext;
void __attribute__((weak)) app_fault_callback(uint32_t reason) void __attribute__((weak)) app_fault_callback(uint32_t reason)
{ {
(void)reason; (void)reason;
} }
void SwoSendStr(char const *str, uint8_t len, uint8_t port) void swo_send_str(char const *str, uint8_t len, uint8_t port)
{ {
while(len) { while(len) {
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && // ITM enabled if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && // ITM enabled
@ -77,24 +53,23 @@ void SwoSendStr(char const *str, uint8_t len, uint8_t port)
void fault_print_str(char const *fmtstr, uint32_t *values) void fault_print_str(char const *fmtstr, uint32_t *values)
{ {
char hex_str[9]={0}; char hex_str[9]={0};
char const *nextChunk = fmtstr; char const *next_chunk = fmtstr;
while(*fmtstr) { while(*fmtstr) {
if(*fmtstr == '%') { if(*fmtstr == '%') {
SwoSendStr(nextChunk, fmtstr-nextChunk, 0); swo_send_str(next_chunk, fmtstr - next_chunk, 0);
uitohex(hex_str, *values++, 8); uitohex(hex_str, *values++, 8);
SwoSendStr(hex_str, 8, 0); swo_send_str(hex_str, 8, 0);
nextChunk = fmtstr +1; next_chunk = fmtstr + 1;
} }
++fmtstr; ++fmtstr;
} }
if(nextChunk != fmtstr) if (next_chunk != fmtstr) {
SwoSendStr(nextChunk, fmtstr-nextChunk, 0); swo_send_str(next_chunk, fmtstr - next_chunk, 0);
}
} }
void fault_handler(uint32_t type, fault_context_t *context)
__attribute__((noreturn)) void FaultHandler(uint32_t type, fault_context_t *context)
{ {
uint32_t FSR[9] = { uint32_t FSR[9] = {
SCB->HFSR, SCB->HFSR,

153
components/f4ll/src/packet_usart.cpp
View file

@ -9,79 +9,80 @@
namespace f4ll { namespace f4ll {
template <typename T> static inline T RoundUpTo4(T input) template <typename T> static inline T round_up_to_4(T input)
{ {
return (input + 3) & (((T)-1) - 3); return (input + 3) & (((T)-1) - 3);
} }
PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx) packet_usart::packet_usart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx)
: usart_core(usart, dma, streamRx, streamTx) : usart_core(usart, dma, stream_rx, stream_tx)
{ {
crc_handler::instance().attach_slot(m_crcSlot); crc_handler::instance().attach_slot(m_crc_slot);
LL_USART_EnableIT_IDLE(usart); LL_USART_EnableIT_IDLE(usart);
LL_USART_EnableIT_ERROR(usart); LL_USART_EnableIT_ERROR(usart);
} }
void PacketUsart::RxProcessed(bool second) void packet_usart::rx_processed(bool second)
{ {
m_rxBuffers[second].busy = false; m_rx_buffers[second].busy = false;
m_rxBuffers[second].error = false; m_rx_buffers[second].error = false;
} }
void PacketUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam) void packet_usart::set_callback(ihs_usart_callback *callback, uintptr_t callback_param)
{ {
m_userCallback = callback; m_user_callback = callback;
m_userCallbackParam = callbackParam; m_user_callback_param = callback_param;
} }
void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue) void packet_usart::post_packet(uint8_t const *payload, uint8_t length, bool wait_for_crc_queue)
{ {
uint16_t payloadLength = RoundUpTo4((uint16_t)length); uint16_t payload_length = round_up_to_4((uint16_t)length);
BuildHeader(m_txBuffer.packet, m_txSerialNo++, length); build_header(m_tx_buffer.pkt, m_tx_serial_nr++, length);
if (payload) { if (payload) {
memcpy(m_txBuffer.packet.payload, payload, length); memcpy(m_tx_buffer.pkt.payload, payload, length);
} }
m_txBuffer.requestedLength = sizeof(m_txBuffer.packet.header) + payloadLength + sizeof(uint32_t); m_tx_buffer.requested_length = sizeof(m_tx_buffer.pkt.header) + payload_length + sizeof(uint32_t);
m_txBuffer.busy = true; m_tx_buffer.busy = true;
m_txBuffer.error = false; m_tx_buffer.error = false;
crc_handler::instance().enqueue( crc_handler::instance().enqueue(
m_crcSlot, 0, &m_txBuffer.packet, sizeof(PacketHeader) + payloadLength, nullptr, m_crc_slot, 0, &m_tx_buffer.pkt, sizeof(packet_header) + payload_length, nullptr,
reinterpret_cast<uintptr_t>(m_txBuffer.packet.payload + payloadLength)); reinterpret_cast<uintptr_t>(m_tx_buffer.pkt.payload + payload_length));
while (waitForCrcQueue && crc_handler::instance().is_queued(m_crcSlot, 0)) while (wait_for_crc_queue && crc_handler::instance().is_queued(m_crc_slot, 0))
; ;
setup_transmit(&m_txBuffer.packet, m_txBuffer.requestedLength); setup_transmit(&m_tx_buffer.pkt, m_tx_buffer.requested_length);
++m_stats.sent; ++m_stats.sent;
} }
void PacketUsart::SetupReceive() void packet_usart::setup_receive()
{ {
m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet); m_rx_buffers[m_rx_buffer_selector].requested_length = sizeof(m_rx_buffers[m_rx_buffer_selector].pkt);
usart_core::setup_receive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet)); usart_core::setup_receive(&m_rx_buffers[m_rx_buffer_selector], sizeof(m_rx_buffers[m_rx_buffer_selector].pkt));
} }
////////////////////////////////////// //////////////////////////////////////
// UsartCore pure virtual functions // // UsartCore pure virtual functions //
////////////////////////////////////// //////////////////////////////////////
void PacketUsart::receiver_idle(void) void packet_usart::receiver_idle(void)
{ {
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rx_dma.get_dma(), m_rx_dma.get_stream()); uint16_t rcvdLen =
m_rx_buffers[m_rx_buffer_selector].requested_length - LL_DMA_GetDataLength(m_rx_dma.get_dma(), m_rx_dma.get_stream());
if (rcvdLen >= sizeof(PacketHeader)) { if (rcvdLen >= sizeof(packet_header)) {
if (CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) { if (check_header(m_rx_buffers[m_rx_buffer_selector].pkt.header)) {
if (rcvdLen >= sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength) + if (rcvdLen >= sizeof(packet_header) + round_up_to_4((uint16_t)m_rx_buffers[m_rx_buffer_selector].pkt.header.payload_length) +
sizeof(uint32_t)) { sizeof(uint32_t)) {
LL_DMA_DisableStream(m_rx_dma.get_dma(), m_rx_dma.get_stream()); LL_DMA_DisableStream(m_rx_dma.get_dma(), m_rx_dma.get_stream());
} else { } else {
++m_stats.premature_payload; ++m_stats.premature_payload;
} }
} else { } else {
m_rxBuffers[m_rxBufferSelector].error = 1; m_rx_buffers[m_rx_buffer_selector].error = 1;
LL_DMA_DisableStream(m_rx_dma.get_dma(), m_rx_dma.get_stream()); LL_DMA_DisableStream(m_rx_dma.get_dma(), m_rx_dma.get_stream());
} }
} else { } else {
@ -89,122 +90,122 @@ void PacketUsart::receiver_idle(void)
} }
} }
void PacketUsart::transmission_complete(void) void packet_usart::transmission_complete(void)
{ {
LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
LL_USART_EnableDirectionTx(m_usart); LL_USART_EnableDirectionTx(m_usart);
m_txBuffer.busy = 0; m_tx_buffer.busy = 0;
} }
void PacketUsart::framing_error(void) {} void packet_usart::framing_error(void) {}
void PacketUsart::overrun(void) {} void packet_usart::overrun(void) {}
void PacketUsart::rx_dma_transfer_complete(void) void packet_usart::rx_dma_transfer_complete(void)
{ {
if (CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) { if (check_header(m_rx_buffers[m_rx_buffer_selector].pkt.header)) {
crc_handler::instance().enqueue( crc_handler::instance().enqueue(
m_crcSlot, 1, &m_rxBuffers[m_rxBufferSelector].packet, m_crc_slot, 1, &m_rx_buffers[m_rx_buffer_selector].pkt,
sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength), this, sizeof(packet_header) + round_up_to_4((uint16_t)m_rx_buffers[m_rx_buffer_selector].pkt.header.payload_length), this,
m_rxBufferSelector); m_rx_buffer_selector);
} else { } else {
++m_stats.hdrError; ++m_stats.hdr_error;
m_rxBuffers[m_rxBufferSelector].error = true; m_rx_buffers[m_rx_buffer_selector].error = true;
} }
SwitchRxBuffers(); switch_rx_buffers();
} }
void PacketUsart::rx_dma_half_transfer(void) {} void packet_usart::rx_dma_half_transfer(void) {}
void PacketUsart::rx_dma_error(dma_helper::dma_error_type reason) void packet_usart::rx_dma_error(dma_helper::dma_error_type reason)
{ {
(void)reason; (void)reason;
m_rxBuffers[m_rxBufferSelector].error = 1; m_rx_buffers[m_rx_buffer_selector].error = 1;
++m_stats.rxDmaError; ++m_stats.rx_dma_error;
SwitchRxBuffers(); switch_rx_buffers();
} }
void PacketUsart::tx_dma_transfer_complete(void) void packet_usart::tx_dma_transfer_complete(void)
{ {
LL_USART_EnableIT_TC(m_usart); LL_USART_EnableIT_TC(m_usart);
LL_DMA_DisableStream(m_tx_dma.get_dma(), m_tx_dma.get_stream()); LL_DMA_DisableStream(m_tx_dma.get_dma(), m_tx_dma.get_stream());
} }
void PacketUsart::tx_dma_half_transfer(void) {} void packet_usart::tx_dma_half_transfer(void) {}
void PacketUsart::tx_dma_error(dma_helper::dma_error_type reason) void packet_usart::tx_dma_error(dma_helper::dma_error_type reason)
{ {
(void)reason; (void)reason;
m_txBuffer.error = 1; m_tx_buffer.error = 1;
++m_stats.txDmaError; ++m_stats.tx_dma_error;
} }
/////////////////////// ///////////////////////
// Private functions // // Private functions //
/////////////////////// ///////////////////////
void PacketUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length) void packet_usart::build_header(packet &packet, uint8_t serial_nr, uint8_t length)
{ {
uint8_t hash = STARTMARKER; uint8_t hash = STARTMARKER;
packet.header.startByte = STARTMARKER; packet.header.start_byte = STARTMARKER;
packet.header.serial = serialNo; packet.header.serial = serial_nr;
hash ^= serialNo; hash ^= serial_nr;
packet.header.payloadLength = length; packet.header.payload_length = length;
hash ^= length; hash ^= length;
packet.header.hash = hash; packet.header.hash = hash;
} }
bool PacketUsart::CheckHeader(PacketHeader &header) bool packet_usart::check_header(packet_header &header)
{ {
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash; return header.start_byte == STARTMARKER && (header.start_byte ^ header.serial ^ header.payload_length) == header.hash;
} }
void PacketUsart::SwitchRxBuffers(void) void packet_usart::switch_rx_buffers(void)
{ {
++m_stats.rcvd; ++m_stats.rcvd;
m_rxBufferSelector = !m_rxBufferSelector; m_rx_buffer_selector = !m_rx_buffer_selector;
if (m_rxBuffers[m_rxBufferSelector].busy) { if (m_rx_buffers[m_rx_buffer_selector].busy) {
++m_stats.overrun; ++m_stats.overrun;
} }
SetupReceive(); setup_receive();
} }
/////////////////////////// ///////////////////////////
// crc_handler::ICallback // // crc_handler::ICallback //
/////////////////////////// ///////////////////////////
void PacketUsart::crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t task) void packet_usart::crc_succeeded(uintptr_t callback_param, uint32_t crc, uint8_t task)
{ {
(void)task; (void)task;
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]); Buffer &buf(m_rx_buffers[static_cast<int>(callback_param)]);
buf.busy = 1; buf.busy = 1;
if (*(uint32_t *)(buf.packet.payload + RoundUpTo4((uint16_t)buf.packet.header.payloadLength)) != crc) { if (*(uint32_t *)(buf.pkt.payload + round_up_to_4((uint16_t)buf.pkt.header.payload_length)) != crc) {
buf.error = 1; buf.error = 1;
buf.errorInfo = crc; buf.error_info = crc;
++m_stats.payloadErrror; ++m_stats.payload_errror;
} }
if (m_userCallback) { if (m_user_callback) {
buf.busy = !m_userCallback->PacketReceived(this, m_userCallbackParam, buf.packet); buf.busy = !m_user_callback->packet_received(this, m_user_callback_param, buf.pkt);
} }
} }
void PacketUsart::crc_failed(uintptr_t callbackParam, uint32_t crc, uint8_t task) void packet_usart::crc_failed(uintptr_t callback_param, uint32_t crc, uint8_t task)
{ {
(void)crc; (void)crc;
(void)task; (void)task;
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]); Buffer &buf(m_rx_buffers[static_cast<int>(callback_param)]);
buf.busy = buf.error = true; buf.busy = buf.error = true;
buf.errorInfo = 0; buf.error_info = 0;
++m_stats.payloadErrror; ++m_stats.payload_errror;
if (m_userCallback) { if (m_user_callback) {
buf.busy = !m_userCallback->PacketReceived(this, m_userCallbackParam, buf.packet); buf.busy = !m_user_callback->packet_received(this, m_user_callback_param, buf.pkt);
} }
} }