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BD0C6214E68FB5CF
14 changed files with 398 additions and 399 deletions
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@ -6,14 +6,14 @@
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*/
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#ifdef USE_CPLUSPLUS
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#include <string.h>
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#include <stdlib.h>
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#include "f4ll/packetusart.h"
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#include "f4ll/crchandler.h"
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#include "f4ll/memcpydma.h"
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#include "f4ll/consolehandler.h"
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#include "f4ll/crc_handler.h"
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#include "f4ll/irqlock.h"
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#include "f4ll/memcpydma.h"
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#include "f4ll/packetusart.h"
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#include "f4ll/strutil.h"
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#include <stdlib.h>
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#include <string.h>
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extern "C" {
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#include "main.h"
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@ -38,8 +38,8 @@ extern "C" void MainLoop()
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f4ll::MemcpyDma::Init(MEMCPY_DMA_ENGINE, MEMCPY_DMA_STREAM);
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f4ll::CrcHandler::Init(DMA2, LL_DMA_STREAM_4);
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f4ll::ConsoleHandler::Init(UART4, CONSOLE_DMA_ENGINE, 0u, CONSOLE_TX_DMA_STREAM);
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f4ll::crc_handler::Init(DMA2, LL_DMA_STREAM_4);
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f4ll::ConsoleHandler::Init(UART4, CONSOLE_DMA_ENGINE, 0u, CONSOLE_TX_DMA_STREAM);
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f4ll::PacketUsart u1{ USART1, DMA2, LL_DMA_STREAM_2, LL_DMA_STREAM_7 };
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f4ll::PacketUsart u2{ USART2, DMA1, LL_DMA_STREAM_5, LL_DMA_STREAM_6 };
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@ -1,4 +1,6 @@
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#include "f4ll/console_handler.h"
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#include <f4ll/console_handler.h>
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#include <f4ll/crc_handler.h>
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#include <f4ll/memcpy_dma.h>
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#include <config.h>
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#include <globals.h>
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@ -6,73 +8,80 @@
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void usart1_rx_dma_isr(void)
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{
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART1_OFFSET]);
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f4ll::PacketUsart::rx_dma_isr(g_usarts[USART1_OFFSET]);
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}
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void usart1_tx_dma_isr(void)
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{
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART1_OFFSET]);
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f4ll::PacketUsart::tx_dma_isr(g_usarts[USART1_OFFSET]);
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}
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void usart1_isr(void)
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{
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART1_OFFSET]);
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f4ll::PacketUsart::usart_isr(g_usarts[USART1_OFFSET]);
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}
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//
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void usart2_rx_dma_isr(void)
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{
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART2_OFFSET]);
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f4ll::PacketUsart::rx_dma_isr(g_usarts[USART2_OFFSET]);
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}
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void usart2_tx_dma_isr(void)
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{
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART2_OFFSET]);
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f4ll::PacketUsart::tx_dma_isr(g_usarts[USART2_OFFSET]);
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}
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void usart2_isr(void)
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{
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART2_OFFSET]);
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f4ll::PacketUsart::usart_isr(g_usarts[USART2_OFFSET]);
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}
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//
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void usart3_rx_dma_isr(void)
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{
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART3_OFFSET]);
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f4ll::PacketUsart::rx_dma_isr(g_usarts[USART3_OFFSET]);
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}
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void usart3_tx_dma_isr(void)
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{
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART3_OFFSET]);
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f4ll::PacketUsart::tx_dma_isr(g_usarts[USART3_OFFSET]);
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}
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void usart3_isr(void)
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{
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART3_OFFSET]);
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f4ll::PacketUsart::usart_isr(g_usarts[USART3_OFFSET]);
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}
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//
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void usart4_rx_dma_isr(void) {} // console
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void usart4_tx_dma_isr(void)
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{
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f4ll::console_handler::HandleTxDmaIrq(&f4ll::console_handler::instance());
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f4ll::console_handler::tx_dma_isr(&f4ll::console_handler::instance());
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} // console
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void usart4_isr(void)
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{
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f4ll::console_handler::HandleUsartIrq(&f4ll::console_handler::instance());
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f4ll::console_handler::usart_isr(&f4ll::console_handler::instance());
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}
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//
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void usart6_rx_dma_isr(void)
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{
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART6_OFFSET]);
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f4ll::PacketUsart::rx_dma_isr(g_usarts[USART6_OFFSET]);
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}
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void usart6_tx_dma_isr(void)
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{
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART6_OFFSET]);
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f4ll::PacketUsart::tx_dma_isr(g_usarts[USART6_OFFSET]);
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}
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void usart6_isr(void)
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{
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART6_OFFSET]);
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f4ll::PacketUsart::usart_isr(g_usarts[USART6_OFFSET]);
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}
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void m2m1_dma_isr(void) {} // m2mcpy
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void m2m2_dma_isr(void) {} // crc
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void m2m1_dma_isr(void)
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{
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f4ll::memcpy_dma::instance().dma_transfer_completed();
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} // m2mcpy
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void m2m2_dma_isr(void)
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{
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f4ll::crc_handler::instance().dma_transfer_completed();
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} // crc
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@ -24,16 +24,16 @@ private:
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console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(dma_helper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(dma_helper::DmaErrorType reason);
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virtual void receiver_idle(void);
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virtual void transmission_complete(void);
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virtual void framing_error(void);
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virtual void overrun(void);
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virtual void rx_dma_transfer_complete(void);
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virtual void rx_dma_half_transfer(void);
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virtual void rx_dma_error(dma_helper::dma_error_type reason);
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virtual void tx_dma_transfer_complete(void);
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virtual void tx_dma_half_transfer(void);
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virtual void tx_dma_error(dma_helper::dma_error_type reason);
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char m_buffer[128];
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uint16_t m_used = 0;
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@ -1,96 +1,90 @@
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/*
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* ll_crchandler.h
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* ll_crc_handler.h
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*
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* Created on: Oct 26, 2019
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* Author: compi
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*/
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#pragma once
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#ifndef LL_CRCHANDLER_H_
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#define LL_CRCHANDLER_H_
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#include <f4ll/dma_helper.h>
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#include <f4ll/singleton.h>
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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extern "C" void _HandleCrcDmaIrq(void);
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namespace f4ll {
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class CrcHandler : public singleton<CrcHandler>
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class crc_handler : public singleton<crc_handler>
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{
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friend class singleton<CrcHandler>;
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friend class singleton<crc_handler>;
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public:
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struct ICallback
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struct icallback
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{
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
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virtual void crc_succeeded(uintptr_t callback_param, uint32_t crc, uint8_t task) = 0;
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virtual void crc_failed(uintptr_t callback_param, uint32_t crc, uint8_t task) = 0;
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};
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class SlotBase
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class slot_base
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{
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friend class CrcHandler;
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friend class crc_handler;
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public:
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struct CrcTask
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struct crc_task
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{
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void const *m_address; // changed to nullptr when execution starts
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uint16_t m_wordCount;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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uint16_t m_word_count;
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icallback *m_callback;
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uintptr_t m_callback_param;
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};
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private:
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SlotBase volatile *m_next = nullptr;
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uint8_t m_taskCount;
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slot_base volatile *m_next = nullptr;
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uint8_t m_task_count;
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virtual CrcTask volatile &operator[](int index) volatile = 0;
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virtual crc_task volatile &operator[](int index) volatile = 0;
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protected:
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SlotBase(unsigned int taskCount)
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: m_taskCount(taskCount)
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slot_base(unsigned int task_count)
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: m_task_count(task_count)
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{
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}
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SlotBase() = delete;
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SlotBase(SlotBase const &other) = delete;
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slot_base() = delete;
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slot_base(slot_base const &other) = delete;
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};
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template <uint8_t n> class Slot : public SlotBase
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template <uint8_t n> class slot : public slot_base
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{
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public:
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Slot()
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: SlotBase(n)
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slot()
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: slot_base(n)
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{
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}
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virtual CrcTask volatile &operator[](int index) volatile { return m_tasks[index]; }
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virtual crc_task volatile &operator[](int index) volatile { return m_tasks[index]; }
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private:
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Slot::CrcTask m_tasks[n];
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slot::crc_task m_tasks[n];
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};
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void AttachSlot(SlotBase &slot);
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bool Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam);
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uint32_t Compute(SlotBase &slot, uint8_t task, void const *address, uint16_t len);
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void attach_slot(slot_base &slot);
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bool enqueue(slot_base &slot, uint8_t task, void const *address, uint16_t len, icallback *cb, uintptr_t cb_param);
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uint32_t compute(slot_base &slot, uint8_t task, void const *address, uint16_t len);
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bool IsActive(SlotBase &slot, uint8_t task) const;
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bool IsQueued(SlotBase &slot, uint8_t task) const;
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bool IsRunning(SlotBase &slot, uint8_t task) const;
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bool is_active(slot_base &slot, uint8_t task) const;
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bool is_queued(slot_base &slot, uint8_t task) const;
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bool is_running(slot_base &slot, uint8_t task) const;
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void DmaTransferCompleted(void);
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void dma_transfer_completed(void);
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private:
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CrcHandler(DMA_TypeDef *dma, uint32_t stream);
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crc_handler(DMA_TypeDef *dma, uint32_t stream);
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friend void ::_HandleCrcDmaIrq(void);
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void StartNextTask(void);
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void WaitResults(SlotBase &slot, uint8_t task) const;
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void start_next_task(void);
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void wait_results(slot_base &slot, uint8_t task) const;
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dma_helper m_dma;
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SlotBase volatile *m_firstSlot = nullptr;
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SlotBase volatile *m_activeSlot = nullptr;
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slot_base volatile *m_first_slot = nullptr;
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slot_base volatile *m_active_slot = nullptr;
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int volatile m_activeTask;
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};
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} // namespace f4ll
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#endif /* LL_CRCHANDLER_H_ */
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dma_helper(DMA_TypeDef *dma, uint32_t stream);
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dma_helper(dma_helper const &base) = default;
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inline DMA_TypeDef *GetDma() const { return m_dma; }
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inline uint32_t GetStream() const { return m_stream; }
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inline volatile uint32_t *GetIsReg() const { return m_isReg; }
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inline volatile uint32_t *GetIfcReg() const { return m_ifcReg; }
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inline uint32_t GetFeMask() const { return m_FEMasks[m_stream]; }
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inline uint32_t GetDmeMask() const { return m_DMEMasks[m_stream]; }
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inline uint32_t GetTeMask() const { return m_TEMasks[m_stream]; }
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inline uint32_t GetHtMask() const { return m_HTMasks[m_stream]; }
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inline uint32_t GetTcMask() const { return m_TCMasks[m_stream]; }
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inline DMA_TypeDef *get_dma() const { return m_dma; }
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inline uint32_t get_stream() const { return m_stream; }
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inline volatile uint32_t *get_is_reg() const { return m_is_reg; }
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inline volatile uint32_t *get_ifc_reg() const { return m_ifc_reg; }
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inline uint32_t get_fe_mask() const { return m_fe_masks[m_stream]; }
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inline uint32_t get_dme_mask() const { return m_dme_masks[m_stream]; }
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inline uint32_t get_te_mask() const { return m_te_masks[m_stream]; }
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inline uint32_t get_ht_mask() const { return m_ht_masks[m_stream]; }
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inline uint32_t get_tc_mask() const { return m_tc_masks[m_stream]; }
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inline bool IsEnabledIt_HT() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TE() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TC() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_DME() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_FE() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
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inline bool is_enabled_it_ht() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
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inline bool is_enabled_it_te() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
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inline bool is_enabled_it_tc() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
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inline bool is_enabled_it_dme() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
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inline bool is_enabled_it_fe() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
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enum class DmaErrorType
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{
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Transfer,
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DirectMode,
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Fifo
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};
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enum class dma_error_type { transfer, direct_mode, fifo };
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private:
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DMA_TypeDef *m_dma;
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uint32_t m_stream;
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volatile uint32_t *m_isReg;
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volatile uint32_t *m_ifcReg;
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volatile uint32_t *m_is_reg;
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volatile uint32_t *m_ifc_reg;
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static const uint32_t m_FEMasks[8];
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static const uint32_t m_DMEMasks[8];
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static const uint32_t m_TEMasks[8];
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static const uint32_t m_HTMasks[8];
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static const uint32_t m_TCMasks[8];
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static const uint32_t m_fe_masks[8];
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static const uint32_t m_dme_masks[8];
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static const uint32_t m_te_masks[8];
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static const uint32_t m_ht_masks[8];
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static const uint32_t m_tc_masks[8];
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};
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} /* namespace f4ll */
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@ -4,27 +4,24 @@
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* Created on: Nov 4, 2019
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* Author: abody
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*/
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#pragma once
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#ifndef LL_MEMCPY_DMA_H_
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#define LL_MEMCPY_DMA_H_
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#include <f4ll/dma_helper.h>
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#include <f4ll/singleton.h>
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namespace f4ll {
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class MemcpyDma : public singleton<MemcpyDma>, private dma_helper
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class memcpy_dma : public singleton<memcpy_dma>, private dma_helper
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{
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friend class singleton<MemcpyDma>;
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friend class singleton<memcpy_dma>;
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public:
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void *Copy(void *dst, void const *src, uint16_t length);
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void DmaTransferCompleted();
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void *copy(void *dst, void const *src, uint16_t length);
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void dma_transfer_completed();
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private:
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MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
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memcpy_dma(DMA_TypeDef *dma, uint32_t stream);
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bool volatile m_busy = false;
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};
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} /* namespace f4ll */
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#endif /* LL_MEMCPY_DMA_H_ */
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@ -15,7 +15,7 @@ namespace f4ll {
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struct DMAINFO;
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class PacketUsart : public CrcHandler::ICallback, public usart_core
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class PacketUsart : public crc_handler::icallback, public usart_core
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{
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// friend class UsartCore;
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public:
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@ -56,9 +56,9 @@ public:
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virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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};
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// CRCHandler::ICallback interface functions
|
||||
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
|
||||
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
|
||||
// crc_handler::ICallback interface functions
|
||||
virtual void crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
|
||||
virtual void crc_failed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
|
||||
|
||||
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
|
||||
void SetupReceive(void);
|
||||
|
|
@ -83,16 +83,16 @@ private:
|
|||
void SwitchRxBuffers(void);
|
||||
|
||||
// UsartCore pure virtual function implementations
|
||||
virtual void ReceiverIdle(void);
|
||||
virtual void TransmissionComplete(void);
|
||||
virtual void FramingError(void);
|
||||
virtual void Overrun(void);
|
||||
virtual void RxDmaTransferComplete(void);
|
||||
virtual void RxDmaHalfTransfer(void);
|
||||
virtual void RxDmaError(dma_helper::DmaErrorType reason);
|
||||
virtual void TxDmaTransferComplete(void);
|
||||
virtual void TxDmaHalfTransfer(void);
|
||||
virtual void TxDmaError(dma_helper::DmaErrorType reason);
|
||||
virtual void receiver_idle(void);
|
||||
virtual void transmission_complete(void);
|
||||
virtual void framing_error(void);
|
||||
virtual void overrun(void);
|
||||
virtual void rx_dma_transfer_complete(void);
|
||||
virtual void rx_dma_half_transfer(void);
|
||||
virtual void rx_dma_error(dma_helper::dma_error_type reason);
|
||||
virtual void tx_dma_transfer_complete(void);
|
||||
virtual void tx_dma_half_transfer(void);
|
||||
virtual void tx_dma_error(dma_helper::dma_error_type reason);
|
||||
|
||||
struct Buffer
|
||||
{
|
||||
|
|
@ -111,7 +111,7 @@ private:
|
|||
Stats m_stats;
|
||||
bool m_rxBufferSelector = false;
|
||||
|
||||
CrcHandler::Slot<2> m_crcSlot;
|
||||
crc_handler::slot<2> m_crcSlot;
|
||||
IHsUsartCallback *m_userCallback = nullptr;
|
||||
uintptr_t m_userCallbackParam = 0;
|
||||
Buffer m_txBuffer;
|
||||
|
|
|
|||
|
|
@ -16,37 +16,37 @@ namespace f4ll {
|
|||
class usart_core
|
||||
{
|
||||
public:
|
||||
static inline void HandleUsartIrq(usart_core *_this) { _this->UsartIsr(); }
|
||||
static inline void HandleRxDmaIrq(usart_core *_this) { _this->RxDmaIsr(); }
|
||||
static inline void HandleTxDmaIrq(usart_core *_this) { _this->TxDmaIsr(); }
|
||||
static inline void usart_isr(usart_core *_this) { _this->usart_isr(); }
|
||||
static inline void rx_dma_isr(usart_core *_this) { _this->rx_dma_isr(); }
|
||||
static inline void tx_dma_isr(usart_core *_this) { _this->tx_dma_isr(); }
|
||||
|
||||
void SetupTransmit(void const *buffer, uint16_t length);
|
||||
void SetupReceive(void *buffer, uint16_t length);
|
||||
void setup_transmit(void const *buffer, uint16_t length);
|
||||
void setup_receive(void *buffer, uint16_t length);
|
||||
|
||||
protected:
|
||||
usart_core(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
|
||||
usart_core(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
|
||||
|
||||
USART_TypeDef *m_usart;
|
||||
dma_helper m_rxDma;
|
||||
dma_helper m_txDma;
|
||||
dma_helper m_rx_dma;
|
||||
dma_helper m_tx_dma;
|
||||
|
||||
private:
|
||||
virtual void ReceiverIdle(void) = 0;
|
||||
virtual void TransmissionComplete(void) = 0;
|
||||
virtual void FramingError(void) = 0;
|
||||
virtual void Overrun(void) = 0;
|
||||
virtual void receiver_idle(void) = 0;
|
||||
virtual void transmission_complete(void) = 0;
|
||||
virtual void framing_error(void) = 0;
|
||||
virtual void overrun(void) = 0;
|
||||
|
||||
virtual void RxDmaTransferComplete(void) = 0;
|
||||
virtual void RxDmaHalfTransfer(void) = 0;
|
||||
virtual void RxDmaError(dma_helper::DmaErrorType reason) = 0;
|
||||
virtual void rx_dma_transfer_complete(void) = 0;
|
||||
virtual void rx_dma_half_transfer(void) = 0;
|
||||
virtual void rx_dma_error(dma_helper::dma_error_type reason) = 0;
|
||||
|
||||
virtual void TxDmaTransferComplete(void) = 0;
|
||||
virtual void TxDmaHalfTransfer(void) = 0;
|
||||
virtual void TxDmaError(dma_helper::DmaErrorType reason) = 0;
|
||||
virtual void tx_dma_transfer_complete(void) = 0;
|
||||
virtual void tx_dma_half_transfer(void) = 0;
|
||||
virtual void tx_dma_error(dma_helper::dma_error_type reason) = 0;
|
||||
|
||||
void UsartIsr();
|
||||
void RxDmaIsr();
|
||||
void TxDmaIsr();
|
||||
void usart_isr();
|
||||
void rx_dma_isr();
|
||||
void tx_dma_isr();
|
||||
};
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
|
|
|||
|
|
@ -15,32 +15,32 @@ console_handler::console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_
|
|||
{
|
||||
}
|
||||
|
||||
void console_handler::ReceiverIdle(void) {}
|
||||
void console_handler::receiver_idle(void) {}
|
||||
|
||||
void console_handler::TransmissionComplete(void) {}
|
||||
void console_handler::transmission_complete(void) {}
|
||||
|
||||
void console_handler::FramingError(void) {}
|
||||
void console_handler::framing_error(void) {}
|
||||
|
||||
void console_handler::Overrun(void) {}
|
||||
void console_handler::overrun(void) {}
|
||||
|
||||
void console_handler::RxDmaTransferComplete(void) {}
|
||||
void console_handler::rx_dma_transfer_complete(void) {}
|
||||
|
||||
void console_handler::RxDmaHalfTransfer(void) {}
|
||||
void console_handler::rx_dma_half_transfer(void) {}
|
||||
|
||||
void console_handler::RxDmaError(dma_helper::DmaErrorType reason)
|
||||
void console_handler::rx_dma_error(dma_helper::dma_error_type reason)
|
||||
{
|
||||
(void)reason;
|
||||
}
|
||||
|
||||
void console_handler::TxDmaTransferComplete(void)
|
||||
void console_handler::tx_dma_transfer_complete(void)
|
||||
{
|
||||
LL_USART_EnableIT_TC(m_usart);
|
||||
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
|
||||
LL_DMA_DisableStream(m_tx_dma.get_dma(), m_tx_dma.get_stream());
|
||||
}
|
||||
|
||||
void console_handler::TxDmaHalfTransfer(void) {}
|
||||
void console_handler::tx_dma_half_transfer(void) {}
|
||||
|
||||
void console_handler::TxDmaError(dma_helper::DmaErrorType reason)
|
||||
void console_handler::tx_dma_error(dma_helper::dma_error_type reason)
|
||||
{
|
||||
(void)reason;
|
||||
}
|
||||
|
|
@ -73,7 +73,7 @@ void console_handler::PrintStats(uint8_t id, PacketUsart &usart)
|
|||
ADDINFO(buffer, " pmp: ", stats.premature_payload);
|
||||
buffer += strcpy_ex(buffer, "\r\n");
|
||||
|
||||
SetupTransmit(m_buffer, buffer - m_buffer + 1);
|
||||
setup_transmit(m_buffer, buffer - m_buffer + 1);
|
||||
}
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* ll_crchandler.cpp
|
||||
* ll_crc_handler.cpp
|
||||
*
|
||||
* Created on: Oct 26, 2019
|
||||
* Author: compi
|
||||
|
|
@ -8,151 +8,153 @@
|
|||
|
||||
namespace f4ll {
|
||||
|
||||
CrcHandler::CrcHandler(DMA_TypeDef *dma, uint32_t stream) : m_dma(dma, stream) {
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
LL_DMA_EnableIT_TE(dma, stream);
|
||||
LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
|
||||
crc_handler::crc_handler(DMA_TypeDef *dma, uint32_t stream)
|
||||
: m_dma(dma, stream)
|
||||
{
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
LL_DMA_EnableIT_TE(dma, stream);
|
||||
LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
|
||||
}
|
||||
|
||||
void CrcHandler::AttachSlot(SlotBase &slot) {
|
||||
for (unsigned int i = 0; i < slot.m_taskCount; ++i) {
|
||||
auto &task(slot[i]);
|
||||
task.m_address = nullptr;
|
||||
task.m_wordCount = 0;
|
||||
task.m_callback = nullptr;
|
||||
task.m_callbackParam = 0;
|
||||
}
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
slot.m_next = m_firstSlot;
|
||||
m_firstSlot = &slot;
|
||||
__set_PRIMASK(prim);
|
||||
}
|
||||
|
||||
bool CrcHandler::Enqueue(SlotBase &slot, uint8_t task, void const *address,
|
||||
uint16_t len, ICallback *cb, uintptr_t cbParam) {
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
bool immediate;
|
||||
|
||||
// TODO: do we need sanity check here? (is slot attached, is task in range,
|
||||
// etc...?)
|
||||
|
||||
while (IsActive(slot, task))
|
||||
;
|
||||
__disable_irq();
|
||||
immediate = m_activeSlot == nullptr;
|
||||
slot[task].m_address = (!immediate) ? address : nullptr;
|
||||
slot[task].m_wordCount = (len + 3) / 4;
|
||||
slot[task].m_callback = cb;
|
||||
slot[task].m_callbackParam = cbParam;
|
||||
if (immediate) {
|
||||
m_activeSlot = &slot;
|
||||
m_activeTask = task;
|
||||
}
|
||||
__set_PRIMASK(prim);
|
||||
|
||||
if (immediate) {
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(),
|
||||
(uint32_t)address);
|
||||
LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), (len + 3) / 4);
|
||||
LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
|
||||
}
|
||||
return immediate;
|
||||
}
|
||||
|
||||
bool CrcHandler::IsActive(SlotBase &slot, uint8_t task) const {
|
||||
return task < slot.m_taskCount && slot[task].m_wordCount != 0;
|
||||
}
|
||||
|
||||
bool CrcHandler::IsQueued(SlotBase &slot, uint8_t task) const {
|
||||
return task < slot.m_taskCount && slot[task].m_address != nullptr;
|
||||
}
|
||||
|
||||
bool CrcHandler::IsRunning(SlotBase &slot, uint8_t task) const {
|
||||
return task < slot.m_taskCount && slot[task].m_wordCount &&
|
||||
!slot[task].m_address;
|
||||
}
|
||||
|
||||
void CrcHandler::DmaTransferCompleted(void) {
|
||||
if (*m_dma.GetIsReg() & m_dma.GetTcMask()) { // DMA transfer complete
|
||||
*m_dma.GetIfcReg() = m_dma.GetTcMask();
|
||||
LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
|
||||
if (m_activeSlot) {
|
||||
if ((*m_activeSlot)[m_activeTask].m_callback)
|
||||
(*m_activeSlot)[m_activeTask].m_callback->CrcSucceeded(
|
||||
(*m_activeSlot)[m_activeTask].m_callbackParam, CRC->DR,
|
||||
m_activeTask);
|
||||
else if ((*m_activeSlot)[m_activeTask].m_callbackParam)
|
||||
*reinterpret_cast<uint32_t *>(
|
||||
(*m_activeSlot)[m_activeTask].m_callbackParam) = CRC->DR;
|
||||
void crc_handler::attach_slot(slot_base &slot)
|
||||
{
|
||||
for (unsigned int i = 0; i < slot.m_task_count; ++i) {
|
||||
auto &task(slot[i]);
|
||||
task.m_address = nullptr;
|
||||
task.m_word_count = 0;
|
||||
task.m_callback = nullptr;
|
||||
task.m_callback_param = 0;
|
||||
}
|
||||
} else if (*m_dma.GetIsReg() & m_dma.GetTeMask()) { // DMA transfer error
|
||||
*m_dma.GetIfcReg() = m_dma.GetTeMask();
|
||||
LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
|
||||
if (m_activeSlot) {
|
||||
if ((*m_activeSlot)[m_activeTask].m_callback)
|
||||
(*m_activeSlot)[m_activeTask].m_callback->CrcFailed(
|
||||
(*m_activeSlot)[m_activeTask].m_callbackParam, CRC->DR,
|
||||
m_activeTask);
|
||||
else if ((*m_activeSlot)[m_activeTask].m_callbackParam)
|
||||
*reinterpret_cast<uint32_t *>(
|
||||
(*m_activeSlot)[m_activeTask].m_callbackParam) = -1;
|
||||
}
|
||||
}
|
||||
(*m_activeSlot)[m_activeTask].m_callback = nullptr;
|
||||
(*m_activeSlot)[m_activeTask].m_callbackParam = 0;
|
||||
(*m_activeSlot)[m_activeTask].m_wordCount = 0;
|
||||
StartNextTask();
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
slot.m_next = m_first_slot;
|
||||
m_first_slot = &slot;
|
||||
__set_PRIMASK(prim);
|
||||
}
|
||||
|
||||
void CrcHandler::StartNextTask(void) {
|
||||
bool moreTasks;
|
||||
uint8_t index = 0;
|
||||
bool crc_handler::enqueue(slot_base &slot, uint8_t task, void const *address, uint16_t len, icallback *cb, uintptr_t cbParam)
|
||||
{
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
bool immediate;
|
||||
|
||||
do {
|
||||
SlotBase volatile *slot = m_firstSlot;
|
||||
moreTasks = false;
|
||||
while (slot) {
|
||||
if (index < slot->m_taskCount) {
|
||||
if ((*slot)[index].m_address) {
|
||||
m_activeSlot = slot;
|
||||
m_activeTask = index;
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(
|
||||
m_dma.GetDma(), m_dma.GetStream(),
|
||||
reinterpret_cast<uint32_t>((*slot)[index].m_address));
|
||||
LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(),
|
||||
(*slot)[index].m_wordCount);
|
||||
LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
|
||||
(*slot)[index].m_address = nullptr; // marking as started
|
||||
return;
|
||||
// TODO: do we need sanity check here? (is slot attached, is task in range,
|
||||
// etc...?)
|
||||
|
||||
while (is_active(slot, task))
|
||||
;
|
||||
__disable_irq();
|
||||
immediate = m_active_slot == nullptr;
|
||||
slot[task].m_address = (!immediate) ? address : nullptr;
|
||||
slot[task].m_word_count = (len + 3) / 4;
|
||||
slot[task].m_callback = cb;
|
||||
slot[task].m_callback_param = cbParam;
|
||||
if (immediate) {
|
||||
m_active_slot = &slot;
|
||||
m_activeTask = task;
|
||||
}
|
||||
__set_PRIMASK(prim);
|
||||
|
||||
if (immediate) {
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(m_dma.get_dma(), m_dma.get_stream(), (uint32_t)address);
|
||||
LL_DMA_SetDataLength(m_dma.get_dma(), m_dma.get_stream(), (len + 3) / 4);
|
||||
LL_DMA_EnableStream(m_dma.get_dma(), m_dma.get_stream());
|
||||
}
|
||||
return immediate;
|
||||
}
|
||||
|
||||
bool crc_handler::is_active(slot_base &slot, uint8_t task) const
|
||||
{
|
||||
return task < slot.m_task_count && slot[task].m_word_count != 0;
|
||||
}
|
||||
|
||||
bool crc_handler::is_queued(slot_base &slot, uint8_t task) const
|
||||
{
|
||||
return task < slot.m_task_count && slot[task].m_address != nullptr;
|
||||
}
|
||||
|
||||
bool crc_handler::is_running(slot_base &slot, uint8_t task) const
|
||||
{
|
||||
return task < slot.m_task_count && slot[task].m_word_count && !slot[task].m_address;
|
||||
}
|
||||
|
||||
void crc_handler::dma_transfer_completed(void)
|
||||
{
|
||||
if (*m_dma.get_is_reg() & m_dma.get_tc_mask()) { // DMA transfer complete
|
||||
*m_dma.get_ifc_reg() = m_dma.get_tc_mask();
|
||||
LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream());
|
||||
if (m_active_slot) {
|
||||
if ((*m_active_slot)[m_activeTask].m_callback) {
|
||||
(*m_active_slot)[m_activeTask].m_callback->crc_succeeded(
|
||||
(*m_active_slot)[m_activeTask].m_callback_param, CRC->DR, m_activeTask);
|
||||
} else if ((*m_active_slot)[m_activeTask].m_callback_param) {
|
||||
*reinterpret_cast<uint32_t *>((*m_active_slot)[m_activeTask].m_callback_param) = CRC->DR;
|
||||
}
|
||||
}
|
||||
} else if (*m_dma.get_is_reg() & m_dma.get_te_mask()) { // DMA transfer error
|
||||
*m_dma.get_ifc_reg() = m_dma.get_te_mask();
|
||||
LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream());
|
||||
if (m_active_slot) {
|
||||
if ((*m_active_slot)[m_activeTask].m_callback) {
|
||||
(*m_active_slot)[m_activeTask].m_callback->crc_failed(
|
||||
(*m_active_slot)[m_activeTask].m_callback_param, CRC->DR, m_activeTask);
|
||||
} else if ((*m_active_slot)[m_activeTask].m_callback_param) {
|
||||
*reinterpret_cast<uint32_t *>((*m_active_slot)[m_activeTask].m_callback_param) = -1;
|
||||
}
|
||||
}
|
||||
if (index + 1 < slot->m_taskCount)
|
||||
moreTasks = true;
|
||||
}
|
||||
slot = slot->m_next;
|
||||
}
|
||||
++index;
|
||||
} while (moreTasks);
|
||||
m_activeSlot = nullptr;
|
||||
(*m_active_slot)[m_activeTask].m_callback = nullptr;
|
||||
(*m_active_slot)[m_activeTask].m_callback_param = 0;
|
||||
(*m_active_slot)[m_activeTask].m_word_count = 0;
|
||||
start_next_task();
|
||||
}
|
||||
|
||||
void CrcHandler::WaitResults(SlotBase &slot, uint8_t task) const {
|
||||
while (IsQueued(slot, task))
|
||||
;
|
||||
while (IsActive(slot, task))
|
||||
;
|
||||
void crc_handler::start_next_task(void)
|
||||
{
|
||||
bool moreTasks;
|
||||
uint8_t index = 0;
|
||||
|
||||
do {
|
||||
slot_base volatile *slot = m_first_slot;
|
||||
moreTasks = false;
|
||||
while (slot) {
|
||||
if (index < slot->m_task_count) {
|
||||
if ((*slot)[index].m_address) {
|
||||
m_active_slot = slot;
|
||||
m_activeTask = index;
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(m_dma.get_dma(), m_dma.get_stream(), reinterpret_cast<uint32_t>((*slot)[index].m_address));
|
||||
LL_DMA_SetDataLength(m_dma.get_dma(), m_dma.get_stream(), (*slot)[index].m_word_count);
|
||||
LL_DMA_EnableStream(m_dma.get_dma(), m_dma.get_stream());
|
||||
(*slot)[index].m_address = nullptr; // marking as started
|
||||
return;
|
||||
}
|
||||
if (index + 1 < slot->m_task_count) {
|
||||
moreTasks = true;
|
||||
}
|
||||
}
|
||||
slot = slot->m_next;
|
||||
}
|
||||
++index;
|
||||
} while (moreTasks);
|
||||
m_active_slot = nullptr;
|
||||
}
|
||||
|
||||
uint32_t CrcHandler::Compute(SlotBase &slot, uint8_t task, void const *address,
|
||||
uint16_t len) {
|
||||
uint32_t result;
|
||||
Enqueue(slot, task, address, len, nullptr,
|
||||
reinterpret_cast<uintptr_t>(&result));
|
||||
while (IsActive(slot, task))
|
||||
;
|
||||
return result;
|
||||
void crc_handler::wait_results(slot_base &slot, uint8_t task) const
|
||||
{
|
||||
while (is_queued(slot, task))
|
||||
;
|
||||
while (is_active(slot, task))
|
||||
;
|
||||
}
|
||||
|
||||
uint32_t crc_handler::compute(slot_base &slot, uint8_t task, void const *address, uint16_t len)
|
||||
{
|
||||
uint32_t result;
|
||||
enqueue(slot, task, address, len, nullptr, reinterpret_cast<uintptr_t>(&result));
|
||||
while (is_active(slot, task))
|
||||
;
|
||||
return result;
|
||||
}
|
||||
|
||||
} // namespace f4ll
|
||||
|
|
|
|||
|
|
@ -9,24 +9,24 @@ q * ll_dmahelper.cpp
|
|||
|
||||
namespace f4ll {
|
||||
|
||||
const uint32_t dma_helper::m_FEMasks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3,
|
||||
DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
|
||||
const uint32_t dma_helper::m_DMEMasks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3,
|
||||
DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
|
||||
const uint32_t dma_helper::m_TEMasks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3,
|
||||
DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
|
||||
const uint32_t dma_helper::m_HTMasks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3,
|
||||
DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
|
||||
const uint32_t dma_helper::m_TCMasks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3,
|
||||
DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
|
||||
const uint32_t dma_helper::m_fe_masks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3,
|
||||
DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
|
||||
const uint32_t dma_helper::m_dme_masks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3,
|
||||
DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
|
||||
const uint32_t dma_helper::m_te_masks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3,
|
||||
DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
|
||||
const uint32_t dma_helper::m_ht_masks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3,
|
||||
DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
|
||||
const uint32_t dma_helper::m_tc_masks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3,
|
||||
DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
|
||||
|
||||
dma_helper::dma_helper(DMA_TypeDef *dma, uint32_t stream)
|
||||
: m_dma(dma),
|
||||
m_stream(stream),
|
||||
m_isReg(
|
||||
m_is_reg(
|
||||
(dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR)
|
||||
: ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR)),
|
||||
m_ifcReg(
|
||||
m_ifc_reg(
|
||||
(dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR)
|
||||
: ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR))
|
||||
{
|
||||
|
|
|
|||
|
|
@ -9,29 +9,29 @@
|
|||
|
||||
namespace f4ll {
|
||||
|
||||
MemcpyDma::MemcpyDma(DMA_TypeDef *dma, uint32_t stream)
|
||||
memcpy_dma::memcpy_dma(DMA_TypeDef *dma, uint32_t stream)
|
||||
: dma_helper(dma, stream)
|
||||
{
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
}
|
||||
|
||||
void *MemcpyDma::Copy(void *dst, void const *src, uint16_t length)
|
||||
void *memcpy_dma::copy(void *dst, void const *src, uint16_t length)
|
||||
{
|
||||
LL_DMA_SetM2MSrcAddress(GetDma(), GetStream(), (uint32_t)src);
|
||||
LL_DMA_SetM2MDstAddress(GetDma(), GetStream(), (uint32_t)dst);
|
||||
LL_DMA_SetDataLength(GetDma(), GetStream(), (length + 3) / 4);
|
||||
LL_DMA_SetM2MSrcAddress(get_dma(), get_stream(), (uint32_t)src);
|
||||
LL_DMA_SetM2MDstAddress(get_dma(), get_stream(), (uint32_t)dst);
|
||||
LL_DMA_SetDataLength(get_dma(), get_stream(), (length + 3) / 4);
|
||||
m_busy = 1;
|
||||
LL_DMA_EnableStream(GetDma(), GetStream());
|
||||
LL_DMA_EnableStream(get_dma(), get_stream());
|
||||
while (m_busy)
|
||||
;
|
||||
return dst;
|
||||
}
|
||||
|
||||
void MemcpyDma::DmaTransferCompleted()
|
||||
void memcpy_dma::dma_transfer_completed()
|
||||
{
|
||||
if (*GetIsReg() & GetTcMask()) { // DMA transfer complete
|
||||
*GetIfcReg() = GetTcMask();
|
||||
LL_DMA_DisableStream(GetDma(), GetStream());
|
||||
if (*get_is_reg() & get_tc_mask()) { // DMA transfer complete
|
||||
*get_ifc_reg() = get_tc_mask();
|
||||
LL_DMA_DisableStream(get_dma(), get_stream());
|
||||
m_busy = 0;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ template <typename T> static inline T RoundUpTo4(T input)
|
|||
PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
: usart_core(usart, dma, streamRx, streamTx)
|
||||
{
|
||||
CrcHandler::instance().AttachSlot(m_crcSlot);
|
||||
crc_handler::instance().attach_slot(m_crcSlot);
|
||||
LL_USART_EnableIT_IDLE(usart);
|
||||
LL_USART_EnableIT_ERROR(usart);
|
||||
}
|
||||
|
|
@ -46,14 +46,14 @@ void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFo
|
|||
m_txBuffer.busy = true;
|
||||
m_txBuffer.error = false;
|
||||
|
||||
CrcHandler::instance().Enqueue(
|
||||
crc_handler::instance().enqueue(
|
||||
m_crcSlot, 0, &m_txBuffer.packet, sizeof(PacketHeader) + payloadLength, nullptr,
|
||||
reinterpret_cast<uintptr_t>(m_txBuffer.packet.payload + payloadLength));
|
||||
|
||||
while (waitForCrcQueue && CrcHandler::instance().IsQueued(m_crcSlot, 0))
|
||||
while (waitForCrcQueue && crc_handler::instance().is_queued(m_crcSlot, 0))
|
||||
;
|
||||
|
||||
SetupTransmit(&m_txBuffer.packet, m_txBuffer.requestedLength);
|
||||
setup_transmit(&m_txBuffer.packet, m_txBuffer.requestedLength);
|
||||
|
||||
++m_stats.sent;
|
||||
}
|
||||
|
|
@ -61,49 +61,49 @@ void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFo
|
|||
void PacketUsart::SetupReceive()
|
||||
{
|
||||
m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
|
||||
usart_core::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
|
||||
usart_core::setup_receive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
|
||||
}
|
||||
|
||||
//////////////////////////////////////
|
||||
// UsartCore pure virtual functions //
|
||||
//////////////////////////////////////
|
||||
|
||||
void PacketUsart::ReceiverIdle(void)
|
||||
void PacketUsart::receiver_idle(void)
|
||||
{
|
||||
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rx_dma.get_dma(), m_rx_dma.get_stream());
|
||||
|
||||
if (rcvdLen >= sizeof(PacketHeader)) {
|
||||
if (CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
|
||||
if (rcvdLen >= sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength) +
|
||||
sizeof(uint32_t)) {
|
||||
LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
LL_DMA_DisableStream(m_rx_dma.get_dma(), m_rx_dma.get_stream());
|
||||
} else {
|
||||
++m_stats.premature_payload;
|
||||
}
|
||||
} else {
|
||||
m_rxBuffers[m_rxBufferSelector].error = 1;
|
||||
LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
LL_DMA_DisableStream(m_rx_dma.get_dma(), m_rx_dma.get_stream());
|
||||
}
|
||||
} else {
|
||||
++m_stats.premature_hdr;
|
||||
}
|
||||
}
|
||||
|
||||
void PacketUsart::TransmissionComplete(void)
|
||||
void PacketUsart::transmission_complete(void)
|
||||
{
|
||||
LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(m_usart);
|
||||
m_txBuffer.busy = 0;
|
||||
}
|
||||
|
||||
void PacketUsart::FramingError(void) {}
|
||||
void PacketUsart::framing_error(void) {}
|
||||
|
||||
void PacketUsart::Overrun(void) {}
|
||||
void PacketUsart::overrun(void) {}
|
||||
|
||||
void PacketUsart::RxDmaTransferComplete(void)
|
||||
void PacketUsart::rx_dma_transfer_complete(void)
|
||||
{
|
||||
if (CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
|
||||
CrcHandler::instance().Enqueue(
|
||||
crc_handler::instance().enqueue(
|
||||
m_crcSlot, 1, &m_rxBuffers[m_rxBufferSelector].packet,
|
||||
sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength), this,
|
||||
m_rxBufferSelector);
|
||||
|
|
@ -114,9 +114,9 @@ void PacketUsart::RxDmaTransferComplete(void)
|
|||
SwitchRxBuffers();
|
||||
}
|
||||
|
||||
void PacketUsart::RxDmaHalfTransfer(void) {}
|
||||
void PacketUsart::rx_dma_half_transfer(void) {}
|
||||
|
||||
void PacketUsart::RxDmaError(dma_helper::DmaErrorType reason)
|
||||
void PacketUsart::rx_dma_error(dma_helper::dma_error_type reason)
|
||||
{
|
||||
(void)reason;
|
||||
|
||||
|
|
@ -125,15 +125,15 @@ void PacketUsart::RxDmaError(dma_helper::DmaErrorType reason)
|
|||
SwitchRxBuffers();
|
||||
}
|
||||
|
||||
void PacketUsart::TxDmaTransferComplete(void)
|
||||
void PacketUsart::tx_dma_transfer_complete(void)
|
||||
{
|
||||
LL_USART_EnableIT_TC(m_usart);
|
||||
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
|
||||
LL_DMA_DisableStream(m_tx_dma.get_dma(), m_tx_dma.get_stream());
|
||||
}
|
||||
|
||||
void PacketUsart::TxDmaHalfTransfer(void) {}
|
||||
void PacketUsart::tx_dma_half_transfer(void) {}
|
||||
|
||||
void PacketUsart::TxDmaError(dma_helper::DmaErrorType reason)
|
||||
void PacketUsart::tx_dma_error(dma_helper::dma_error_type reason)
|
||||
{
|
||||
(void)reason;
|
||||
|
||||
|
|
@ -174,10 +174,10 @@ void PacketUsart::SwitchRxBuffers(void)
|
|||
}
|
||||
|
||||
///////////////////////////
|
||||
// CrcHandler::ICallback //
|
||||
// crc_handler::ICallback //
|
||||
///////////////////////////
|
||||
|
||||
void PacketUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
void PacketUsart::crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
{
|
||||
(void)task;
|
||||
|
||||
|
|
@ -194,7 +194,7 @@ void PacketUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t ta
|
|||
}
|
||||
}
|
||||
|
||||
void PacketUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
void PacketUsart::crc_failed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
{
|
||||
(void)crc;
|
||||
(void)task;
|
||||
|
|
|
|||
|
|
@ -11,16 +11,18 @@ namespace f4ll {
|
|||
|
||||
usart_core::usart_core(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
: m_usart(usart),
|
||||
m_rxDma(dma, streamRx),
|
||||
m_txDma(dma, streamTx)
|
||||
m_rx_dma(dma, streamRx),
|
||||
m_tx_dma(dma, streamTx)
|
||||
{
|
||||
uint32_t status = usart->SR;
|
||||
volatile uint32_t tmpreg = usart->DR; // clearing some of the error/status bits in the USART
|
||||
(void)tmpreg;
|
||||
(void)status;
|
||||
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTcMask() | m_rxDma.GetHtMask() | m_txDma.GetTeMask() | m_rxDma.GetFeMask() | m_rxDma.GetDmeMask();
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask() | m_rxDma.GetHtMask() | m_rxDma.GetTeMask() | m_rxDma.GetFeMask() | m_rxDma.GetDmeMask();
|
||||
*m_tx_dma.get_ifc_reg() =
|
||||
m_tx_dma.get_tc_mask() | m_rx_dma.get_ht_mask() | m_tx_dma.get_te_mask() | m_rx_dma.get_fe_mask() | m_rx_dma.get_dme_mask();
|
||||
*m_rx_dma.get_ifc_reg() =
|
||||
m_rx_dma.get_tc_mask() | m_rx_dma.get_ht_mask() | m_rx_dma.get_te_mask() | m_rx_dma.get_fe_mask() | m_rx_dma.get_dme_mask();
|
||||
|
||||
LL_DMA_EnableIT_TC(dma, streamRx);
|
||||
LL_DMA_EnableIT_TE(dma, streamRx);
|
||||
|
|
@ -28,7 +30,7 @@ usart_core::usart_core(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx
|
|||
LL_DMA_EnableIT_TE(dma, streamTx);
|
||||
}
|
||||
|
||||
void usart_core::UsartIsr()
|
||||
void usart_core::usart_isr()
|
||||
{
|
||||
uint32_t status = m_usart->SR;
|
||||
volatile uint32_t tmpreg = m_usart->DR; // clearing some of the error/status bits in the HW
|
||||
|
|
@ -36,108 +38,108 @@ void usart_core::UsartIsr()
|
|||
|
||||
if (LL_USART_IsEnabledIT_TC(m_usart) && LL_USART_IsActiveFlag_TC(m_usart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(m_usart);
|
||||
TransmissionComplete();
|
||||
transmission_complete();
|
||||
}
|
||||
if (LL_USART_IsEnabledIT_IDLE(m_usart) && (status & USART_SR_IDLE)) {
|
||||
ReceiverIdle();
|
||||
receiver_idle();
|
||||
}
|
||||
if (LL_USART_IsEnabledIT_ERROR(m_usart)) {
|
||||
if (status & USART_SR_FE) {
|
||||
FramingError();
|
||||
framing_error();
|
||||
}
|
||||
if (status & USART_SR_ORE) {
|
||||
Overrun();
|
||||
overrun();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void usart_core::RxDmaIsr()
|
||||
void usart_core::rx_dma_isr()
|
||||
{
|
||||
if (*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
|
||||
if (m_rxDma.IsEnabledIt_TC()) {
|
||||
RxDmaTransferComplete();
|
||||
if (*m_rx_dma.get_is_reg() & m_rx_dma.get_tc_mask()) {
|
||||
*m_rx_dma.get_ifc_reg() = m_rx_dma.get_tc_mask();
|
||||
if (m_rx_dma.is_enabled_it_tc()) {
|
||||
rx_dma_transfer_complete();
|
||||
}
|
||||
}
|
||||
if (*m_rxDma.GetIsReg() & m_rxDma.GetHtMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetHtMask();
|
||||
if (m_rxDma.IsEnabledIt_HT()) {
|
||||
RxDmaHalfTransfer();
|
||||
if (*m_rx_dma.get_is_reg() & m_rx_dma.get_ht_mask()) {
|
||||
*m_rx_dma.get_ifc_reg() = m_rx_dma.get_ht_mask();
|
||||
if (m_rx_dma.is_enabled_it_ht()) {
|
||||
rx_dma_half_transfer();
|
||||
}
|
||||
}
|
||||
if (*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
|
||||
if (m_rxDma.IsEnabledIt_TE()) {
|
||||
RxDmaError(dma_helper::DmaErrorType::Transfer);
|
||||
if (*m_rx_dma.get_is_reg() & m_rx_dma.get_te_mask()) {
|
||||
*m_rx_dma.get_ifc_reg() = m_rx_dma.get_te_mask();
|
||||
if (m_rx_dma.is_enabled_it_te()) {
|
||||
rx_dma_error(dma_helper::dma_error_type::transfer);
|
||||
}
|
||||
}
|
||||
if (*m_rxDma.GetIsReg() & m_rxDma.GetFeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetFeMask();
|
||||
if (m_rxDma.IsEnabledIt_FE()) {
|
||||
RxDmaError(dma_helper::DmaErrorType::Fifo);
|
||||
if (*m_rx_dma.get_is_reg() & m_rx_dma.get_fe_mask()) {
|
||||
*m_rx_dma.get_ifc_reg() = m_rx_dma.get_fe_mask();
|
||||
if (m_rx_dma.is_enabled_it_fe()) {
|
||||
rx_dma_error(dma_helper::dma_error_type::fifo);
|
||||
}
|
||||
}
|
||||
if (*m_rxDma.GetIsReg() & m_rxDma.GetDmeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetDmeMask();
|
||||
if (m_rxDma.IsEnabledIt_DME()) {
|
||||
RxDmaError(dma_helper::DmaErrorType::DirectMode);
|
||||
if (*m_rx_dma.get_is_reg() & m_rx_dma.get_dme_mask()) {
|
||||
*m_rx_dma.get_ifc_reg() = m_rx_dma.get_dme_mask();
|
||||
if (m_rx_dma.is_enabled_it_dme()) {
|
||||
rx_dma_error(dma_helper::dma_error_type::direct_mode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void usart_core::TxDmaIsr()
|
||||
void usart_core::tx_dma_isr()
|
||||
{
|
||||
if (*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
|
||||
if (m_txDma.IsEnabledIt_TC()) {
|
||||
TxDmaTransferComplete();
|
||||
if (*m_tx_dma.get_is_reg() & m_tx_dma.get_tc_mask()) { // DMA transfer complete
|
||||
*m_tx_dma.get_ifc_reg() = m_tx_dma.get_tc_mask();
|
||||
if (m_tx_dma.is_enabled_it_tc()) {
|
||||
tx_dma_transfer_complete();
|
||||
}
|
||||
}
|
||||
if (*m_txDma.GetIsReg() & m_txDma.GetHtMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetHtMask();
|
||||
if (m_txDma.IsEnabledIt_HT()) {
|
||||
TxDmaHalfTransfer();
|
||||
if (*m_tx_dma.get_is_reg() & m_tx_dma.get_ht_mask()) {
|
||||
*m_tx_dma.get_ifc_reg() = m_tx_dma.get_ht_mask();
|
||||
if (m_tx_dma.is_enabled_it_ht()) {
|
||||
tx_dma_half_transfer();
|
||||
}
|
||||
}
|
||||
if (*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
|
||||
if (m_txDma.IsEnabledIt_TE()) {
|
||||
TxDmaError(dma_helper::DmaErrorType::Transfer);
|
||||
if (*m_tx_dma.get_is_reg() & m_tx_dma.get_te_mask()) {
|
||||
*m_tx_dma.get_ifc_reg() = m_tx_dma.get_te_mask();
|
||||
if (m_tx_dma.is_enabled_it_te()) {
|
||||
tx_dma_error(dma_helper::dma_error_type::transfer);
|
||||
}
|
||||
}
|
||||
if (*m_txDma.GetIsReg() & m_txDma.GetFeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
|
||||
if (m_txDma.IsEnabledIt_FE()) {
|
||||
TxDmaError(dma_helper::DmaErrorType::Fifo);
|
||||
if (*m_tx_dma.get_is_reg() & m_tx_dma.get_fe_mask()) {
|
||||
*m_tx_dma.get_ifc_reg() = m_tx_dma.get_fe_mask();
|
||||
if (m_tx_dma.is_enabled_it_fe()) {
|
||||
tx_dma_error(dma_helper::dma_error_type::fifo);
|
||||
}
|
||||
}
|
||||
if (*m_txDma.GetIsReg() & m_txDma.GetDmeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
|
||||
if (m_txDma.IsEnabledIt_DME()) {
|
||||
TxDmaError(dma_helper::DmaErrorType::DirectMode);
|
||||
if (*m_tx_dma.get_is_reg() & m_tx_dma.get_dme_mask()) {
|
||||
*m_tx_dma.get_ifc_reg() = m_tx_dma.get_dme_mask();
|
||||
if (m_tx_dma.is_enabled_it_dme()) {
|
||||
tx_dma_error(dma_helper::dma_error_type::direct_mode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void usart_core::SetupTransmit(void const *buffer, uint16_t length)
|
||||
void usart_core::setup_transmit(void const *buffer, uint16_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(
|
||||
m_txDma.GetDma(), m_txDma.GetStream(), reinterpret_cast<uint32_t>(buffer), LL_USART_DMA_GetRegAddr(m_usart),
|
||||
m_tx_dma.get_dma(), m_tx_dma.get_stream(), reinterpret_cast<uint32_t>(buffer), LL_USART_DMA_GetRegAddr(m_usart),
|
||||
LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_SetDataLength(m_txDma.GetDma(), m_txDma.GetStream(), length);
|
||||
LL_DMA_SetDataLength(m_tx_dma.get_dma(), m_tx_dma.get_stream(), length);
|
||||
LL_USART_EnableDMAReq_TX(m_usart);
|
||||
LL_DMA_EnableStream(m_txDma.GetDma(), m_txDma.GetStream());
|
||||
LL_DMA_EnableStream(m_tx_dma.get_dma(), m_tx_dma.get_stream());
|
||||
}
|
||||
|
||||
void usart_core::SetupReceive(void *buffer, uint16_t length)
|
||||
void usart_core::setup_receive(void *buffer, uint16_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(
|
||||
m_rxDma.GetDma(), m_rxDma.GetStream(), LL_USART_DMA_GetRegAddr(m_usart), reinterpret_cast<uint32_t>(buffer),
|
||||
m_rx_dma.get_dma(), m_rx_dma.get_stream(), LL_USART_DMA_GetRegAddr(m_usart), reinterpret_cast<uint32_t>(buffer),
|
||||
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
||||
LL_DMA_SetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream(), length);
|
||||
LL_DMA_SetDataLength(m_rx_dma.get_dma(), m_rx_dma.get_stream(), length);
|
||||
LL_USART_EnableDMAReq_RX(m_usart);
|
||||
LL_USART_ClearFlag_ORE(m_usart);
|
||||
LL_DMA_EnableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
LL_DMA_EnableStream(m_rx_dma.get_dma(), m_rx_dma.get_stream());
|
||||
}
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue