C++ build fixed, C dropped
This commit is contained in:
parent
c439c48643
commit
f26710a667
23 changed files with 50 additions and 1062 deletions
15
.cproject
15
.cproject
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@ -10,6 +10,7 @@
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<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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</extensions>
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</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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@ -40,6 +41,7 @@
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<listOptionValue builtIn="false" value="DEBUG"/>
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<listOptionValue builtIn="false" value="STM32F407xx"/>
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<listOptionValue builtIn="false" value="HAVE_CONFIG"/>
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<listOptionValue builtIn="false" value="USE_CPLUSPLUS"/>
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</option>
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.410582808" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
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<listOptionValue builtIn="false" value="../Inc"/>
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@ -73,6 +75,7 @@
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<listOptionValue builtIn="false" value="DEBUG"/>
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<listOptionValue builtIn="false" value="STM32F407xx"/>
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<listOptionValue builtIn="false" value="HAVE_CONFIG"/>
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<listOptionValue builtIn="false" value="USE_CPLUSPLUS"/>
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</option>
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<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.languagestandard.1833413246" name="Language standard" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.languagestandard" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.languagestandard.value.isocpp14" valueType="enumerated"/>
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<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.1377090173" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp"/>
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@ -106,14 +109,13 @@
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</toolChain>
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</folderInfo>
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<sourceEntries>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="App"/>
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<entry excluding="application.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="App"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Lib"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
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<entry excluding="stm32f4xx_it.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="components/f4ll/src"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="components/f4ll_c/src"/>
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</sourceEntries>
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</configuration>
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</storageModule>
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@ -128,6 +130,7 @@
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<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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</extensions>
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</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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@ -158,7 +161,7 @@
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<listOptionValue builtIn="false" value="DEBUG"/>
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<listOptionValue builtIn="false" value="STM32F407xx"/>
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<listOptionValue builtIn="false" value="HAVE_CONFIG"/>
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<listOptionValue builtIn="false" value="ENABLE_DIAG"/>
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<listOptionValue builtIn="false" value="USE_CPLUSPLUS"/>
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</option>
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.941145715" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
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<listOptionValue builtIn="false" value="../Inc"/>
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@ -192,7 +195,7 @@
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<listOptionValue builtIn="false" value="DEBUG"/>
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<listOptionValue builtIn="false" value="STM32F407xx"/>
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<listOptionValue builtIn="false" value="HAVE_CONFIG"/>
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<listOptionValue builtIn="false" value="ENABLE_DIAG"/>
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<listOptionValue builtIn="false" value="USE_CPLUSPLUS"/>
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</option>
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<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.687772733" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp"/>
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</tool>
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@ -222,14 +225,13 @@
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</toolChain>
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</folderInfo>
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<sourceEntries>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="App"/>
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<entry excluding="application.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="App"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Lib"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
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<entry excluding="stm32f4xx_it.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="components/f4ll/src"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="components/f4ll_c/src"/>
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</sourceEntries>
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</configuration>
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</storageModule>
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@ -270,7 +272,6 @@
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="App"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Lib"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="components/f4ll/src"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="components/f4ll_c/src"/>
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</sourceEntries>
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</configuration>
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</storageModule>
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@ -1,109 +0,0 @@
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#include <string.h>
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#include <stdlib.h>
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#include "application.h"
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#include "globals.h"
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#include "f4ll_c/strutil.h"
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#include "diag.h"
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#include "f4ll_c/usart_handler.h"
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#include "f4ll_c/crc_handler.h"
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#include "f4ll_c/console_handler.h"
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#include "f4ll_c/memcpy_dma.h"
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#ifndef USE_CPLUSPLUS
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#define PACKAGE_DELAY_MS 0
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#define STATS_DELAY_MS 1000
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// USART DMA RX TX
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// 1 2 2 7
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// 2 1 5 6
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// 3 1 1 3
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// 6 2 1 6
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// console USART
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// 4 1 2 4
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void MainLoop()
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{
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uint8_t const text2Send[] __attribute__((aligned(4))) =
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"Megszentsegtelenithetetlensegeskedeseitekert\r\n"
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"--------------------------------------------\r\n\0\0\0";
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struct initdata_t {
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USART_TypeDef* uart;
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DMA_TypeDef* dma;
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uint32_t stream_rx;
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uint32_t stream_tx;
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} static const initdata[] = {
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{ USART1, DMA2, LL_DMA_STREAM_2, LL_DMA_STREAM_7 },
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{ USART2, DMA1, LL_DMA_STREAM_5, LL_DMA_STREAM_6 },
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{ USART3, DMA1, LL_DMA_STREAM_1, LL_DMA_STREAM_3 },
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{ USART6, DMA2, LL_DMA_STREAM_1, LL_DMA_STREAM_6 },
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};
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uint32_t lastStatsTick = 0;
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uint32_t prevSentTick = 0;
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uint8_t statId = 0;
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uint32_t tmp = sizeof(text2Send) - 1;
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uint32_t randmask = 0x80000000;
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do
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if(randmask & tmp)
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break;
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while((randmask = randmask >> 1));
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randmask -= 1;
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InitCrcStatus(&g_crcStatus, DMA2, LL_DMA_STREAM_4);
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for(uint16_t idx = 0; idx < sizeof(g_uartStatuses) / sizeof(g_uartStatuses[0]); ++idx) {
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struct initdata_t const *id = &initdata[idx];
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InitUartStatus(&g_uartStatuses[idx], id->uart, id->dma, id->stream_rx, id->stream_tx, &g_crcStatus, NULL, NULL);
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memcpy(GetTxBuffer(&g_uartStatuses[idx]), text2Send, sizeof(text2Send) -1);
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}
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InitDmaInfo(&g_ConsoleTxDmaInfo, CONSOLE_DMA_ENGINE, CONSOLE_TX_DMA_STREAM);
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LL_DMA_EnableIT_TC(g_ConsoleTxDmaInfo.dma, g_ConsoleTxDmaInfo.stream);
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InitMemcpyDma(MEMCPY_DMA_ENGINE, MEMCPY_DMA_STREAM);
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lastStatsTick = HAL_GetTick();
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for(uint16_t idx = 0; idx < sizeof(g_uartStatuses) / sizeof(g_uartStatuses[0]); ++idx)
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SetupReceive(&g_uartStatuses[idx]);
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for(;;) {
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uint32_t tick = HAL_GetTick();
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uint8_t send = PACKAGE_DELAY_MS ? (tick - prevSentTick > PACKAGE_DELAY_MS) : 1;
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if(send)
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prevSentTick += PACKAGE_DELAY_MS;
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for(uint16_t idx = 0; idx < sizeof(g_uartStatuses) / sizeof(g_uartStatuses[0]); ++idx) {
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if(!g_uartStatuses[idx].txBuffer.busy && send) {
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uint16_t len = sizeof(text2Send) - 1 - (rand() & randmask);
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DIAG_ENTER_BUSY();
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MemcpyDma(GetTxBuffer(&g_uartStatuses[idx]), text2Send, len);
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PostPacket(&g_uartStatuses[idx], NULL, len, &g_crcStatus, 1);
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DIAG_EXIT_BUSY();
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}
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for(uint16_t rIdx = 0; rIdx < 2; ++rIdx)
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if(g_uartStatuses[idx].rxBuffers[rIdx].busy || g_uartStatuses[idx].rxBuffers[rIdx].error) {
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DIAG_ENTER_BUSY();
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ConsumePacket(&g_uartStatuses[idx], rIdx);
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DIAG_EXIT_BUSY();
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}
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}
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if(tick - lastStatsTick > STATS_DELAY_MS) {
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PrintStats((char*)g_statsBuf, statId, &g_uartStatuses[statId].stats, UART4, &g_ConsoleTxDmaInfo);
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lastStatsTick += STATS_DELAY_MS;
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++statId;
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if(statId >= USARTCOUNT)
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statId = 0;
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}
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uint32_t ein = LL_GPIO_ReadInputPort(KEY1_GPIO_Port);
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if(!(ein & KEY1_Pin)) {
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void (*fptr)(void) = (void (*)(void))(void*)0xa0000000;
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fptr();
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}
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}
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}
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#endif // USE_CPLUSPLUS
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@ -13,10 +13,11 @@
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#include "f4ll/memcpydma.h"
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#include "f4ll/consolehandler.h"
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#include "f4ll/irqlock.h"
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#include "f4ll/strutil.h"
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extern "C" {
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#include "main.h"
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#include "globals.h"
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#include "f4ll_c/strutil.h"
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#include "config.h"
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}
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#include "globals_cpp.h"
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@ -7,10 +7,10 @@
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#include "globals.h"
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struct usartstatus_t g_uartStatuses[USARTCOUNT];
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//struct usartstatus_t g_uartStatuses[USARTCOUNT];
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struct crcstatus_t g_crcStatus;
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//struct crcstatus_t g_crcStatus;
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DMAINFO g_ConsoleTxDmaInfo;
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//DMAINFO g_ConsoleTxDmaInfo;
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uint8_t g_statsBuf[256];
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@ -10,15 +10,15 @@
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#include <inttypes.h>
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#include "config.h"
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#include "f4ll_c/usart_handler.h"
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#include "f4ll_c/dma_helper.h"
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#include "f4ll_c/crc_handler.h"
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//#include "f4ll_c/usart_handler.h"
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//#include "f4ll_c/dma_helper.h"
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//#include "f4ll_c/crc_handler.h"
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extern struct usartstatus_t g_uartStatuses[USARTCOUNT];
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//extern struct usartstatus_t g_uartStatuses[USARTCOUNT];
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extern struct crcstatus_t g_crcStatus;
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//extern struct crcstatus_t g_crcStatus;
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extern DMAINFO g_ConsoleTxDmaInfo;
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//extern DMAINFO g_ConsoleTxDmaInfo;
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extern uint8_t g_statsBuf[256];
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#endif /* GLOBALS_H_ */
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*
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******************************************************************************
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*/
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/* This generated C file is symlinked as C++ and excluded from the build
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* USE_CPLUSPLUS macro is defined externally (Preprocessor Settings or Makefile)
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*/
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#ifdef __cplusplus
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extern "C" {
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@ -281,7 +286,7 @@ void DMA1_Stream4_IRQHandler(void)
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#ifdef USE_CPLUSPLUS
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f4ll::ConsoleHandler::HandleTxDmaIrq(&f4ll::ConsoleHandler::Instance());
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#else
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HandleConsoleUsartTxDmaIrq(&g_ConsoleTxDmaInfo, UART4);
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HandleConsoleTxDmaIrq(&g_ConsoleTxDmaInfo, UART4);
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#endif
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/* USER CODE END DMA1_Stream4_IRQn 0 */
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@ -399,7 +404,7 @@ void UART4_IRQHandler(void)
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#ifdef USE_CPLUSPLUS
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f4ll::ConsoleHandler::HandleUsartIrq(&f4ll::ConsoleHandler::Instance());
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#else
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HandleConsoleUsartIrq(UART4);
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Con_HandleUsartIrq(UART4);
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#endif
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/* USER CODE END UART4_IRQn 0 */
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/* USER CODE BEGIN UART4_IRQn 1 */
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@ -452,7 +457,7 @@ void DMA2_Stream3_IRQHandler(void)
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#ifdef USE_CPLUSPLUS
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f4ll::MemcpyDma::Instance().DmaTransferCompleted();
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#else
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HandleMemcpyDmaIrq();
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Mcd_HandleDmaIrq();
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#endif
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/* USER CODE END DMA2_Stream3_IRQn 0 */
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@ -6,6 +6,14 @@
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#define FAULT_REASON_BUS_FAULT 3
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#define FAULT_REASON_USAGE_FAULT 4
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#ifdef __cplusplus
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extern "C" {
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#endif
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void app_fault_callback(uint32_t reason);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __FAULT_H */
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@ -6,7 +6,7 @@
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*/
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#include "f4ll/consolehandler.h"
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#include <f4ll_c/strutil.h>
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#include "f4ll/strutil.h"
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namespace f4ll {
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@ -8,8 +8,12 @@
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#include <inttypes.h>
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//#include <core_cm4.h>
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#include "stm32f4xx.h"
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#include "f4ll_c/strutil.h"
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#include "fault.h"
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#include "f4ll/strutil.h"
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#include "f4ll/fault.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint32_t R0;
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@ -69,10 +73,10 @@ void SwoSendStr(char const *str, uint8_t len, uint8_t port)
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}
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}
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void fault_print_str(char *fmtstr, uint32_t *values)
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void fault_print_str(char const *fmtstr, uint32_t *values)
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{
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char hex_str[9]={0};
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char *nextChunk = fmtstr;
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char const *nextChunk = fmtstr;
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while(*fmtstr) {
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if(*fmtstr == '%') {
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@ -164,3 +168,7 @@ __attribute__((noreturn)) void FaultHandler(uint32_t type, fault_context_t *cont
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}
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}
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#ifdef __cplusplus
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}
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#endif
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@ -1,5 +1,5 @@
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#include <stdint.h>
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#include "f4ll_c/strutil.h"
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#include "f4ll/strutil.h"
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//////////////////////////////////////////////////////////////////////////////
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size_t strcpy_ex(char *dst, char const *src)
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@ -1,11 +0,0 @@
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#encoder
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SELF_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
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REL_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
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ifeq ($(MKDBG), 1)
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$(info >>> $(REL_DIR)/component.mk)
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endif
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$(eval C_INCLUDES += -I$(REL_DIR)/inc)
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$(eval C_SOURCES += $(wildcard $(REL_DIR)/src/*.c))
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ifeq ($(MKDBG), 1)
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$(info <<<)
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endif
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@ -1,19 +0,0 @@
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/*
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* interrupt.h
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*
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* Created on: Aug 29, 2019
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* Author: abody
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*/
|
||||
|
||||
#ifndef INTERRUPT_HANDLERS_H_
|
||||
#define INTERRUPT_HANDLERS_H_
|
||||
|
||||
#include "usart.h"
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
|
||||
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart);
|
||||
void HandleConsoleUsartIrq(USART_TypeDef *usart);
|
||||
|
||||
void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo);
|
||||
|
||||
#endif /* INTERRUPT_HANDLERS_H_ */
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
* interrupt.h
|
||||
*
|
||||
* Created on: Aug 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef CRC_HANDLER_H_
|
||||
#define CRC_HANDLER_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#ifdef HAVE_CONFIG
|
||||
#include "config.h"
|
||||
#endif // HAVE_CONFIG
|
||||
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
|
||||
struct crcslottask_t {
|
||||
void * volatile address;
|
||||
uint16_t wordCount;
|
||||
void (*callback)(void*, uint32_t, uint8_t);
|
||||
void *callbackParam;
|
||||
};
|
||||
|
||||
struct crcslotlistitem_t {
|
||||
uint16_t count;
|
||||
struct crcslotlistitem_t *next;
|
||||
struct crcslottask_t *tasks;
|
||||
};
|
||||
|
||||
struct crcstatus_t {
|
||||
DMAINFO dmaInfo;
|
||||
struct crcslotlistitem_t *activeSlot;
|
||||
uint8_t activeTask;
|
||||
struct crcslotlistitem_t *first;
|
||||
};
|
||||
|
||||
void InitCrcStatus(struct crcstatus_t *status, DMA_TypeDef *dma, uint32_t stream);
|
||||
|
||||
uint8_t GetActiveTask(struct crcslotlistitem_t **slot_out, struct crcstatus_t volatile *status);
|
||||
|
||||
static inline uint8_t IsSlotQueued(struct crcslotlistitem_t volatile *slot, uint8_t task) {
|
||||
return slot->tasks[task].address != NULL;
|
||||
}
|
||||
|
||||
static inline uint8_t IsSlotActive(struct crcslotlistitem_t volatile *slot, uint8_t task) {
|
||||
return slot->tasks[task].callback != NULL || slot->tasks[task].callbackParam != NULL;
|
||||
}
|
||||
|
||||
void AttachCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, struct crcslottask_t *tasks, uint8_t taskCount);
|
||||
|
||||
uint8_t EnqueueCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task,
|
||||
uint8_t *address, uint16_t len, void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
|
||||
void WaitCrcResults(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task);
|
||||
uint32_t ComputeCrc(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task, uint8_t *address, uint16_t len);
|
||||
void ComputeCrcAsync(struct crcstatus_t *status, uint8_t slot,
|
||||
uint8_t *address, uint16_t len,
|
||||
void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
|
||||
void HandleCrcDmaIrq(struct crcstatus_t *status);
|
||||
|
||||
#endif /* CRC_HANDLER_H_ */
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* dma_helper.h
|
||||
*
|
||||
* Created on: Sep 18, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef DMA_HELPER_H_
|
||||
#define DMA_HELPER_H_
|
||||
#include <inttypes.h>
|
||||
#include <platform/dma_ll.h>
|
||||
|
||||
typedef struct {
|
||||
DMA_TypeDef *dma;
|
||||
uint32_t stream;
|
||||
volatile uint32_t *isReg;
|
||||
volatile uint32_t *ifcReg;
|
||||
uint32_t feMask;
|
||||
uint32_t dmeMask;
|
||||
uint32_t teMask;
|
||||
uint32_t htMask;
|
||||
uint32_t tcMask;
|
||||
} DMAINFO;
|
||||
|
||||
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream);
|
||||
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream);
|
||||
uint32_t GetDmeMask(uint32_t stream);
|
||||
uint32_t GetTeMask(uint32_t stream);
|
||||
uint32_t GetHtMask(uint32_t stream);
|
||||
uint32_t GetTcMask(uint32_t stream);
|
||||
uint32_t GetFeMask(uint32_t stream);
|
||||
|
||||
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream);
|
||||
|
||||
#endif /* DMA_HELPER_H_ */
|
||||
|
|
@ -1 +0,0 @@
|
|||
.
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
/*
|
||||
* memcpy_dma.h
|
||||
*
|
||||
* Created on: Oct 1, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef MEMCPY_DMA_H_
|
||||
#define MEMCPY_DMA_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <platform/dma_ll.h>
|
||||
|
||||
void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream);
|
||||
void * MemcpyDma(void *dst, void const *src, size_t length);
|
||||
void HandleMemcpyDmaIrq();
|
||||
|
||||
#endif /* MEMCPY_DMA_H_ */
|
||||
|
|
@ -1,142 +0,0 @@
|
|||
/*
|
||||
* usart_handler.h
|
||||
*
|
||||
* Created on: Sep 16, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef USART_HANDLER_H_
|
||||
#define USART_HANDLER_H_
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
#include "f4ll_c/crc_handler.h"
|
||||
|
||||
struct usart_buffer;
|
||||
struct usartstatus_t;
|
||||
|
||||
typedef void (*PACKETRECEIVEDCALLBACK)(void *userParam, struct usart_buffer *buffer);
|
||||
|
||||
void InitUartStatus(
|
||||
struct usartstatus_t *st, USART_TypeDef *usart, DMA_TypeDef *dma,
|
||||
uint32_t stream_rx, uint32_t stream_tx,
|
||||
struct crcstatus_t *crcStatus,
|
||||
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam);
|
||||
|
||||
uint8_t* GetTxBuffer(struct usartstatus_t *status);
|
||||
|
||||
uint8_t PostPacket(struct usartstatus_t *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue);
|
||||
void SetupReceive(struct usartstatus_t *status);
|
||||
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length);
|
||||
void ConsumePacket(struct usartstatus_t *status, uint8_t packetIndex);
|
||||
|
||||
void HandleUsartRxDmaIrq(struct usartstatus_t *status);
|
||||
void HandleUsartTxDmaIrq(struct usartstatus_t *status);
|
||||
void HandleUsartIrq(struct usartstatus_t *status);
|
||||
|
||||
/******************************************************************************************
|
||||
*
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
struct usart_stats {
|
||||
uint32_t overrun;
|
||||
uint32_t hdrError;
|
||||
uint32_t lastErrHdr;
|
||||
uint32_t payloadErrror;
|
||||
uint32_t pep1, pep2;
|
||||
uint32_t dmaError;
|
||||
uint32_t rcvd;
|
||||
uint32_t premature_hdr;
|
||||
uint32_t premature_payload;
|
||||
uint32_t sent;
|
||||
uint32_t skiped;
|
||||
};
|
||||
|
||||
struct usartpacketheader_t {
|
||||
uint8_t startByte;
|
||||
uint8_t serial;
|
||||
uint8_t payloadLength;
|
||||
uint8_t hash;
|
||||
};
|
||||
|
||||
struct usartpacket_t {
|
||||
struct usartpacketheader_t header;
|
||||
//!!! should start on word offset !!!
|
||||
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
|
||||
} __attribute__((aligned));
|
||||
|
||||
struct usart_buffer {
|
||||
struct usartpacket_t packet;
|
||||
//transfer area ends here
|
||||
volatile uint8_t busy;
|
||||
volatile uint8_t error;
|
||||
uint16_t requestedLength;
|
||||
uint32_t errorInfo;
|
||||
struct usartstatus_t *usartStatus;
|
||||
};
|
||||
|
||||
struct usartstatus_t {
|
||||
USART_TypeDef *usart;
|
||||
DMAINFO rxDmaInfo;
|
||||
DMAINFO txDmaInfo;
|
||||
struct crcstatus_t *crcStatus;
|
||||
struct crcslotlistitem_t crcSlot;
|
||||
struct crcslottask_t crcTasks[2];
|
||||
|
||||
uint8_t rxSerial;
|
||||
uint8_t txSerial;
|
||||
struct usart_stats stats;
|
||||
uint8_t activeRxBuf;
|
||||
PACKETRECEIVEDCALLBACK packetReceivedCallback;
|
||||
void *packetReceivedCallbacParam;
|
||||
struct usart_buffer txBuffer;
|
||||
struct usart_buffer rxBuffers[2];
|
||||
};
|
||||
|
||||
#ifndef USART_STATS_DISABLED
|
||||
static inline void StatsIncOverrun(struct usart_stats *s) {
|
||||
++s->overrun;
|
||||
}
|
||||
static inline void StatsIncHdrError(struct usart_stats *s, uint32_t hdr) {
|
||||
++s->hdrError;
|
||||
s->lastErrHdr = hdr;
|
||||
}
|
||||
static inline void StatsIncPayloadError(struct usart_stats *s, uint32_t pep1, uint32_t pep2) {
|
||||
++s->payloadErrror;
|
||||
s->pep1 = pep1;
|
||||
s->pep2 = pep2;
|
||||
}
|
||||
static inline void StatsIncDmaError(struct usart_stats *s) {
|
||||
++s->dmaError;
|
||||
}
|
||||
static inline void StatsIncRcvd(struct usart_stats *s) {
|
||||
++s->rcvd;
|
||||
}
|
||||
static inline void StatsIncPremature_hdr(struct usart_stats *s) {
|
||||
++s->premature_hdr;
|
||||
}
|
||||
static inline void StatsIncPremature_payload(struct usart_stats *s) {
|
||||
++s->premature_payload;
|
||||
}
|
||||
static inline void StatsIncSent(struct usart_stats *s) {
|
||||
++s->sent;
|
||||
}
|
||||
static inline void StatsAddSkiped(struct usart_stats *s, uint8_t cnt) {
|
||||
s->skiped += s->rcvd > 2 ? cnt : 0;
|
||||
}
|
||||
|
||||
#else // USART_STATS_DISABLED
|
||||
#define StatsIncOverrun(x)
|
||||
#define StatsIncHdrError(x,y)
|
||||
#define StatsIncPayloadError(x,y,z)
|
||||
#define StatsIncDmaError(x)
|
||||
#define StatsIncRcvd(x)
|
||||
#define StatsIncPremature_hdr(x)
|
||||
#define StatsIncPremature_payload(x)
|
||||
#define StatsIncSent(x)
|
||||
#define StatsAddSkiped(x)
|
||||
#endif // USART_STATS_DISABLED
|
||||
|
||||
#endif /* UART_HANDLER_H_ */
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
/*
|
||||
* interrupt.c
|
||||
*
|
||||
* Created on: Aug 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include "main.h"
|
||||
#include "globals.h"
|
||||
#include "f4ll_c/usart_handler.h"
|
||||
#include "f4ll_c/strutil.h"
|
||||
|
||||
#ifndef DIAG_INTERRUPT_IN
|
||||
# define DIAG_INTERRUPT_IN()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_INTERRUPT_OUT
|
||||
# define DIAG_INTERRUPT_OUT()
|
||||
#endif
|
||||
|
||||
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart) // debug usart
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*info->isReg & info->tcMask) { // DMA transfer complete
|
||||
*info->ifcReg = info->tcMask;
|
||||
LL_USART_EnableIT_TC(usart);
|
||||
LL_DMA_DisableStream(info->dma, info->stream);
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleConsoleUsartIrq(USART_TypeDef *usart)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(LL_USART_IsActiveFlag_TC(usart) && LL_USART_IsEnabledIT_TC(usart)) // transmission complete
|
||||
LL_USART_DisableIT_TC(usart);
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
#define ADDINFO(b,s,u) \
|
||||
b += strcpy_ex(b,s); \
|
||||
b += uitodec(b,u);
|
||||
|
||||
void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo)
|
||||
{
|
||||
char ids[] = " : ";
|
||||
char *bs = buffer;
|
||||
|
||||
ids[0] = id + '0';
|
||||
buffer += strcpy_ex(buffer, ids);
|
||||
ADDINFO(buffer, " s: ", stats->sent);
|
||||
ADDINFO(buffer, " r: ", stats->rcvd);
|
||||
ADDINFO(buffer, " sk: ", stats->skiped);
|
||||
ADDINFO(buffer, " or: ", stats->overrun);
|
||||
ADDINFO(buffer, " he: ", stats->hdrError);
|
||||
buffer += strcpy_ex(buffer,",0x");
|
||||
buffer += uitohex(buffer, stats->lastErrHdr, 8);
|
||||
ADDINFO(buffer, " pe: ", stats->payloadErrror);
|
||||
buffer += strcpy_ex(buffer,",0x");
|
||||
buffer += uitohex(buffer, stats->pep1, 8);
|
||||
buffer += strcpy_ex(buffer,",0x");
|
||||
buffer += uitohex(buffer, stats->pep2, 8);
|
||||
ADDINFO(buffer, " de: ", stats->dmaError);
|
||||
ADDINFO(buffer, " pmh: ", stats->premature_hdr);
|
||||
ADDINFO(buffer, " pmp: ", stats->premature_payload);
|
||||
buffer += strcpy_ex(buffer, "\r\n");
|
||||
|
||||
SetupTransmit(usart, dmaInfo->dma, dmaInfo->stream, bs, buffer - bs + 1);
|
||||
}
|
||||
|
|
@ -1,179 +0,0 @@
|
|||
/*
|
||||
* interrupt.c
|
||||
*
|
||||
* Created on: Aug 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include "main.h"
|
||||
#include <string.h>
|
||||
#include <platform/crc_ll.h>
|
||||
#include "diag.h"
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
#include "f4ll_c/crc_handler.h"
|
||||
|
||||
#ifndef DIAG_CRC_CALC_START
|
||||
# define DIAG_CRC_CALC_START()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_CRC_CALC_END
|
||||
# define DIAG_CRC_CALC_END()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_INTERRUPT_IN
|
||||
# define DIAG_INTERRUPT_IN()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_INTERRUPT_OUT
|
||||
# define DIAG_INTERRUPT_OUT()
|
||||
#endif
|
||||
|
||||
void InitCrcStatus(struct crcstatus_t *st, DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
InitDmaInfo(&st->dmaInfo, dma, stream);
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
LL_DMA_EnableIT_TE(dma, stream);
|
||||
LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
|
||||
st->activeSlot = NULL;
|
||||
st->first = NULL;
|
||||
}
|
||||
|
||||
void AttachCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, struct crcslottask_t *tasks, uint8_t taskCount)
|
||||
{
|
||||
slot->count = taskCount;
|
||||
slot->tasks = tasks;
|
||||
memset(tasks, 0, sizeof(*tasks)*taskCount);
|
||||
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
slot->next = status->first;
|
||||
status->first = slot;
|
||||
__set_PRIMASK(prim);
|
||||
}
|
||||
|
||||
uint8_t GetActiveTask(struct crcslotlistitem_t **slot_out, struct crcstatus_t volatile *status)
|
||||
{
|
||||
uint8_t ret;
|
||||
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
|
||||
__disable_irq();
|
||||
ret = status->activeTask;
|
||||
if(slot_out)
|
||||
*slot_out = (struct crcslotlistitem_t *) status->activeSlot;
|
||||
__set_PRIMASK(prim);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
uint8_t EnqueueCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task,
|
||||
uint8_t *address, uint16_t len, void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
|
||||
{
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
uint16_t need_start;
|
||||
struct crcstatus_t volatile *st = status;
|
||||
|
||||
while(st->activeSlot == slot && st->activeTask == task);
|
||||
__disable_irq();
|
||||
need_start = (st->activeSlot == NULL);
|
||||
slot->tasks[task].address = need_start ? NULL : address;
|
||||
slot->tasks[task].wordCount = (len+3)/4;
|
||||
slot->tasks[task].callback = callback;
|
||||
slot->tasks[task].callbackParam = callbackParam;
|
||||
if(need_start) {
|
||||
status->activeSlot = slot;
|
||||
status->activeTask = task;
|
||||
}
|
||||
__set_PRIMASK(prim);
|
||||
|
||||
if(need_start) {
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)address);
|
||||
LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, (len+3)/4);
|
||||
DIAG_CRC_CALC_START();
|
||||
LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
|
||||
}
|
||||
return need_start;
|
||||
}
|
||||
|
||||
void WaitCrcResults(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task)
|
||||
{
|
||||
struct crcslotlistitem_t *slotQueued;
|
||||
|
||||
while(IsSlotQueued(slot, task));
|
||||
while(GetActiveTask(&slotQueued, status) == task && slotQueued == slot);
|
||||
}
|
||||
|
||||
|
||||
uint32_t ComputeCrc(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task, uint8_t *address, uint16_t len)
|
||||
{
|
||||
uint32_t result;
|
||||
EnqueueCrcTask(status, slot, task, address, len, NULL, &result);
|
||||
while((struct crcslotlistitem_t volatile *)slot->tasks[task].callbackParam);
|
||||
return result;
|
||||
}
|
||||
|
||||
// only called from ISR context
|
||||
static void StartNextCrcTask(struct crcstatus_t *status)
|
||||
{
|
||||
char moreTasks;
|
||||
uint8_t index = 0;
|
||||
|
||||
do {
|
||||
struct crcslotlistitem_t *slot = status->first;
|
||||
moreTasks = 0;
|
||||
while(slot) {
|
||||
if(index < slot->count) {
|
||||
if(slot->tasks[index].address) {
|
||||
status->activeSlot = slot;
|
||||
status->activeTask = index;
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)slot->tasks[index].address);
|
||||
LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, slot->tasks[index].wordCount);
|
||||
LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
|
||||
slot->tasks[index].address = NULL; // marking as started
|
||||
return;
|
||||
}
|
||||
if(index + 1 < slot->count)
|
||||
moreTasks = 1;
|
||||
}
|
||||
slot = slot->next;
|
||||
}
|
||||
++index;
|
||||
} while(moreTasks);
|
||||
status->activeSlot = NULL;
|
||||
}
|
||||
|
||||
void HandleCrcDmaIrq(struct crcstatus_t *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*status->dmaInfo.isReg & status->dmaInfo.tcMask) { // DMA transfer complete
|
||||
*status->dmaInfo.ifcReg = status->dmaInfo.tcMask;
|
||||
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
|
||||
if(status->activeSlot) {
|
||||
struct crcslottask_t *tsk = &status->activeSlot->tasks[status->activeTask];
|
||||
if(tsk->callback)
|
||||
tsk->callback(tsk->callbackParam, CRC->DR, 1);
|
||||
else if(tsk->callbackParam)
|
||||
*(uint32_t*)tsk->callbackParam = CRC->DR;
|
||||
tsk->callback = tsk->callbackParam = NULL; // marking as inactive
|
||||
DIAG_CRC_CALC_END();
|
||||
StartNextCrcTask(status);
|
||||
}
|
||||
}
|
||||
else if(*status->dmaInfo.isReg & status->dmaInfo.teMask) {
|
||||
*status->dmaInfo.ifcReg = status->dmaInfo.teMask;
|
||||
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
|
||||
if(status->activeSlot) {
|
||||
struct crcslottask_t *tsk = &status->activeSlot->tasks[status->activeTask];
|
||||
if(tsk->callback)
|
||||
tsk->callback(tsk->callbackParam, CRC->DR, 0);
|
||||
else if(tsk->callbackParam)
|
||||
*(uint32_t*)tsk->callbackParam = 0xffffffff;
|
||||
tsk->callback = tsk->callbackParam = NULL; // marking as inactive
|
||||
DIAG_CRC_CALC_END();
|
||||
StartNextCrcTask(status);
|
||||
}
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/*
|
||||
* dma_helper.c
|
||||
*
|
||||
* Created on: Sep 18, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
|
||||
|
||||
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
if(dma == DMA1)
|
||||
return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR;
|
||||
else
|
||||
return (stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR;
|
||||
}
|
||||
|
||||
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
if(dma == DMA1)
|
||||
return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR;
|
||||
else
|
||||
return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR;
|
||||
}
|
||||
|
||||
uint32_t GetFeMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t feMasks[8] = {
|
||||
DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7
|
||||
};
|
||||
return feMasks[stream];
|
||||
}
|
||||
|
||||
uint32_t GetDmeMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t dmeMasks[8] = {
|
||||
DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7
|
||||
};
|
||||
return dmeMasks[stream];
|
||||
}
|
||||
|
||||
uint32_t GetTeMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t teMasks[8] = {
|
||||
DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7
|
||||
};
|
||||
return teMasks[stream];
|
||||
}
|
||||
|
||||
uint32_t GetHtMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t htMasks[8] = {
|
||||
DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7
|
||||
};
|
||||
return htMasks[stream];
|
||||
}
|
||||
|
||||
uint32_t GetTcMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t tcMasks[8] = {
|
||||
DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7
|
||||
};
|
||||
|
||||
return tcMasks[stream];
|
||||
}
|
||||
|
||||
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
info->dma = dma;
|
||||
info->stream = stream;
|
||||
info->isReg = GetIsReg(dma, stream);
|
||||
info->ifcReg = GetIfcReg(dma, stream);
|
||||
info->feMask = GetFeMask(stream);
|
||||
info->dmeMask = GetDmeMask(stream);
|
||||
info->teMask = GetTeMask(stream);
|
||||
info->htMask = GetHtMask(stream);
|
||||
info->tcMask = GetTcMask(stream);
|
||||
}
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
/*
|
||||
* memcpy_dma.c
|
||||
*
|
||||
* Created on: Oct 1, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include "f4ll_c/memcpy_dma.h"
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
|
||||
#ifndef DIAG_INTERRUPT_IN
|
||||
# define DIAG_INTERRUPT_IN()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_INTERRUPT_OUT
|
||||
# define DIAG_INTERRUPT_OUT()
|
||||
#endif
|
||||
|
||||
volatile uint8_t g_memcpyDmaBusy = 0;
|
||||
|
||||
static DMAINFO g_memcpyDmaInfo;
|
||||
|
||||
void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
InitDmaInfo(&g_memcpyDmaInfo, dma, stream);
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
}
|
||||
|
||||
void * MemcpyDma(void *dst, void const *src, size_t length)
|
||||
{
|
||||
LL_DMA_SetM2MSrcAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)src);
|
||||
LL_DMA_SetM2MDstAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)dst);
|
||||
LL_DMA_SetDataLength(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (length+3)/4 );
|
||||
g_memcpyDmaBusy = 1;
|
||||
LL_DMA_EnableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
|
||||
while(g_memcpyDmaBusy);
|
||||
return dst;
|
||||
}
|
||||
|
||||
void HandleMemcpyDmaIrq()
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*g_memcpyDmaInfo.isReg & g_memcpyDmaInfo.tcMask) { // DMA transfer complete
|
||||
*g_memcpyDmaInfo.ifcReg = g_memcpyDmaInfo.tcMask;
|
||||
LL_DMA_DisableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
|
||||
g_memcpyDmaBusy = 0;
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
/*
|
||||
* usart_handler.c
|
||||
*
|
||||
* Created on: Sep 16, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <platform/usart_ll.h>
|
||||
#include "diag.h"
|
||||
#include "f4ll_c/usart_handler.h"
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
#include "f4ll_c/crc_handler.h"
|
||||
#include "f4ll_c/memcpy_dma.h"
|
||||
|
||||
#ifndef DIAG_RX_BUFFER_SWITCH
|
||||
# define DIAG_RX_BUFFER_SWITCH(x)
|
||||
#endif
|
||||
#ifndef DIAG_INTERRUPT_IN
|
||||
# define DIAG_INTERRUPT_IN()
|
||||
#endif
|
||||
#ifndef DIAG_INTERRUPT_OUT
|
||||
# define DIAG_INTERRUPT_OUT()
|
||||
#endif
|
||||
|
||||
#define STARTMARKER 0x95
|
||||
|
||||
static inline uint32_t RoundUpTo4(uint32_t inp)
|
||||
{
|
||||
return (inp + 3) & 0xfffc;
|
||||
}
|
||||
|
||||
void InitUartStatus(
|
||||
struct usartstatus_t *st, USART_TypeDef *usart, DMA_TypeDef *dma,
|
||||
uint32_t stream_rx, uint32_t stream_tx,
|
||||
struct crcstatus_t *crcStatus,
|
||||
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
|
||||
{
|
||||
uint32_t status = usart->SR;
|
||||
volatile uint32_t tmpreg = usart->DR; // clearing some of the error/status bits in the USART
|
||||
(void) tmpreg;
|
||||
(void) status;
|
||||
|
||||
st->usart = usart;
|
||||
InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
|
||||
InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
|
||||
st->txBuffer.busy = 0;
|
||||
st->txBuffer.error = 0;
|
||||
st->txBuffer.requestedLength = 0;
|
||||
st->rxBuffers[0].busy = 0;
|
||||
st->rxBuffers[1].busy = 0;
|
||||
st->rxBuffers[0].error = 0;
|
||||
st->rxBuffers[1].error = 0;
|
||||
st->rxBuffers[0].requestedLength = 0;
|
||||
st->rxBuffers[1].requestedLength = 0;
|
||||
st->txBuffer.usartStatus = st;
|
||||
st->rxBuffers[0].usartStatus = st;
|
||||
st->rxBuffers[1].usartStatus = st;
|
||||
st->packetReceivedCallback = packetReceivedCallback;
|
||||
st->packetReceivedCallbacParam = packetReceivedCallbackParam;
|
||||
st->rxSerial = -1;
|
||||
st->txSerial = 0;
|
||||
st->activeRxBuf = 0;
|
||||
st->crcStatus = crcStatus;
|
||||
AttachCrcTask(crcStatus, &st->crcSlot, st->crcTasks, 2);
|
||||
memset(&st->stats, 0, sizeof(st->stats));
|
||||
|
||||
*GetIfcReg(dma, stream_rx) =
|
||||
GetTcMask(stream_rx) | GetHtMask(stream_rx) |
|
||||
GetTeMask(stream_rx) | GetFeMask(stream_rx) | GetDmeMask(stream_rx);
|
||||
*GetIfcReg(dma, stream_tx) =
|
||||
GetTcMask(stream_tx) | GetHtMask(stream_tx) |
|
||||
GetTeMask(stream_tx) | GetFeMask(stream_tx) | GetDmeMask(stream_tx);
|
||||
|
||||
LL_DMA_EnableIT_TC(dma, stream_rx);
|
||||
LL_DMA_EnableIT_TE(dma, stream_rx);
|
||||
LL_DMA_EnableIT_TC(dma, stream_tx);
|
||||
LL_DMA_EnableIT_TE(dma, stream_tx);
|
||||
LL_USART_EnableIT_IDLE(usart);
|
||||
}
|
||||
|
||||
|
||||
uint8_t* GetTxBuffer(struct usartstatus_t *status)
|
||||
{
|
||||
return status->txBuffer.packet.payload;
|
||||
}
|
||||
|
||||
|
||||
static inline void BuildHeader(struct usart_buffer *buffer, uint8_t serial, uint8_t length)
|
||||
{
|
||||
uint8_t hash = STARTMARKER;
|
||||
buffer->packet.header.startByte = STARTMARKER;
|
||||
buffer->packet.header.serial = serial;
|
||||
hash ^= serial;
|
||||
buffer->packet.header.payloadLength = length - 1;
|
||||
hash ^= length - 1;
|
||||
buffer->packet.header.hash = hash;
|
||||
}
|
||||
|
||||
static inline uint8_t CheckHeader(struct usartpacket_t *packet)
|
||||
{
|
||||
return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
|
||||
}
|
||||
|
||||
|
||||
uint8_t PostPacket(struct usartstatus_t *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue)
|
||||
{
|
||||
// static uint32_t count = 0;
|
||||
// ITM->PORT[1].u32 = count++;
|
||||
|
||||
if(length > 256)
|
||||
return 1;
|
||||
|
||||
|
||||
BuildHeader(&status->txBuffer, status->txSerial++, length);
|
||||
uint16_t payloadLength = RoundUpTo4(length);
|
||||
if(payload)
|
||||
memcpy(status->txBuffer.packet.payload, payload, length);
|
||||
status->txBuffer.requestedLength = sizeof(struct usartpacketheader_t) + payloadLength + sizeof(uint32_t); // +4 for the hash
|
||||
status->txBuffer.busy = 1;
|
||||
status->txBuffer.error = 0;
|
||||
EnqueueCrcTask(status->crcStatus, &status->crcSlot, 0, status->txBuffer.packet.payload, length,
|
||||
NULL, (uint32_t*)(status->txBuffer.packet.payload + payloadLength));
|
||||
while(waitForCrcQueue && IsSlotQueued(&status->crcSlot, 0));
|
||||
SetupTransmit(status->usart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
|
||||
|
||||
StatsIncSent(&status->stats);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void SetupReceive(struct usartstatus_t *status)
|
||||
{
|
||||
uint8_t packetIndex = status->activeRxBuf;
|
||||
|
||||
LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->usart), (uint32_t)&status->rxBuffers[packetIndex],
|
||||
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
||||
status->rxBuffers[packetIndex].requestedLength = sizeof(status->rxBuffers[packetIndex].packet);
|
||||
LL_DMA_SetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream, status->rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
|
||||
LL_USART_EnableDMAReq_RX(status->usart);
|
||||
LL_USART_ClearFlag_ORE(status->usart);
|
||||
LL_DMA_EnableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
}
|
||||
|
||||
|
||||
void ConsumePacket(struct usartstatus_t *status, uint8_t packetIndex)
|
||||
{
|
||||
struct usart_buffer *buffer = &status->rxBuffers[packetIndex];
|
||||
if(buffer->busy) {
|
||||
if(buffer->error)
|
||||
StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + RoundUpTo4(buffer->packet.header.payloadLength + 1)));
|
||||
else {
|
||||
uint8_t diff = buffer->packet.header.serial - status->rxSerial;
|
||||
if(diff > 1)
|
||||
StatsAddSkiped(&status->stats, diff - 1);
|
||||
status->rxSerial = buffer->packet.header.serial;
|
||||
}
|
||||
}
|
||||
|
||||
buffer->busy = buffer->error = 0;
|
||||
}
|
||||
|
||||
|
||||
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_SetDataLength(dma, stream, length);
|
||||
LL_USART_EnableDMAReq_TX(usart);
|
||||
LL_DMA_EnableStream(dma, stream);
|
||||
}
|
||||
|
||||
void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
|
||||
{
|
||||
struct usart_buffer *ub = (struct usart_buffer*) callbackParm;
|
||||
if(!success)
|
||||
ub->error = 1;
|
||||
else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength + 1)) == calculatedCrc)
|
||||
ub->busy = 1;
|
||||
else {
|
||||
ub->error = ub->busy = 1;
|
||||
ub->errorInfo = calculatedCrc;
|
||||
}
|
||||
if(ub->usartStatus->packetReceivedCallback)
|
||||
ub->usartStatus->packetReceivedCallback(ub->usartStatus->packetReceivedCallbacParam, ub);
|
||||
}
|
||||
|
||||
void HandleUsartRxDmaIrq(struct usartstatus_t *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
StatsIncRcvd(&status->stats);
|
||||
if(*status->rxDmaInfo.isReg & status->rxDmaInfo.tcMask) {
|
||||
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.tcMask;
|
||||
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet))
|
||||
EnqueueCrcTask(status->crcStatus, &status->crcSlot, 1,
|
||||
status->rxBuffers[status->activeRxBuf].packet.payload,
|
||||
status->rxBuffers[status->activeRxBuf].packet.header.payloadLength +1,
|
||||
RxCrcComputedCallback, &status->rxBuffers[status->activeRxBuf]);
|
||||
else {
|
||||
StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
}
|
||||
} else if(*status->rxDmaInfo.isReg & status->rxDmaInfo.teMask) {
|
||||
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.teMask;
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
}
|
||||
|
||||
status->activeRxBuf ^= 1;
|
||||
|
||||
DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
|
||||
if(status->rxBuffers[status->activeRxBuf].busy)
|
||||
StatsIncOverrun(&status->stats);
|
||||
SetupReceive(status);
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleUsartTxDmaIrq(struct usartstatus_t *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
|
||||
LL_USART_EnableIT_TC(status->usart);
|
||||
LL_DMA_DisableStream(status->txDmaInfo.dma, status->txDmaInfo.stream);
|
||||
}
|
||||
else if(*status->txDmaInfo.isReg & status->txDmaInfo.teMask) {
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.teMask;
|
||||
status->txBuffer.error = 1;
|
||||
StatsIncDmaError(&status->stats);
|
||||
}
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.feMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.feMask;
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.htMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.htMask;
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.dmeMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.dmeMask;
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleUsartIrq(struct usartstatus_t *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(status->usart);
|
||||
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
if(rcvdLen >= sizeof(struct usartpacketheader_t)) {
|
||||
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
|
||||
if(rcvdLen >= sizeof(struct usartpacketheader_t) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
|
||||
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
else
|
||||
StatsIncPremature_payload(&status->stats);
|
||||
} else {
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
}
|
||||
} else
|
||||
StatsIncPremature_hdr(&status->stats);
|
||||
}
|
||||
else if(LL_USART_IsActiveFlag_TC(status->usart) && LL_USART_IsEnabledIT_TC(status->usart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(status->usart);
|
||||
LL_USART_DisableDirectionTx(status->usart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(status->usart);
|
||||
status->txBuffer.busy = 0;
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue