174 lines
3.2 KiB
C++
174 lines
3.2 KiB
C++
/*
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* fault.c
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*
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* Created on: Oct 1, 2019
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* Author: abody
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* -c "tpiu config internal <logfile_full_path> uart off <cpufreq>"
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*/
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#include <inttypes.h>
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//#include <core_cm4.h>
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#include "stm32f4xx.h"
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#include "f4ll/strutil.h"
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#include "f4ll/fault.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint32_t R0;
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uint32_t R1;
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uint32_t R2;
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uint32_t R3;
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uint32_t R4;
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uint32_t R5;
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uint32_t R6;
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uint32_t R7;
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uint32_t R8;
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uint32_t R9;
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uint32_t R10;
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uint32_t R11;
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uint32_t R12;
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uint32_t SP;
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uint32_t LR;
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uint32_t PC;
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uint32_t xPSR;
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uint32_t PSP;
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uint32_t MSP;
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uint32_t EXC_RETURN;
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uint32_t CONTROL;
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} fault_context_t;
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fault_context_t g_faultContext;
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void __attribute__((weak)) app_fault_callback(uint32_t reason)
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{
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}
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void SwoSendStr(char const *str, uint8_t len, uint8_t port)
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{
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while(len) {
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if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && // ITM enabled
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((ITM->TER & (1UL << port) ) != 0UL) ) // ITM Port enabled
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{
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// Wait until shift register is free
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while (ITM->PORT[port].u32 == 0UL) {
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__ASM volatile ("nop");
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}
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if(len >= 4) {
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ITM->PORT[port].u32 = *(uint32_t*)(str);
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str += 4;
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len -= 4;
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} else if(len >= 2) {
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ITM->PORT[port].u16 = *(uint16_t*)(str);
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str += 2;
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len -= 2;
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} else {
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ITM->PORT[port].u8 = *(uint8_t*)(str);
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++str;
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--len;
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}
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} else
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break;
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}
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}
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void fault_print_str(char const *fmtstr, uint32_t *values)
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{
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char hex_str[9]={0};
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char const *nextChunk = fmtstr;
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while(*fmtstr) {
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if(*fmtstr == '%') {
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SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
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uitohex(hex_str, *values++, 8);
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SwoSendStr(hex_str, 8, 0);
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nextChunk = fmtstr +1;
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}
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++fmtstr;
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}
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if(nextChunk != fmtstr)
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SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
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}
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__attribute__((noreturn)) void FaultHandler(uint32_t type, fault_context_t *context)
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{
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uint32_t FSR[9] = {
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SCB->HFSR,
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0xff & SCB->CFSR,
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(0xff00 & SCB->CFSR) >> 8,
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(0xffff0000 & SCB->CFSR) >> 16,
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SCB->DFSR,
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SCB->AFSR,
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SCB->SHCSR,
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SCB->MMFAR,
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SCB->BFAR
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};
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while(1) {
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fault_print_str("\n++ Fault Handler ++\n\nFaultType: ",NULL);
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switch( type ) {
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case FAULT_REASON_HARD_FAULT:
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fault_print_str("HardFault",NULL);
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break;
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case FAULT_REASON_MEMMANAGE_FAULT:
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fault_print_str("MemManageFault",NULL);
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break;
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case FAULT_REASON_BUS_FAULT:
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fault_print_str("BusFault",NULL);
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break;
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case FAULT_REASON_USAGE_FAULT:
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fault_print_str("UsageFault",NULL);
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break;
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default:
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fault_print_str("Unknown Fault",NULL);
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break;
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}
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fault_print_str("\n\nContext:",NULL);
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fault_print_str(
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"\nR0 : %"
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"\nR1 : %"
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"\nR2 : %"
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"\nR3 : %"
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"\nR4 : %"
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"\nR5 : %"
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"\nR6 : %"
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"\nR7 : %"
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"\nR8 : %"
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"\nR9 : %"
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"\nR10 : %"
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"\nR11 : %"
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"\nR12 : %"
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"\nSP : %"
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"\nLR : %"
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"\nPC : %"
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"\nxPSR : %"
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"\nPSP : %"
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"\nMSP : %",
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(uint32_t *)context);
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//Capture CPUID to get core/cpu info
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fault_print_str("\nCPUID: %",(uint32_t *)&SCB->CPUID);
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fault_print_str(
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"\nHFSR : %"
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"\nMMFSR: %"
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"\nBFSR : %"
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"\nUFSR : %"
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"\nDFSR : %"
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"\nAFSR : %"
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"\nSHCSR: %",
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FSR);
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app_fault_callback(type);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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