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C++ build fixed, C dropped

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This commit is contained in:
Attila Body 2020-11-28 12:18:35 +01:00
parent c439c48643
commit f26710a667
23 changed files with 50 additions and 1062 deletions
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19
components/f4ll/inc/fault.h Normal file
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@ -0,0 +1,19 @@
#ifndef __FAULT_H
#define __FAULT_H
#define FAULT_REASON_HARD_FAULT 1
#define FAULT_REASON_MEMMANAGE_FAULT 2
#define FAULT_REASON_BUS_FAULT 3
#define FAULT_REASON_USAGE_FAULT 4
#ifdef __cplusplus
extern "C" {
#endif
void app_fault_callback(uint32_t reason);
#ifdef __cplusplus
}
#endif
#endif /* __FAULT_H */

0
components/f4ll_c/inc/strutil.h → components/f4ll/inc/strutil.h
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2
components/f4ll/src/consolehandler.cpp
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@ -6,7 +6,7 @@
*/
#include "f4ll/consolehandler.h"
#include <f4ll_c/strutil.h>
#include "f4ll/strutil.h"
namespace f4ll {

174
components/f4ll/src/fault.cpp Normal file
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@ -0,0 +1,174 @@
/*
* fault.c
*
* Created on: Oct 1, 2019
* Author: abody
* -c "tpiu config internal <logfile_full_path> uart off <cpufreq>"
*/
#include <inttypes.h>
//#include <core_cm4.h>
#include "stm32f4xx.h"
#include "f4ll/strutil.h"
#include "f4ll/fault.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t R0;
uint32_t R1;
uint32_t R2;
uint32_t R3;
uint32_t R4;
uint32_t R5;
uint32_t R6;
uint32_t R7;
uint32_t R8;
uint32_t R9;
uint32_t R10;
uint32_t R11;
uint32_t R12;
uint32_t SP;
uint32_t LR;
uint32_t PC;
uint32_t xPSR;
uint32_t PSP;
uint32_t MSP;
uint32_t EXC_RETURN;
uint32_t CONTROL;
} fault_context_t;
fault_context_t g_faultContext;
void __attribute__((weak)) app_fault_callback(uint32_t reason)
{
}
void SwoSendStr(char const *str, uint8_t len, uint8_t port)
{
while(len) {
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && // ITM enabled
((ITM->TER & (1UL << port) ) != 0UL) ) // ITM Port enabled
{
// Wait until shift register is free
while (ITM->PORT[port].u32 == 0UL) {
__ASM volatile ("nop");
}
if(len >= 4) {
ITM->PORT[port].u32 = *(uint32_t*)(str);
str += 4;
len -= 4;
} else if(len >= 2) {
ITM->PORT[port].u16 = *(uint16_t*)(str);
str += 2;
len -= 2;
} else {
ITM->PORT[port].u8 = *(uint8_t*)(str);
++str;
--len;
}
} else
break;
}
}
void fault_print_str(char const *fmtstr, uint32_t *values)
{
char hex_str[9]={0};
char const *nextChunk = fmtstr;
while(*fmtstr) {
if(*fmtstr == '%') {
SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
uitohex(hex_str, *values++, 8);
SwoSendStr(hex_str, 8, 0);
nextChunk = fmtstr +1;
}
++fmtstr;
}
if(nextChunk != fmtstr)
SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
}
__attribute__((noreturn)) void FaultHandler(uint32_t type, fault_context_t *context)
{
uint32_t FSR[9] = {
SCB->HFSR,
0xff & SCB->CFSR,
(0xff00 & SCB->CFSR) >> 8,
(0xffff0000 & SCB->CFSR) >> 16,
SCB->DFSR,
SCB->AFSR,
SCB->SHCSR,
SCB->MMFAR,
SCB->BFAR
};
while(1) {
fault_print_str("\n++ Fault Handler ++\n\nFaultType: ",NULL);
switch( type ) {
case FAULT_REASON_HARD_FAULT:
fault_print_str("HardFault",NULL);
break;
case FAULT_REASON_MEMMANAGE_FAULT:
fault_print_str("MemManageFault",NULL);
break;
case FAULT_REASON_BUS_FAULT:
fault_print_str("BusFault",NULL);
break;
case FAULT_REASON_USAGE_FAULT:
fault_print_str("UsageFault",NULL);
break;
default:
fault_print_str("Unknown Fault",NULL);
break;
}
fault_print_str("\n\nContext:",NULL);
fault_print_str(
"\nR0 : %"
"\nR1 : %"
"\nR2 : %"
"\nR3 : %"
"\nR4 : %"
"\nR5 : %"
"\nR6 : %"
"\nR7 : %"
"\nR8 : %"
"\nR9 : %"
"\nR10 : %"
"\nR11 : %"
"\nR12 : %"
"\nSP : %"
"\nLR : %"
"\nPC : %"
"\nxPSR : %"
"\nPSP : %"
"\nMSP : %",
(uint32_t *)context);
//Capture CPUID to get core/cpu info
fault_print_str("\nCPUID: %",(uint32_t *)&SCB->CPUID);
fault_print_str(
"\nHFSR : %"
"\nMMFSR: %"
"\nBFSR : %"
"\nUFSR : %"
"\nDFSR : %"
"\nAFSR : %"
"\nSHCSR: %",
FSR);
app_fault_callback(type);
}
}
#ifdef __cplusplus
}
#endif

2
components/f4ll_c/src/strutil.c → components/f4ll/src/strutil.cpp
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@ -1,5 +1,5 @@
#include <stdint.h>
#include "f4ll_c/strutil.h"
#include "f4ll/strutil.h"
//////////////////////////////////////////////////////////////////////////////
size_t strcpy_ex(char *dst, char const *src)

11
components/f4ll_c/component.mk
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@ -1,11 +0,0 @@
#encoder
SELF_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
REL_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
ifeq ($(MKDBG), 1)
$(info >>> $(REL_DIR)/component.mk)
endif
$(eval C_INCLUDES += -I$(REL_DIR)/inc)
$(eval C_SOURCES += $(wildcard $(REL_DIR)/src/*.c))
ifeq ($(MKDBG), 1)
$(info <<<)
endif

19
components/f4ll_c/inc/console_handler.h
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@ -1,19 +0,0 @@
/*
* interrupt.h
*
* Created on: Aug 29, 2019
* Author: abody
*/
#ifndef INTERRUPT_HANDLERS_H_
#define INTERRUPT_HANDLERS_H_
#include "usart.h"
#include "f4ll_c/dma_helper.h"
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart);
void HandleConsoleUsartIrq(USART_TypeDef *usart);
void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo);
#endif /* INTERRUPT_HANDLERS_H_ */

62
components/f4ll_c/inc/crc_handler.h
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@ -1,62 +0,0 @@
/*
* interrupt.h
*
* Created on: Aug 29, 2019
* Author: abody
*/
#ifndef CRC_HANDLER_H_
#define CRC_HANDLER_H_
#include <inttypes.h>
#ifdef HAVE_CONFIG
#include "config.h"
#endif // HAVE_CONFIG
#include "f4ll_c/dma_helper.h"
struct crcslottask_t {
void * volatile address;
uint16_t wordCount;
void (*callback)(void*, uint32_t, uint8_t);
void *callbackParam;
};
struct crcslotlistitem_t {
uint16_t count;
struct crcslotlistitem_t *next;
struct crcslottask_t *tasks;
};
struct crcstatus_t {
DMAINFO dmaInfo;
struct crcslotlistitem_t *activeSlot;
uint8_t activeTask;
struct crcslotlistitem_t *first;
};
void InitCrcStatus(struct crcstatus_t *status, DMA_TypeDef *dma, uint32_t stream);
uint8_t GetActiveTask(struct crcslotlistitem_t **slot_out, struct crcstatus_t volatile *status);
static inline uint8_t IsSlotQueued(struct crcslotlistitem_t volatile *slot, uint8_t task) {
return slot->tasks[task].address != NULL;
}
static inline uint8_t IsSlotActive(struct crcslotlistitem_t volatile *slot, uint8_t task) {
return slot->tasks[task].callback != NULL || slot->tasks[task].callbackParam != NULL;
}
void AttachCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, struct crcslottask_t *tasks, uint8_t taskCount);
uint8_t EnqueueCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task,
uint8_t *address, uint16_t len, void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
void WaitCrcResults(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task);
uint32_t ComputeCrc(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task, uint8_t *address, uint16_t len);
void ComputeCrcAsync(struct crcstatus_t *status, uint8_t slot,
uint8_t *address, uint16_t len,
void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
void HandleCrcDmaIrq(struct crcstatus_t *status);
#endif /* CRC_HANDLER_H_ */

35
components/f4ll_c/inc/dma_helper.h
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@ -1,35 +0,0 @@
/*
* dma_helper.h
*
* Created on: Sep 18, 2019
* Author: abody
*/
#ifndef DMA_HELPER_H_
#define DMA_HELPER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
typedef struct {
DMA_TypeDef *dma;
uint32_t stream;
volatile uint32_t *isReg;
volatile uint32_t *ifcReg;
uint32_t feMask;
uint32_t dmeMask;
uint32_t teMask;
uint32_t htMask;
uint32_t tcMask;
} DMAINFO;
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream);
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream);
uint32_t GetDmeMask(uint32_t stream);
uint32_t GetTeMask(uint32_t stream);
uint32_t GetHtMask(uint32_t stream);
uint32_t GetTcMask(uint32_t stream);
uint32_t GetFeMask(uint32_t stream);
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream);
#endif /* DMA_HELPER_H_ */

1
components/f4ll_c/inc/f4ll_c
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@ -1 +0,0 @@
.

18
components/f4ll_c/inc/memcpy_dma.h
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@ -1,18 +0,0 @@
/*
* memcpy_dma.h
*
* Created on: Oct 1, 2019
* Author: abody
*/
#ifndef MEMCPY_DMA_H_
#define MEMCPY_DMA_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream);
void * MemcpyDma(void *dst, void const *src, size_t length);
void HandleMemcpyDmaIrq();
#endif /* MEMCPY_DMA_H_ */

142
components/f4ll_c/inc/usart_handler.h
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@ -1,142 +0,0 @@
/*
* usart_handler.h
*
* Created on: Sep 16, 2019
* Author: abody
*/
#ifndef USART_HANDLER_H_
#define USART_HANDLER_H_
#include <inttypes.h>
#include "f4ll_c/dma_helper.h"
#include "f4ll_c/crc_handler.h"
struct usart_buffer;
struct usartstatus_t;
typedef void (*PACKETRECEIVEDCALLBACK)(void *userParam, struct usart_buffer *buffer);
void InitUartStatus(
struct usartstatus_t *st, USART_TypeDef *usart, DMA_TypeDef *dma,
uint32_t stream_rx, uint32_t stream_tx,
struct crcstatus_t *crcStatus,
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam);
uint8_t* GetTxBuffer(struct usartstatus_t *status);
uint8_t PostPacket(struct usartstatus_t *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue);
void SetupReceive(struct usartstatus_t *status);
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length);
void ConsumePacket(struct usartstatus_t *status, uint8_t packetIndex);
void HandleUsartRxDmaIrq(struct usartstatus_t *status);
void HandleUsartTxDmaIrq(struct usartstatus_t *status);
void HandleUsartIrq(struct usartstatus_t *status);
/******************************************************************************************
*
*
*
*/
struct usart_stats {
uint32_t overrun;
uint32_t hdrError;
uint32_t lastErrHdr;
uint32_t payloadErrror;
uint32_t pep1, pep2;
uint32_t dmaError;
uint32_t rcvd;
uint32_t premature_hdr;
uint32_t premature_payload;
uint32_t sent;
uint32_t skiped;
};
struct usartpacketheader_t {
uint8_t startByte;
uint8_t serial;
uint8_t payloadLength;
uint8_t hash;
};
struct usartpacket_t {
struct usartpacketheader_t header;
//!!! should start on word offset !!!
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned));
struct usart_buffer {
struct usartpacket_t packet;
//transfer area ends here
volatile uint8_t busy;
volatile uint8_t error;
uint16_t requestedLength;
uint32_t errorInfo;
struct usartstatus_t *usartStatus;
};
struct usartstatus_t {
USART_TypeDef *usart;
DMAINFO rxDmaInfo;
DMAINFO txDmaInfo;
struct crcstatus_t *crcStatus;
struct crcslotlistitem_t crcSlot;
struct crcslottask_t crcTasks[2];
uint8_t rxSerial;
uint8_t txSerial;
struct usart_stats stats;
uint8_t activeRxBuf;
PACKETRECEIVEDCALLBACK packetReceivedCallback;
void *packetReceivedCallbacParam;
struct usart_buffer txBuffer;
struct usart_buffer rxBuffers[2];
};
#ifndef USART_STATS_DISABLED
static inline void StatsIncOverrun(struct usart_stats *s) {
++s->overrun;
}
static inline void StatsIncHdrError(struct usart_stats *s, uint32_t hdr) {
++s->hdrError;
s->lastErrHdr = hdr;
}
static inline void StatsIncPayloadError(struct usart_stats *s, uint32_t pep1, uint32_t pep2) {
++s->payloadErrror;
s->pep1 = pep1;
s->pep2 = pep2;
}
static inline void StatsIncDmaError(struct usart_stats *s) {
++s->dmaError;
}
static inline void StatsIncRcvd(struct usart_stats *s) {
++s->rcvd;
}
static inline void StatsIncPremature_hdr(struct usart_stats *s) {
++s->premature_hdr;
}
static inline void StatsIncPremature_payload(struct usart_stats *s) {
++s->premature_payload;
}
static inline void StatsIncSent(struct usart_stats *s) {
++s->sent;
}
static inline void StatsAddSkiped(struct usart_stats *s, uint8_t cnt) {
s->skiped += s->rcvd > 2 ? cnt : 0;
}
#else // USART_STATS_DISABLED
#define StatsIncOverrun(x)
#define StatsIncHdrError(x,y)
#define StatsIncPayloadError(x,y,z)
#define StatsIncDmaError(x)
#define StatsIncRcvd(x)
#define StatsIncPremature_hdr(x)
#define StatsIncPremature_payload(x)
#define StatsIncSent(x)
#define StatsAddSkiped(x)
#endif // USART_STATS_DISABLED
#endif /* UART_HANDLER_H_ */

68
components/f4ll_c/src/console_handler.c
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@ -1,68 +0,0 @@
/*
* interrupt.c
*
* Created on: Aug 29, 2019
* Author: abody
*/
#include "main.h"
#include "globals.h"
#include "f4ll_c/usart_handler.h"
#include "f4ll_c/strutil.h"
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart) // debug usart
{
DIAG_INTERRUPT_IN();
if(*info->isReg & info->tcMask) { // DMA transfer complete
*info->ifcReg = info->tcMask;
LL_USART_EnableIT_TC(usart);
LL_DMA_DisableStream(info->dma, info->stream);
}
DIAG_INTERRUPT_OUT();
}
void HandleConsoleUsartIrq(USART_TypeDef *usart)
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_TC(usart) && LL_USART_IsEnabledIT_TC(usart)) // transmission complete
LL_USART_DisableIT_TC(usart);
DIAG_INTERRUPT_OUT();
}
#define ADDINFO(b,s,u) \
b += strcpy_ex(b,s); \
b += uitodec(b,u);
void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo)
{
char ids[] = " : ";
char *bs = buffer;
ids[0] = id + '0';
buffer += strcpy_ex(buffer, ids);
ADDINFO(buffer, " s: ", stats->sent);
ADDINFO(buffer, " r: ", stats->rcvd);
ADDINFO(buffer, " sk: ", stats->skiped);
ADDINFO(buffer, " or: ", stats->overrun);
ADDINFO(buffer, " he: ", stats->hdrError);
buffer += strcpy_ex(buffer,",0x");
buffer += uitohex(buffer, stats->lastErrHdr, 8);
ADDINFO(buffer, " pe: ", stats->payloadErrror);
buffer += strcpy_ex(buffer,",0x");
buffer += uitohex(buffer, stats->pep1, 8);
buffer += strcpy_ex(buffer,",0x");
buffer += uitohex(buffer, stats->pep2, 8);
ADDINFO(buffer, " de: ", stats->dmaError);
ADDINFO(buffer, " pmh: ", stats->premature_hdr);
ADDINFO(buffer, " pmp: ", stats->premature_payload);
buffer += strcpy_ex(buffer, "\r\n");
SetupTransmit(usart, dmaInfo->dma, dmaInfo->stream, bs, buffer - bs + 1);
}

179
components/f4ll_c/src/crc_handler.c
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@ -1,179 +0,0 @@
/*
* interrupt.c
*
* Created on: Aug 29, 2019
* Author: abody
*/
#include "main.h"
#include <string.h>
#include <platform/crc_ll.h>
#include "diag.h"
#include "f4ll_c/dma_helper.h"
#include "f4ll_c/crc_handler.h"
#ifndef DIAG_CRC_CALC_START
# define DIAG_CRC_CALC_START()
#endif
#ifndef DIAG_CRC_CALC_END
# define DIAG_CRC_CALC_END()
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
void InitCrcStatus(struct crcstatus_t *st, DMA_TypeDef *dma, uint32_t stream)
{
InitDmaInfo(&st->dmaInfo, dma, stream);
LL_DMA_EnableIT_TC(dma, stream);
LL_DMA_EnableIT_TE(dma, stream);
LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
st->activeSlot = NULL;
st->first = NULL;
}
void AttachCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, struct crcslottask_t *tasks, uint8_t taskCount)
{
slot->count = taskCount;
slot->tasks = tasks;
memset(tasks, 0, sizeof(*tasks)*taskCount);
uint32_t prim = __get_PRIMASK();
__disable_irq();
slot->next = status->first;
status->first = slot;
__set_PRIMASK(prim);
}
uint8_t GetActiveTask(struct crcslotlistitem_t **slot_out, struct crcstatus_t volatile *status)
{
uint8_t ret;
uint32_t prim = __get_PRIMASK();
__disable_irq();
ret = status->activeTask;
if(slot_out)
*slot_out = (struct crcslotlistitem_t *) status->activeSlot;
__set_PRIMASK(prim);
return ret;
}
uint8_t EnqueueCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task,
uint8_t *address, uint16_t len, void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
{
uint32_t prim = __get_PRIMASK();
uint16_t need_start;
struct crcstatus_t volatile *st = status;
while(st->activeSlot == slot && st->activeTask == task);
__disable_irq();
need_start = (st->activeSlot == NULL);
slot->tasks[task].address = need_start ? NULL : address;
slot->tasks[task].wordCount = (len+3)/4;
slot->tasks[task].callback = callback;
slot->tasks[task].callbackParam = callbackParam;
if(need_start) {
status->activeSlot = slot;
status->activeTask = task;
}
__set_PRIMASK(prim);
if(need_start) {
CRC->CR = 1;
LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)address);
LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, (len+3)/4);
DIAG_CRC_CALC_START();
LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
}
return need_start;
}
void WaitCrcResults(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task)
{
struct crcslotlistitem_t *slotQueued;
while(IsSlotQueued(slot, task));
while(GetActiveTask(&slotQueued, status) == task && slotQueued == slot);
}
uint32_t ComputeCrc(struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task, uint8_t *address, uint16_t len)
{
uint32_t result;
EnqueueCrcTask(status, slot, task, address, len, NULL, &result);
while((struct crcslotlistitem_t volatile *)slot->tasks[task].callbackParam);
return result;
}
// only called from ISR context
static void StartNextCrcTask(struct crcstatus_t *status)
{
char moreTasks;
uint8_t index = 0;
do {
struct crcslotlistitem_t *slot = status->first;
moreTasks = 0;
while(slot) {
if(index < slot->count) {
if(slot->tasks[index].address) {
status->activeSlot = slot;
status->activeTask = index;
CRC->CR = 1;
LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)slot->tasks[index].address);
LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, slot->tasks[index].wordCount);
LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
slot->tasks[index].address = NULL; // marking as started
return;
}
if(index + 1 < slot->count)
moreTasks = 1;
}
slot = slot->next;
}
++index;
} while(moreTasks);
status->activeSlot = NULL;
}
void HandleCrcDmaIrq(struct crcstatus_t *status)
{
DIAG_INTERRUPT_IN();
if(*status->dmaInfo.isReg & status->dmaInfo.tcMask) { // DMA transfer complete
*status->dmaInfo.ifcReg = status->dmaInfo.tcMask;
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
if(status->activeSlot) {
struct crcslottask_t *tsk = &status->activeSlot->tasks[status->activeTask];
if(tsk->callback)
tsk->callback(tsk->callbackParam, CRC->DR, 1);
else if(tsk->callbackParam)
*(uint32_t*)tsk->callbackParam = CRC->DR;
tsk->callback = tsk->callbackParam = NULL; // marking as inactive
DIAG_CRC_CALC_END();
StartNextCrcTask(status);
}
}
else if(*status->dmaInfo.isReg & status->dmaInfo.teMask) {
*status->dmaInfo.ifcReg = status->dmaInfo.teMask;
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
if(status->activeSlot) {
struct crcslottask_t *tsk = &status->activeSlot->tasks[status->activeTask];
if(tsk->callback)
tsk->callback(tsk->callbackParam, CRC->DR, 0);
else if(tsk->callbackParam)
*(uint32_t*)tsk->callbackParam = 0xffffffff;
tsk->callback = tsk->callbackParam = NULL; // marking as inactive
DIAG_CRC_CALC_END();
StartNextCrcTask(status);
}
}
DIAG_INTERRUPT_OUT();
}

78
components/f4ll_c/src/dma_helper.c
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@ -1,78 +0,0 @@
/*
* dma_helper.c
*
* Created on: Sep 18, 2019
* Author: abody
*/
#include "f4ll_c/dma_helper.h"
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream)
{
if(dma == DMA1)
return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR;
else
return (stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR;
}
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream)
{
if(dma == DMA1)
return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR;
else
return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR;
}
uint32_t GetFeMask(uint32_t stream)
{
static const uint32_t feMasks[8] = {
DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7
};
return feMasks[stream];
}
uint32_t GetDmeMask(uint32_t stream)
{
static const uint32_t dmeMasks[8] = {
DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7
};
return dmeMasks[stream];
}
uint32_t GetTeMask(uint32_t stream)
{
static const uint32_t teMasks[8] = {
DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7
};
return teMasks[stream];
}
uint32_t GetHtMask(uint32_t stream)
{
static const uint32_t htMasks[8] = {
DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7
};
return htMasks[stream];
}
uint32_t GetTcMask(uint32_t stream)
{
static const uint32_t tcMasks[8] = {
DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7
};
return tcMasks[stream];
}
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream)
{
info->dma = dma;
info->stream = stream;
info->isReg = GetIsReg(dma, stream);
info->ifcReg = GetIfcReg(dma, stream);
info->feMask = GetFeMask(stream);
info->dmeMask = GetDmeMask(stream);
info->teMask = GetTeMask(stream);
info->htMask = GetHtMask(stream);
info->tcMask = GetTcMask(stream);
}

48
components/f4ll_c/src/memcpy_dma.c
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@ -1,48 +0,0 @@
/*
* memcpy_dma.c
*
* Created on: Oct 1, 2019
* Author: abody
*/
#include "f4ll_c/memcpy_dma.h"
#include "f4ll_c/dma_helper.h"
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
volatile uint8_t g_memcpyDmaBusy = 0;
static DMAINFO g_memcpyDmaInfo;
void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream)
{
InitDmaInfo(&g_memcpyDmaInfo, dma, stream);
LL_DMA_EnableIT_TC(dma, stream);
}
void * MemcpyDma(void *dst, void const *src, size_t length)
{
LL_DMA_SetM2MSrcAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)src);
LL_DMA_SetM2MDstAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)dst);
LL_DMA_SetDataLength(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (length+3)/4 );
g_memcpyDmaBusy = 1;
LL_DMA_EnableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
while(g_memcpyDmaBusy);
return dst;
}
void HandleMemcpyDmaIrq()
{
DIAG_INTERRUPT_IN();
if(*g_memcpyDmaInfo.isReg & g_memcpyDmaInfo.tcMask) { // DMA transfer complete
*g_memcpyDmaInfo.ifcReg = g_memcpyDmaInfo.tcMask;
LL_DMA_DisableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
g_memcpyDmaBusy = 0;
}
DIAG_INTERRUPT_OUT();
}

265
components/f4ll_c/src/usart_handler.c
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@ -1,265 +0,0 @@
/*
* usart_handler.c
*
* Created on: Sep 16, 2019
* Author: abody
*/
#include <string.h>
#include <platform/usart_ll.h>
#include "diag.h"
#include "f4ll_c/usart_handler.h"
#include "f4ll_c/dma_helper.h"
#include "f4ll_c/crc_handler.h"
#include "f4ll_c/memcpy_dma.h"
#ifndef DIAG_RX_BUFFER_SWITCH
# define DIAG_RX_BUFFER_SWITCH(x)
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
#define STARTMARKER 0x95
static inline uint32_t RoundUpTo4(uint32_t inp)
{
return (inp + 3) & 0xfffc;
}
void InitUartStatus(
struct usartstatus_t *st, USART_TypeDef *usart, DMA_TypeDef *dma,
uint32_t stream_rx, uint32_t stream_tx,
struct crcstatus_t *crcStatus,
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
{
uint32_t status = usart->SR;
volatile uint32_t tmpreg = usart->DR; // clearing some of the error/status bits in the USART
(void) tmpreg;
(void) status;
st->usart = usart;
InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
st->txBuffer.busy = 0;
st->txBuffer.error = 0;
st->txBuffer.requestedLength = 0;
st->rxBuffers[0].busy = 0;
st->rxBuffers[1].busy = 0;
st->rxBuffers[0].error = 0;
st->rxBuffers[1].error = 0;
st->rxBuffers[0].requestedLength = 0;
st->rxBuffers[1].requestedLength = 0;
st->txBuffer.usartStatus = st;
st->rxBuffers[0].usartStatus = st;
st->rxBuffers[1].usartStatus = st;
st->packetReceivedCallback = packetReceivedCallback;
st->packetReceivedCallbacParam = packetReceivedCallbackParam;
st->rxSerial = -1;
st->txSerial = 0;
st->activeRxBuf = 0;
st->crcStatus = crcStatus;
AttachCrcTask(crcStatus, &st->crcSlot, st->crcTasks, 2);
memset(&st->stats, 0, sizeof(st->stats));
*GetIfcReg(dma, stream_rx) =
GetTcMask(stream_rx) | GetHtMask(stream_rx) |
GetTeMask(stream_rx) | GetFeMask(stream_rx) | GetDmeMask(stream_rx);
*GetIfcReg(dma, stream_tx) =
GetTcMask(stream_tx) | GetHtMask(stream_tx) |
GetTeMask(stream_tx) | GetFeMask(stream_tx) | GetDmeMask(stream_tx);
LL_DMA_EnableIT_TC(dma, stream_rx);
LL_DMA_EnableIT_TE(dma, stream_rx);
LL_DMA_EnableIT_TC(dma, stream_tx);
LL_DMA_EnableIT_TE(dma, stream_tx);
LL_USART_EnableIT_IDLE(usart);
}
uint8_t* GetTxBuffer(struct usartstatus_t *status)
{
return status->txBuffer.packet.payload;
}
static inline void BuildHeader(struct usart_buffer *buffer, uint8_t serial, uint8_t length)
{
uint8_t hash = STARTMARKER;
buffer->packet.header.startByte = STARTMARKER;
buffer->packet.header.serial = serial;
hash ^= serial;
buffer->packet.header.payloadLength = length - 1;
hash ^= length - 1;
buffer->packet.header.hash = hash;
}
static inline uint8_t CheckHeader(struct usartpacket_t *packet)
{
return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
}
uint8_t PostPacket(struct usartstatus_t *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue)
{
// static uint32_t count = 0;
// ITM->PORT[1].u32 = count++;
if(length > 256)
return 1;
BuildHeader(&status->txBuffer, status->txSerial++, length);
uint16_t payloadLength = RoundUpTo4(length);
if(payload)
memcpy(status->txBuffer.packet.payload, payload, length);
status->txBuffer.requestedLength = sizeof(struct usartpacketheader_t) + payloadLength + sizeof(uint32_t); // +4 for the hash
status->txBuffer.busy = 1;
status->txBuffer.error = 0;
EnqueueCrcTask(status->crcStatus, &status->crcSlot, 0, status->txBuffer.packet.payload, length,
NULL, (uint32_t*)(status->txBuffer.packet.payload + payloadLength));
while(waitForCrcQueue && IsSlotQueued(&status->crcSlot, 0));
SetupTransmit(status->usart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
StatsIncSent(&status->stats);
return 0;
}
void SetupReceive(struct usartstatus_t *status)
{
uint8_t packetIndex = status->activeRxBuf;
LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->usart), (uint32_t)&status->rxBuffers[packetIndex],
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
status->rxBuffers[packetIndex].requestedLength = sizeof(status->rxBuffers[packetIndex].packet);
LL_DMA_SetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream, status->rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
LL_USART_EnableDMAReq_RX(status->usart);
LL_USART_ClearFlag_ORE(status->usart);
LL_DMA_EnableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
}
void ConsumePacket(struct usartstatus_t *status, uint8_t packetIndex)
{
struct usart_buffer *buffer = &status->rxBuffers[packetIndex];
if(buffer->busy) {
if(buffer->error)
StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + RoundUpTo4(buffer->packet.header.payloadLength + 1)));
else {
uint8_t diff = buffer->packet.header.serial - status->rxSerial;
if(diff > 1)
StatsAddSkiped(&status->stats, diff - 1);
status->rxSerial = buffer->packet.header.serial;
}
}
buffer->busy = buffer->error = 0;
}
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
{
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
LL_DMA_SetDataLength(dma, stream, length);
LL_USART_EnableDMAReq_TX(usart);
LL_DMA_EnableStream(dma, stream);
}
void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
{
struct usart_buffer *ub = (struct usart_buffer*) callbackParm;
if(!success)
ub->error = 1;
else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength + 1)) == calculatedCrc)
ub->busy = 1;
else {
ub->error = ub->busy = 1;
ub->errorInfo = calculatedCrc;
}
if(ub->usartStatus->packetReceivedCallback)
ub->usartStatus->packetReceivedCallback(ub->usartStatus->packetReceivedCallbacParam, ub);
}
void HandleUsartRxDmaIrq(struct usartstatus_t *status)
{
DIAG_INTERRUPT_IN();
StatsIncRcvd(&status->stats);
if(*status->rxDmaInfo.isReg & status->rxDmaInfo.tcMask) {
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.tcMask;
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet))
EnqueueCrcTask(status->crcStatus, &status->crcSlot, 1,
status->rxBuffers[status->activeRxBuf].packet.payload,
status->rxBuffers[status->activeRxBuf].packet.header.payloadLength +1,
RxCrcComputedCallback, &status->rxBuffers[status->activeRxBuf]);
else {
StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
status->rxBuffers[status->activeRxBuf].error = 1;
}
} else if(*status->rxDmaInfo.isReg & status->rxDmaInfo.teMask) {
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.teMask;
status->rxBuffers[status->activeRxBuf].error = 1;
}
status->activeRxBuf ^= 1;
DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
if(status->rxBuffers[status->activeRxBuf].busy)
StatsIncOverrun(&status->stats);
SetupReceive(status);
DIAG_INTERRUPT_OUT();
}
void HandleUsartTxDmaIrq(struct usartstatus_t *status)
{
DIAG_INTERRUPT_IN();
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
LL_USART_EnableIT_TC(status->usart);
LL_DMA_DisableStream(status->txDmaInfo.dma, status->txDmaInfo.stream);
}
else if(*status->txDmaInfo.isReg & status->txDmaInfo.teMask) {
*status->txDmaInfo.ifcReg = status->txDmaInfo.teMask;
status->txBuffer.error = 1;
StatsIncDmaError(&status->stats);
}
if(*status->txDmaInfo.isReg & status->txDmaInfo.feMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.feMask;
if(*status->txDmaInfo.isReg & status->txDmaInfo.htMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.htMask;
if(*status->txDmaInfo.isReg & status->txDmaInfo.dmeMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.dmeMask;
DIAG_INTERRUPT_OUT();
}
void HandleUsartIrq(struct usartstatus_t *status)
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
LL_USART_ClearFlag_IDLE(status->usart);
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
if(rcvdLen >= sizeof(struct usartpacketheader_t)) {
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
if(rcvdLen >= sizeof(struct usartpacketheader_t) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
else
StatsIncPremature_payload(&status->stats);
} else {
status->rxBuffers[status->activeRxBuf].error = 1;
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
}
} else
StatsIncPremature_hdr(&status->stats);
}
else if(LL_USART_IsActiveFlag_TC(status->usart) && LL_USART_IsEnabledIT_TC(status->usart)) { // transmission complete
LL_USART_DisableIT_TC(status->usart);
LL_USART_DisableDirectionTx(status->usart); // enforcing an idle frame
LL_USART_EnableDirectionTx(status->usart);
status->txBuffer.busy = 0;
}
DIAG_INTERRUPT_OUT();
}