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This commit is contained in:
Attila Body 2025-06-08 21:25:05 +02:00
parent a4e25d702b
commit 66c9d451ab
Signed by: abody
GPG key ID: BD0C6214E68FB5CF
14 changed files with 147 additions and 151 deletions
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2
components/app/inc/globals.h
View file

@ -11,5 +11,5 @@
#include <f4ll/packet_usart.h>
#include <inttypes.h>
extern f4ll::PacketUsart *g_usarts[USARTCOUNT];
extern f4ll::packet_usart *g_usarts[USARTCOUNT];
extern uint8_t g_statsBuf[256];

2
components/app/src/globals.cpp
View file

@ -10,6 +10,6 @@
#include <f4ll/memcpy_dma.h>
#include <f4ll/packet_usart.h>
f4ll::PacketUsart *g_usarts[USARTCOUNT];
f4ll::packet_usart *g_usarts[USARTCOUNT];
uint8_t g_statsBuf[256];

24
components/app/src/irq_bridge.cpp
View file

@ -8,46 +8,46 @@
void usart1_rx_dma_isr(void)
{
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART1_OFFSET]);
f4ll::packet_usart::rx_dma_isr(g_usarts[USART1_OFFSET]);
}
void usart1_tx_dma_isr(void)
{
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART1_OFFSET]);
f4ll::packet_usart::tx_dma_isr(g_usarts[USART1_OFFSET]);
}
void usart1_isr(void)
{
f4ll::PacketUsart::usart_isr(g_usarts[USART1_OFFSET]);
f4ll::packet_usart::usart_isr(g_usarts[USART1_OFFSET]);
}
//
void usart2_rx_dma_isr(void)
{
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART2_OFFSET]);
f4ll::packet_usart::rx_dma_isr(g_usarts[USART2_OFFSET]);
}
void usart2_tx_dma_isr(void)
{
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART2_OFFSET]);
f4ll::packet_usart::tx_dma_isr(g_usarts[USART2_OFFSET]);
}
void usart2_isr(void)
{
f4ll::PacketUsart::usart_isr(g_usarts[USART2_OFFSET]);
f4ll::packet_usart::usart_isr(g_usarts[USART2_OFFSET]);
}
//
void usart3_rx_dma_isr(void)
{
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART3_OFFSET]);
f4ll::packet_usart::rx_dma_isr(g_usarts[USART3_OFFSET]);
}
void usart3_tx_dma_isr(void)
{
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART3_OFFSET]);
f4ll::packet_usart::tx_dma_isr(g_usarts[USART3_OFFSET]);
}
void usart3_isr(void)
{
f4ll::PacketUsart::usart_isr(g_usarts[USART3_OFFSET]);
f4ll::packet_usart::usart_isr(g_usarts[USART3_OFFSET]);
}
//
@ -64,16 +64,16 @@ void usart4_isr(void)
//
void usart6_rx_dma_isr(void)
{
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART6_OFFSET]);
f4ll::packet_usart::rx_dma_isr(g_usarts[USART6_OFFSET]);
}
void usart6_tx_dma_isr(void)
{
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART6_OFFSET]);
f4ll::packet_usart::tx_dma_isr(g_usarts[USART6_OFFSET]);
}
void usart6_isr(void)
{
f4ll::PacketUsart::usart_isr(g_usarts[USART6_OFFSET]);
f4ll::packet_usart::usart_isr(g_usarts[USART6_OFFSET]);
}
void m2m1_dma_isr(void)

4
components/f4ll/inc/f4ll/console_handler.h
View file

@ -18,10 +18,10 @@ class console_handler : public usart_core, public singleton<console_handler>
friend class singleton<console_handler>;
public:
void PrintStats(uint8_t id, PacketUsart &usart);
void PrintStats(uint8_t id, packet_usart &usart);
private:
console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
// LL_UsartCore pure virtual function implementations
virtual void receiver_idle(void);

2
components/f4ll/inc/f4ll/crc_handler.h
View file

@ -84,7 +84,7 @@ private:
dma_helper m_dma;
slot_base volatile *m_first_slot = nullptr;
slot_base volatile *m_active_slot = nullptr;
int volatile m_activeTask;
int volatile m_active_task;
};
} // namespace f4ll

15
components/f4ll/inc/f4ll/dma_helper.h
View file

@ -43,11 +43,16 @@ private:
volatile uint32_t *m_is_reg;
volatile uint32_t *m_ifc_reg;
static const uint32_t m_fe_masks[8];
static const uint32_t m_dme_masks[8];
static const uint32_t m_te_masks[8];
static const uint32_t m_ht_masks[8];
static const uint32_t m_tc_masks[8];
static constexpr uint32_t const m_fe_masks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3,
DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
static constexpr uint32_t const m_dme_masks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3,
DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
static constexpr uint32_t const m_te_masks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3,
DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
static constexpr uint32_t const m_ht_masks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3,
DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
static constexpr uint32_t const m_tc_masks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3,
DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
};
} /* namespace f4ll */

28
components/f4ll/inc/f4ll/fault.h
View file

@ -10,7 +10,35 @@
extern "C" {
#endif
typedef struct
{
uint32_t R0;
uint32_t R1;
uint32_t R2;
uint32_t R3;
uint32_t R4;
uint32_t R5;
uint32_t R6;
uint32_t R7;
uint32_t R8;
uint32_t R9;
uint32_t R10;
uint32_t R11;
uint32_t R12;
uint32_t SP;
uint32_t LR;
uint32_t PC;
uint32_t xPSR;
uint32_t PSP;
uint32_t MSP;
uint32_t EXC_RETURN;
uint32_t CONTROL;
} fault_context_t;
extern fault_context_t g_fault_context;
void app_fault_callback(uint32_t reason);
__attribute__((noreturn)) void fault_handler(uint32_t type, fault_context_t *context);
#ifdef __cplusplus
}

17
components/f4ll/inc/f4ll/irq_lock.h
View file

@ -6,22 +6,21 @@
namespace f4ll {
class IrqLock {
class irq_lock
{
public:
inline IrqLock() : m_primask(__get_PRIMASK()) {
inline irq_lock()
: m_primask(__get_PRIMASK())
{
__disable_irq();
}
inline void Release() {
__set_PRIMASK(m_primask);
}
inline void release() { __set_PRIMASK(m_primask); }
inline ~irq_lock() { __set_PRIMASK(m_primask); }
inline ~IrqLock() {
__set_PRIMASK(m_primask);
}
private:
uint32_t m_primask;
};
}
#endif // _IRQLOCK_H_INCLUDED

18
components/f4ll/inc/f4ll/packet_usart.h
View file

@ -15,23 +15,23 @@ namespace f4ll {
struct DMAINFO;
class PacketUsart : public crc_handler::icallback, public usart_core
class packet_usart : public crc_handler::icallback, public usart_core
{
// friend class UsartCore;
public:
PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
packet_usart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
struct PacketHeader
struct packet_header
{ // !!! size should be multiple of 4 !!!
uint8_t startByte;
uint8_t start_byte;
uint8_t serial;
uint8_t payloadLength;
uint8_t payload_length;
uint8_t hash;
};
struct Packet
{
PacketHeader header;
packet_header header;
uint8_t payload[256 + sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned));
@ -53,14 +53,14 @@ public:
struct IHsUsartCallback
{
virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
virtual bool PacketReceived(packet_usart *caller, uintptr_t userParam, Packet const &packet) = 0;
};
// crc_handler::ICallback interface functions
virtual void crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
virtual void crc_failed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
void PostPacket(uint8_t const *payload, uint8_t length, bool wait_for_crc_queue = true);
void SetupReceive(void);
void RxProcessed(bool second);
@ -79,7 +79,7 @@ public:
private:
void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
bool CheckHeader(PacketHeader &header);
bool CheckHeader(packet_header &header);
void SwitchRxBuffers(void);
// UsartCore pure virtual function implementations

8
components/f4ll/src/console_handler.cpp
View file

@ -10,8 +10,8 @@
namespace f4ll {
console_handler::console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
: usart_core(usart, dma, streamRx, streamTx)
console_handler::console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx)
: usart_core(usart, dma, stream_rx, stream_tx)
{
}
@ -49,11 +49,11 @@ void console_handler::tx_dma_error(dma_helper::dma_error_type reason)
b += strcpy_ex(b, s); \
b += uitodec(b, u);
void console_handler::PrintStats(uint8_t id, PacketUsart &usart)
void console_handler::PrintStats(uint8_t id, packet_usart &usart)
{
char ids[] = " : ";
char *buffer = m_buffer;
PacketUsart::Stats const &stats(usart.GetStats());
packet_usart::Stats const &stats(usart.GetStats());
ids[0] = id + '0';
buffer += strcpy_ex(buffer, ids);

42
components/f4ll/src/crc_handler.cpp
View file

@ -32,7 +32,7 @@ void crc_handler::attach_slot(slot_base &slot)
__set_PRIMASK(prim);
}
bool crc_handler::enqueue(slot_base &slot, uint8_t task, void const *address, uint16_t len, icallback *cb, uintptr_t cbParam)
bool crc_handler::enqueue(slot_base &slot, uint8_t task, void const *address, uint16_t len, icallback *cb, uintptr_t cb_param)
{
uint32_t prim = __get_PRIMASK();
bool immediate;
@ -47,10 +47,10 @@ bool crc_handler::enqueue(slot_base &slot, uint8_t task, void const *address, ui
slot[task].m_address = (!immediate) ? address : nullptr;
slot[task].m_word_count = (len + 3) / 4;
slot[task].m_callback = cb;
slot[task].m_callback_param = cbParam;
slot[task].m_callback_param = cb_param;
if (immediate) {
m_active_slot = &slot;
m_activeTask = task;
m_active_task = task;
}
__set_PRIMASK(prim);
@ -84,44 +84,44 @@ void crc_handler::dma_transfer_completed(void)
*m_dma.get_ifc_reg() = m_dma.get_tc_mask();
LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream());
if (m_active_slot) {
if ((*m_active_slot)[m_activeTask].m_callback) {
(*m_active_slot)[m_activeTask].m_callback->crc_succeeded(
(*m_active_slot)[m_activeTask].m_callback_param, CRC->DR, m_activeTask);
} else if ((*m_active_slot)[m_activeTask].m_callback_param) {
*reinterpret_cast<uint32_t *>((*m_active_slot)[m_activeTask].m_callback_param) = CRC->DR;
if ((*m_active_slot)[m_active_task].m_callback) {
(*m_active_slot)[m_active_task].m_callback->crc_succeeded(
(*m_active_slot)[m_active_task].m_callback_param, CRC->DR, m_active_task);
} else if ((*m_active_slot)[m_active_task].m_callback_param) {
*reinterpret_cast<uint32_t *>((*m_active_slot)[m_active_task].m_callback_param) = CRC->DR;
}
}
} else if (*m_dma.get_is_reg() & m_dma.get_te_mask()) { // DMA transfer error
*m_dma.get_ifc_reg() = m_dma.get_te_mask();
LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream());
if (m_active_slot) {
if ((*m_active_slot)[m_activeTask].m_callback) {
(*m_active_slot)[m_activeTask].m_callback->crc_failed(
(*m_active_slot)[m_activeTask].m_callback_param, CRC->DR, m_activeTask);
} else if ((*m_active_slot)[m_activeTask].m_callback_param) {
*reinterpret_cast<uint32_t *>((*m_active_slot)[m_activeTask].m_callback_param) = -1;
if ((*m_active_slot)[m_active_task].m_callback) {
(*m_active_slot)[m_active_task].m_callback->crc_failed(
(*m_active_slot)[m_active_task].m_callback_param, CRC->DR, m_active_task);
} else if ((*m_active_slot)[m_active_task].m_callback_param) {
*reinterpret_cast<uint32_t *>((*m_active_slot)[m_active_task].m_callback_param) = -1;
}
}
}
(*m_active_slot)[m_activeTask].m_callback = nullptr;
(*m_active_slot)[m_activeTask].m_callback_param = 0;
(*m_active_slot)[m_activeTask].m_word_count = 0;
(*m_active_slot)[m_active_task].m_callback = nullptr;
(*m_active_slot)[m_active_task].m_callback_param = 0;
(*m_active_slot)[m_active_task].m_word_count = 0;
start_next_task();
}
void crc_handler::start_next_task(void)
{
bool moreTasks;
bool more_tasks;
uint8_t index = 0;
do {
slot_base volatile *slot = m_first_slot;
moreTasks = false;
more_tasks = false;
while (slot) {
if (index < slot->m_task_count) {
if ((*slot)[index].m_address) {
m_active_slot = slot;
m_activeTask = index;
m_active_task = index;
CRC->CR = 1;
LL_DMA_SetM2MSrcAddress(m_dma.get_dma(), m_dma.get_stream(), reinterpret_cast<uint32_t>((*slot)[index].m_address));
LL_DMA_SetDataLength(m_dma.get_dma(), m_dma.get_stream(), (*slot)[index].m_word_count);
@ -130,13 +130,13 @@ void crc_handler::start_next_task(void)
return;
}
if (index + 1 < slot->m_task_count) {
moreTasks = true;
more_tasks = true;
}
}
slot = slot->m_next;
}
++index;
} while (moreTasks);
} while (more_tasks);
m_active_slot = nullptr;
}

11
components/f4ll/src/dma_helper.cpp
View file

@ -9,17 +9,6 @@ q * ll_dmahelper.cpp
namespace f4ll {
const uint32_t dma_helper::m_fe_masks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3,
DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
const uint32_t dma_helper::m_dme_masks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3,
DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
const uint32_t dma_helper::m_te_masks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3,
DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
const uint32_t dma_helper::m_ht_masks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3,
DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
const uint32_t dma_helper::m_tc_masks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3,
DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
dma_helper::dma_helper(DMA_TypeDef *dma, uint32_t stream)
: m_dma(dma),
m_stream(stream),

45
components/f4ll/src/fault.cpp
View file

@ -15,38 +15,14 @@
extern "C" {
#endif
typedef struct {
uint32_t R0;
uint32_t R1;
uint32_t R2;
uint32_t R3;
uint32_t R4;
uint32_t R5;
uint32_t R6;
uint32_t R7;
uint32_t R8;
uint32_t R9;
uint32_t R10;
uint32_t R11;
uint32_t R12;
uint32_t SP;
uint32_t LR;
uint32_t PC;
uint32_t xPSR;
uint32_t PSP;
uint32_t MSP;
uint32_t EXC_RETURN;
uint32_t CONTROL;
} fault_context_t;
fault_context_t g_faultContext;
fault_context_t g_fault_context;
void __attribute__((weak)) app_fault_callback(uint32_t reason)
{
(void)reason;
}
void SwoSendStr(char const *str, uint8_t len, uint8_t port)
void swo_send_str(char const *str, uint8_t len, uint8_t port)
{
while(len) {
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && // ITM enabled
@ -77,24 +53,23 @@ void SwoSendStr(char const *str, uint8_t len, uint8_t port)
void fault_print_str(char const *fmtstr, uint32_t *values)
{
char hex_str[9]={0};
char const *nextChunk = fmtstr;
char const *next_chunk = fmtstr;
while(*fmtstr) {
if(*fmtstr == '%') {
SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
swo_send_str(next_chunk, fmtstr - next_chunk, 0);
uitohex(hex_str, *values++, 8);
SwoSendStr(hex_str, 8, 0);
nextChunk = fmtstr +1;
swo_send_str(hex_str, 8, 0);
next_chunk = fmtstr + 1;
}
++fmtstr;
}
if(nextChunk != fmtstr)
SwoSendStr(nextChunk, fmtstr-nextChunk, 0);
if (next_chunk != fmtstr) {
swo_send_str(next_chunk, fmtstr - next_chunk, 0);
}
}
__attribute__((noreturn)) void FaultHandler(uint32_t type, fault_context_t *context)
void fault_handler(uint32_t type, fault_context_t *context)
{
uint32_t FSR[9] = {
SCB->HFSR,

66
components/f4ll/src/packet_usart.cpp
View file

@ -9,12 +9,12 @@
namespace f4ll {
template <typename T> static inline T RoundUpTo4(T input)
template <typename T> static inline T round_up_to_4(T input)
{
return (input + 3) & (((T)-1) - 3);
}
PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
packet_usart::packet_usart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
: usart_core(usart, dma, streamRx, streamTx)
{
crc_handler::instance().attach_slot(m_crcSlot);
@ -22,35 +22,35 @@ PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream
LL_USART_EnableIT_ERROR(usart);
}
void PacketUsart::RxProcessed(bool second)
void packet_usart::RxProcessed(bool second)
{
m_rxBuffers[second].busy = false;
m_rxBuffers[second].error = false;
}
void PacketUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
void packet_usart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
{
m_userCallback = callback;
m_userCallbackParam = callbackParam;
}
void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
void packet_usart::PostPacket(uint8_t const *payload, uint8_t length, bool wait_for_crc_queue)
{
uint16_t payloadLength = RoundUpTo4((uint16_t)length);
uint16_t payload_length = round_up_to_4((uint16_t)length);
BuildHeader(m_txBuffer.packet, m_txSerialNo++, length);
if (payload) {
memcpy(m_txBuffer.packet.payload, payload, length);
}
m_txBuffer.requestedLength = sizeof(m_txBuffer.packet.header) + payloadLength + sizeof(uint32_t);
m_txBuffer.requestedLength = sizeof(m_txBuffer.packet.header) + payload_length + sizeof(uint32_t);
m_txBuffer.busy = true;
m_txBuffer.error = false;
crc_handler::instance().enqueue(
m_crcSlot, 0, &m_txBuffer.packet, sizeof(PacketHeader) + payloadLength, nullptr,
reinterpret_cast<uintptr_t>(m_txBuffer.packet.payload + payloadLength));
m_crcSlot, 0, &m_txBuffer.packet, sizeof(packet_header) + payload_length, nullptr,
reinterpret_cast<uintptr_t>(m_txBuffer.packet.payload + payload_length));
while (waitForCrcQueue && crc_handler::instance().is_queued(m_crcSlot, 0))
while (wait_for_crc_queue && crc_handler::instance().is_queued(m_crcSlot, 0))
;
setup_transmit(&m_txBuffer.packet, m_txBuffer.requestedLength);
@ -58,7 +58,7 @@ void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFo
++m_stats.sent;
}
void PacketUsart::SetupReceive()
void packet_usart::SetupReceive()
{
m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
usart_core::setup_receive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
@ -68,13 +68,13 @@ void PacketUsart::SetupReceive()
// UsartCore pure virtual functions //
//////////////////////////////////////
void PacketUsart::receiver_idle(void)
void packet_usart::receiver_idle(void)
{
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rx_dma.get_dma(), m_rx_dma.get_stream());
if (rcvdLen >= sizeof(PacketHeader)) {
if (rcvdLen >= sizeof(packet_header)) {
if (CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
if (rcvdLen >= sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength) +
if (rcvdLen >= sizeof(packet_header) + round_up_to_4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payload_length) +
sizeof(uint32_t)) {
LL_DMA_DisableStream(m_rx_dma.get_dma(), m_rx_dma.get_stream());
} else {
@ -89,23 +89,23 @@ void PacketUsart::receiver_idle(void)
}
}
void PacketUsart::transmission_complete(void)
void packet_usart::transmission_complete(void)
{
LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
LL_USART_EnableDirectionTx(m_usart);
m_txBuffer.busy = 0;
}
void PacketUsart::framing_error(void) {}
void packet_usart::framing_error(void) {}
void PacketUsart::overrun(void) {}
void packet_usart::overrun(void) {}
void PacketUsart::rx_dma_transfer_complete(void)
void packet_usart::rx_dma_transfer_complete(void)
{
if (CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
crc_handler::instance().enqueue(
m_crcSlot, 1, &m_rxBuffers[m_rxBufferSelector].packet,
sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength), this,
sizeof(packet_header) + round_up_to_4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payload_length), this,
m_rxBufferSelector);
} else {
++m_stats.hdrError;
@ -114,9 +114,9 @@ void PacketUsart::rx_dma_transfer_complete(void)
SwitchRxBuffers();
}
void PacketUsart::rx_dma_half_transfer(void) {}
void packet_usart::rx_dma_half_transfer(void) {}
void PacketUsart::rx_dma_error(dma_helper::dma_error_type reason)
void packet_usart::rx_dma_error(dma_helper::dma_error_type reason)
{
(void)reason;
@ -125,15 +125,15 @@ void PacketUsart::rx_dma_error(dma_helper::dma_error_type reason)
SwitchRxBuffers();
}
void PacketUsart::tx_dma_transfer_complete(void)
void packet_usart::tx_dma_transfer_complete(void)
{
LL_USART_EnableIT_TC(m_usart);
LL_DMA_DisableStream(m_tx_dma.get_dma(), m_tx_dma.get_stream());
}
void PacketUsart::tx_dma_half_transfer(void) {}
void packet_usart::tx_dma_half_transfer(void) {}
void PacketUsart::tx_dma_error(dma_helper::dma_error_type reason)
void packet_usart::tx_dma_error(dma_helper::dma_error_type reason)
{
(void)reason;
@ -145,24 +145,24 @@ void PacketUsart::tx_dma_error(dma_helper::dma_error_type reason)
// Private functions //
///////////////////////
void PacketUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
void packet_usart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
{
uint8_t hash = STARTMARKER;
packet.header.startByte = STARTMARKER;
packet.header.start_byte = STARTMARKER;
packet.header.serial = serialNo;
hash ^= serialNo;
packet.header.payloadLength = length;
packet.header.payload_length = length;
hash ^= length;
packet.header.hash = hash;
}
bool PacketUsart::CheckHeader(PacketHeader &header)
bool packet_usart::CheckHeader(packet_header &header)
{
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
return header.start_byte == STARTMARKER && (header.start_byte ^ header.serial ^ header.payload_length) == header.hash;
}
void PacketUsart::SwitchRxBuffers(void)
void packet_usart::SwitchRxBuffers(void)
{
++m_stats.rcvd;
m_rxBufferSelector = !m_rxBufferSelector;
@ -177,14 +177,14 @@ void PacketUsart::SwitchRxBuffers(void)
// crc_handler::ICallback //
///////////////////////////
void PacketUsart::crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
void packet_usart::crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
{
(void)task;
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
buf.busy = 1;
if (*(uint32_t *)(buf.packet.payload + RoundUpTo4((uint16_t)buf.packet.header.payloadLength)) != crc) {
if (*(uint32_t *)(buf.packet.payload + round_up_to_4((uint16_t)buf.packet.header.payload_length)) != crc) {
buf.error = 1;
buf.errorInfo = crc;
++m_stats.payloadErrror;
@ -194,7 +194,7 @@ void PacketUsart::crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t t
}
}
void PacketUsart::crc_failed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
void packet_usart::crc_failed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
{
(void)crc;
(void)task;