HsUsart renamed to PacketUsart, volatile usage review
This commit is contained in:
parent
7cdc79c2ac
commit
23a75f43c7
12 changed files with 179 additions and 171 deletions
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@ -8,7 +8,7 @@
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#include <string.h>
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#include <stdlib.h>
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#include "f4ll/hsusart.h"
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#include "f4ll/packetusart.h"
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#include "f4ll/crchandler.h"
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#include "f4ll/memcpydma.h"
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#include "f4ll/consolehandler.h"
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@ -30,7 +30,7 @@ extern "C" {
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extern "C" void MainLoop()
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{
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uint8_t const text2Send[] __attribute__((aligned(4))) =
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uint8_t const text2Send[] __attribute__((aligned(16))) =
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"Megszentsegtelenithetetlensegeskedeseitekert\r\n"
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"--------------------------------------------\r\n\0\0\0";
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@ -38,12 +38,12 @@ extern "C" void MainLoop()
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f4ll::CrcHandler::Init(DMA2, LL_DMA_STREAM_4);
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f4ll::ConsoleHandler::Init(UART4, CONSOLE_DMA_ENGINE, 0u, CONSOLE_TX_DMA_STREAM);
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f4ll::HsUsart u1{ USART1, DMA2, LL_DMA_STREAM_2, LL_DMA_STREAM_7 };
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f4ll::HsUsart u2{ USART2, DMA1, LL_DMA_STREAM_5, LL_DMA_STREAM_6 };
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f4ll::HsUsart u3{ USART3, DMA1, LL_DMA_STREAM_1, LL_DMA_STREAM_3 };
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f4ll::HsUsart u6{ USART6, DMA2, LL_DMA_STREAM_1, LL_DMA_STREAM_6 };
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f4ll::PacketUsart u1{ USART1, DMA2, LL_DMA_STREAM_2, LL_DMA_STREAM_7 };
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f4ll::PacketUsart u2{ USART2, DMA1, LL_DMA_STREAM_5, LL_DMA_STREAM_6 };
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f4ll::PacketUsart u3{ USART3, DMA1, LL_DMA_STREAM_1, LL_DMA_STREAM_3 };
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f4ll::PacketUsart u6{ USART6, DMA2, LL_DMA_STREAM_1, LL_DMA_STREAM_6 };
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f4ll::HsUsart * usarts[] = { &u1, &u2, &u3, &u6 };
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f4ll::PacketUsart * usarts[] = { &u1, &u2, &u3, &u6 };
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for(unsigned int i=0; i < sizeof(usarts) / sizeof(usarts[0]); ++i)
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g_usarts[i] = usarts[i];
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@ -81,8 +81,11 @@ extern "C" void MainLoop()
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//DIAG_EXIT_BUSY();
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}
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for(uint16_t rIdx = 0; rIdx < 2; ++rIdx)
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if(u->IsRxBusy((bool)rIdx) || u->IsRxFailed(rIdx))
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if(u->IsRxBusy((bool)rIdx) || u->IsRxFailed(rIdx)) {
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u->GetRxPacketBuffer(rIdx);
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// ...
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u->RxProcessed((bool)rIdx);
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}
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}
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if(tick - lastStatsTick > STATS_DELAY_MS) {
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f4ll::ConsoleHandler::Instance().PrintStats(statId, *usarts[statId]);
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@ -6,8 +6,8 @@
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*/
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#include "globals.h"
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#include <f4ll/hsusart.h>
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#include <f4ll/packetusart.h>
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#include <f4ll/memcpydma.h>
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f4ll::HsUsart *g_usarts[4];
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f4ll::PacketUsart *g_usarts[4];
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@ -9,9 +9,9 @@
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#define GLOBALS_CPP_H_
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#ifdef __cplusplus
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#include "f4ll/hsusart.h"
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#include "f4ll/packetusart.h"
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extern f4ll::HsUsart *g_usarts[4];
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extern f4ll::PacketUsart *g_usarts[4];
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#endif // __cplusplus
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#endif /* GLOBALS_CPP_H_ */
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@ -261,7 +261,7 @@ void DMA1_Stream3_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleTxDmaIrq(g_usarts[USART3_OFFSET]);
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART3_OFFSET]);
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#else
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HandleUsartTxDmaIrq(&g_uartStatuses[USART3_OFFSET]);
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#endif
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@ -297,7 +297,7 @@ void DMA1_Stream5_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleRxDmaIrq(g_usarts[USART2_OFFSET]);
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART2_OFFSET]);
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#else
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HandleUsartRxDmaIrq(&g_uartStatuses[USART2_OFFSET]);
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#endif
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@ -315,7 +315,7 @@ void DMA1_Stream6_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleTxDmaIrq(g_usarts[USART2_OFFSET]);
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART2_OFFSET]);
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#else
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HandleUsartTxDmaIrq(&g_uartStatuses[USART2_OFFSET]);
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#endif
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@ -359,7 +359,7 @@ void USART1_IRQHandler(void)
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{
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/* USER CODE BEGIN USART1_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleUsartIrq(g_usarts[USART1_OFFSET]);
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART1_OFFSET]);
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#else
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HandleUsartIrq(&g_uartStatuses[USART1_OFFSET]);
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#endif
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@ -376,7 +376,7 @@ void USART2_IRQHandler(void)
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{
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/* USER CODE BEGIN USART2_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleUsartIrq(g_usarts[USART2_OFFSET]);
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART2_OFFSET]);
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#else
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HandleUsartIrq(&g_uartStatuses[USART2_OFFSET]);
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#endif
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@ -393,7 +393,7 @@ void USART3_IRQHandler(void)
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{
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/* USER CODE BEGIN USART3_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleUsartIrq(g_usarts[USART3_OFFSET]);
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART3_OFFSET]);
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#else
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HandleUsartIrq(&g_uartStatuses[USART3_OFFSET]);
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#endif
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@ -441,7 +441,7 @@ void DMA2_Stream1_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream1_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleRxDmaIrq(g_usarts[USART6_OFFSET]);
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART6_OFFSET]);
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#else
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HandleUsartRxDmaIrq(&g_uartStatuses[USART6_OFFSET]);
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#endif
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@ -459,7 +459,7 @@ void DMA2_Stream2_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleRxDmaIrq(g_usarts[USART1_OFFSET]);
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART1_OFFSET]);
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#else
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HandleUsartRxDmaIrq(&g_uartStatuses[USART1_OFFSET]);
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#endif
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@ -527,7 +527,7 @@ void DMA2_Stream6_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream6_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleTxDmaIrq(g_usarts[USART6_OFFSET]);
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART6_OFFSET]);
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#else
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HandleUsartTxDmaIrq(&g_uartStatuses[USART6_OFFSET]);
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#endif
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@ -545,7 +545,7 @@ void DMA2_Stream7_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleTxDmaIrq(g_usarts[USART1_OFFSET]);
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART1_OFFSET]);
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#else
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HandleUsartTxDmaIrq(&g_uartStatuses[USART1_OFFSET]);
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#endif
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@ -563,7 +563,7 @@ void USART6_IRQHandler(void)
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{
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/* USER CODE BEGIN USART6_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::HsUsart::HandleUsartIrq(g_usarts[USART6_OFFSET]);
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART6_OFFSET]);
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#else
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HandleUsartIrq(&g_uartStatuses[USART6_OFFSET]);
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#endif
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#ifndef LL_CONSOLEHANDLER_H_
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#define LL_CONSOLEHANDLER_H_
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#include "f4ll/hsusart.h"
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#include "f4ll/packetusart.h"
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#include "singleton.h"
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friend class Singleton<ConsoleHandler>;
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public:
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void PrintStats(uint8_t id, PacketUsart &usart);
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private:
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ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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void PrintStats(uint8_t id, HsUsart &usart);
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private:
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ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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char m_buffer[128];
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uint16_t m_used = 0;
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};
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friend class CrcHandler;
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public:
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struct CrcTask {
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void const * volatile m_address; // changed to nullptr when execution starts
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uint16_t volatile m_wordCount;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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void const * m_address; // changed to nullptr when execution starts
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uint16_t m_wordCount;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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};
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private:
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SlotBase *m_next = nullptr;
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SlotBase volatile *m_next = nullptr;
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uint8_t m_taskCount;
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virtual CrcTask& operator[](int index) = 0;
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virtual CrcTask volatile & operator[](int index) volatile = 0;
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protected:
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SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
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{
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public:
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Slot() : SlotBase(n) {}
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virtual CrcTask& operator[](int index) { return m_tasks[index]; }
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virtual CrcTask volatile & operator[](int index) volatile { return m_tasks[index]; }
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private:
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Slot::CrcTask m_tasks[n];
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bool IsQueued(SlotBase &slot, uint8_t task) const;
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bool IsRunning(SlotBase &slot, uint8_t task) const;
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void DmaTransferCompleted(void);
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void DmaTransferCompleted(void);
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private:
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CrcHandler(DMA_TypeDef *dma, uint32_t stream);
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void StartNextTask(void);
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void WaitResults(SlotBase &slot, uint8_t task) const;
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DmaHelper m_dma;
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SlotBase * volatile m_firstSlot = nullptr;
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SlotBase * volatile m_activeSlot = nullptr;
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int volatile m_activeTask;
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DmaHelper m_dma;
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SlotBase volatile *m_firstSlot = nullptr;
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SlotBase volatile *m_activeSlot = nullptr;
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int volatile m_activeTask;
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};
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struct DMAINFO;
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class HsUsart : public CrcHandler::ICallback, public UsartCore
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class PacketUsart : public CrcHandler::ICallback, public UsartCore
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{
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// friend class UsartCore;
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public:
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HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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struct PacketHeader { // !!! size should be multiple of 4 !!!
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uint8_t startByte;
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} __attribute__((aligned));
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struct Stats {
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uint32_t overrun = 0;
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uint32_t hdrError = 0;
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uint32_t payloadErrror = 0;
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uint32_t pep1 = 0;
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uint32_t pep2 = 0;
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uint32_t rxDmaError = 0;
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uint32_t txDmaError = 0;
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uint32_t rcvd = 0;
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uint32_t premature_hdr = 0;
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uint32_t overrun = 0;
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uint32_t hdrError = 0;
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uint32_t payloadErrror = 0;
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uint32_t pep1 = 0;
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uint32_t pep2 = 0;
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uint32_t rxDmaError = 0;
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uint32_t txDmaError = 0;
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uint32_t rcvd = 0;
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uint32_t premature_hdr = 0;
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uint32_t premature_payload = 0;
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uint32_t sent = 0;
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uint32_t skiped = 0;
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uint32_t sent = 0;
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uint32_t skiped = 0;
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};
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struct IHsUsartCallback {
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virtual bool PacketReceived(HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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};
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// CRCHandler::ICallback interface functions
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
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// UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
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void SetupReceive(void);
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void RxProcessed(bool second);
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uint8_t* GetTxPacketBuffer(void);
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USART_TypeDef* GetUsart(void);
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Stats const & GetStats(void);
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bool IsTxBusy(void);
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bool IsTxFailed(void);
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bool IsRxBusy(bool second);
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bool IsRxFailed(bool second);
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// Getters
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uint8_t* GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
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uint8_t const * GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
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USART_TypeDef* GetUsart(void) const { return m_usart; }
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Stats const & GetStats(void) const { return m_stats; }
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inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
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inline bool IsTxFailed(void) const { return m_txBuffer.error; }
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inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
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inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
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void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
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bool CheckHeader(PacketHeader &header);
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void SwitchRxBuffers(void);
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// UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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struct Buffer {
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Packet packet;
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//transfer area ends here
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volatile bool busy = 0;
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volatile bool error = 0;
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bool volatile busy = 0;
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bool volatile error = 0;
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uint16_t requestedLength = 0;
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uint32_t errorInfo = 0;
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uint32_t errorInfo = 0;
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};
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static const uint8_t STARTMARKER = 0x95;
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static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
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static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
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void SetupTransmit(void const *buffer, uint16_t length);
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void SetupReceive(void *buffer, uint16_t length);
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protected:
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UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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virtual void ReceiverIdle() = 0;
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virtual void TransmissionComplete() = 0;
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USART_TypeDef *m_usart;
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DmaHelper m_rxDma;
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DmaHelper m_txDma;
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virtual void RxDmaTransferComplete() = 0;
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virtual void RxDmaHalfTransfer() = 0;
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private:
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virtual void ReceiverIdle(void) = 0;
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virtual void TransmissionComplete(void) = 0;
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virtual void FramingError(void) = 0;
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virtual void Overrun(void) = 0;
|
||||
|
||||
virtual void RxDmaTransferComplete(void) = 0;
|
||||
virtual void RxDmaHalfTransfer(void) = 0;
|
||||
virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
|
||||
|
||||
virtual void TxDmaTransferComplete() = 0;
|
||||
virtual void TxDmaHalfTransfer() = 0;
|
||||
virtual void TxDmaTransferComplete(void) = 0;
|
||||
virtual void TxDmaHalfTransfer(void) = 0;
|
||||
virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
|
||||
|
||||
void SetupTransmit(void const *buffer, uint16_t length);
|
||||
void SetupReceive(void *buffer, uint16_t length);
|
||||
|
||||
void UsartIsr();
|
||||
void RxDmaIsr();
|
||||
void TxDmaIsr();
|
||||
|
||||
USART_TypeDef *m_usart;
|
||||
DmaHelper m_rxDma;
|
||||
DmaHelper m_txDma;
|
||||
};
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
|
|
@ -17,6 +17,8 @@ ConsoleHandler::ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t
|
|||
|
||||
void ConsoleHandler::ReceiverIdle(void) {}
|
||||
void ConsoleHandler::TransmissionComplete(void) {}
|
||||
void ConsoleHandler::FramingError(void) {}
|
||||
void ConsoleHandler::Overrun(void) {}
|
||||
void ConsoleHandler::RxDmaTransferComplete(void) {}
|
||||
void ConsoleHandler::RxDmaHalfTransfer(void) {}
|
||||
void ConsoleHandler::RxDmaError(DmaHelper::DmaErrorType reason) {}
|
||||
|
@ -33,11 +35,11 @@ void ConsoleHandler::TxDmaError(DmaHelper::DmaErrorType reason) {}
|
|||
b += strcpy_ex(b,s); \
|
||||
b += uitodec(b,u);
|
||||
|
||||
void ConsoleHandler::PrintStats(uint8_t id, HsUsart &usart)
|
||||
void ConsoleHandler::PrintStats(uint8_t id, PacketUsart &usart)
|
||||
{
|
||||
char ids[] = " : ";
|
||||
char *buffer = m_buffer;
|
||||
HsUsart::Stats const &stats(usart.GetStats());
|
||||
PacketUsart::Stats const &stats(usart.GetStats());
|
||||
|
||||
ids[0] = id + '0';
|
||||
buffer += strcpy_ex(buffer, ids);
|
||||
|
|
|
@ -113,7 +113,7 @@ void CrcHandler::StartNextTask(void)
|
|||
uint8_t index = 0;
|
||||
|
||||
do {
|
||||
SlotBase *slot = m_firstSlot;
|
||||
SlotBase volatile *slot = m_firstSlot;
|
||||
moreTasks = false;
|
||||
while(slot) {
|
||||
if(index < slot->m_taskCount) {
|
||||
|
|
|
@ -5,7 +5,7 @@
|
|||
* Author: abody
|
||||
*/
|
||||
#include <string.h>
|
||||
#include "f4ll/hsusart.h"
|
||||
#include "f4ll/packetusart.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
|
@ -15,87 +15,28 @@ template<typename T> static inline T RoundUpTo4(T input)
|
|||
}
|
||||
|
||||
|
||||
HsUsart::HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
: UsartCore(usart, dma, streamRx, streamTx)
|
||||
{
|
||||
CrcHandler::Instance().AttachSlot(m_crcSlot);
|
||||
}
|
||||
|
||||
|
||||
uint8_t* HsUsart::GetTxPacketBuffer(void)
|
||||
{
|
||||
return m_txBuffer.packet.payload;
|
||||
}
|
||||
|
||||
|
||||
USART_TypeDef* HsUsart::GetUsart(void)
|
||||
{
|
||||
return m_usart;
|
||||
}
|
||||
|
||||
|
||||
HsUsart::Stats const & HsUsart::GetStats(void)
|
||||
{
|
||||
return m_stats;
|
||||
}
|
||||
|
||||
|
||||
bool HsUsart::IsTxBusy()
|
||||
{
|
||||
return m_txBuffer.busy;
|
||||
}
|
||||
|
||||
|
||||
bool HsUsart::IsTxFailed()
|
||||
{
|
||||
return m_txBuffer.error;
|
||||
}
|
||||
|
||||
|
||||
bool HsUsart::IsRxBusy(bool second)
|
||||
{
|
||||
return m_rxBuffers[second].busy;
|
||||
}
|
||||
|
||||
|
||||
bool HsUsart::IsRxFailed(bool second)
|
||||
{
|
||||
return m_rxBuffers[second].error;
|
||||
|
||||
}
|
||||
|
||||
void HsUsart::RxProcessed(bool second)
|
||||
void PacketUsart::RxProcessed(bool second)
|
||||
{
|
||||
m_rxBuffers[second].busy = false;
|
||||
m_rxBuffers[second].error = false;
|
||||
}
|
||||
|
||||
void HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
|
||||
|
||||
void PacketUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
|
||||
{
|
||||
m_userCallback = callback;
|
||||
m_userCallbackParam = callbackParam;
|
||||
}
|
||||
|
||||
void HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
|
||||
{
|
||||
uint8_t hash = STARTMARKER;
|
||||
|
||||
packet.header.startByte = STARTMARKER;
|
||||
packet.header.serial = serialNo;
|
||||
hash ^= serialNo;
|
||||
packet.header.payloadLength = length;
|
||||
hash ^= length;
|
||||
packet.header.hash = hash;
|
||||
}
|
||||
|
||||
|
||||
bool HsUsart::CheckHeader(PacketHeader &header)
|
||||
{
|
||||
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
|
||||
}
|
||||
|
||||
|
||||
void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
|
||||
void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
|
||||
{
|
||||
uint16_t payloadLength = RoundUpTo4((uint16_t)length);
|
||||
|
||||
|
@ -117,16 +58,21 @@ void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrc
|
|||
}
|
||||
|
||||
|
||||
void HsUsart::SetupReceive()
|
||||
void PacketUsart::SetupReceive()
|
||||
{
|
||||
m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
|
||||
UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
|
||||
}
|
||||
|
||||
|
||||
void HsUsart::ReceiverIdle(void)
|
||||
//////////////////////////////////////
|
||||
// UsartCore pure virtual functions //
|
||||
//////////////////////////////////////
|
||||
|
||||
void PacketUsart::ReceiverIdle(void)
|
||||
{
|
||||
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
|
||||
if(rcvdLen >= sizeof(PacketHeader)) {
|
||||
if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
|
||||
if(rcvdLen >= sizeof(PacketHeader) +
|
||||
|
@ -144,7 +90,7 @@ void HsUsart::ReceiverIdle(void)
|
|||
}
|
||||
|
||||
|
||||
void HsUsart::TransmissionComplete(void)
|
||||
void PacketUsart::TransmissionComplete(void)
|
||||
{
|
||||
LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(m_usart);
|
||||
|
@ -152,7 +98,13 @@ void HsUsart::TransmissionComplete(void)
|
|||
}
|
||||
|
||||
|
||||
void HsUsart::RxDmaTransferComplete(void)
|
||||
void PacketUsart::FramingError(void) {}
|
||||
|
||||
|
||||
void PacketUsart::Overrun(void) {}
|
||||
|
||||
|
||||
void PacketUsart::RxDmaTransferComplete(void)
|
||||
{
|
||||
if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
|
||||
CrcHandler::Instance().Enqueue(m_crcSlot, 1,
|
||||
|
@ -166,38 +118,61 @@ void HsUsart::RxDmaTransferComplete(void)
|
|||
SwitchRxBuffers();
|
||||
}
|
||||
|
||||
void HsUsart::RxDmaHalfTransfer(void)
|
||||
void PacketUsart::RxDmaHalfTransfer(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void HsUsart::RxDmaError(DmaHelper::DmaErrorType reason)
|
||||
void PacketUsart::RxDmaError(DmaHelper::DmaErrorType reason)
|
||||
{
|
||||
m_rxBuffers[m_rxBufferSelector].error = 1;
|
||||
++m_stats.rxDmaError;
|
||||
SwitchRxBuffers();
|
||||
}
|
||||
|
||||
void HsUsart::TxDmaTransferComplete(void)
|
||||
void PacketUsart::TxDmaTransferComplete(void)
|
||||
{
|
||||
LL_USART_EnableIT_TC(m_usart);
|
||||
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
|
||||
}
|
||||
|
||||
|
||||
void HsUsart::TxDmaHalfTransfer(void)
|
||||
void PacketUsart::TxDmaHalfTransfer(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void HsUsart::TxDmaError(DmaHelper::DmaErrorType reason)
|
||||
void PacketUsart::TxDmaError(DmaHelper::DmaErrorType reason)
|
||||
{
|
||||
m_txBuffer.error = 1;
|
||||
++m_stats.txDmaError;
|
||||
}
|
||||
|
||||
|
||||
void HsUsart::SwitchRxBuffers(void)
|
||||
///////////////////////
|
||||
// Private functions //
|
||||
///////////////////////
|
||||
|
||||
void PacketUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
|
||||
{
|
||||
uint8_t hash = STARTMARKER;
|
||||
|
||||
packet.header.startByte = STARTMARKER;
|
||||
packet.header.serial = serialNo;
|
||||
hash ^= serialNo;
|
||||
packet.header.payloadLength = length;
|
||||
hash ^= length;
|
||||
packet.header.hash = hash;
|
||||
}
|
||||
|
||||
|
||||
bool PacketUsart::CheckHeader(PacketHeader &header)
|
||||
{
|
||||
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
|
||||
}
|
||||
|
||||
|
||||
void PacketUsart::SwitchRxBuffers(void)
|
||||
{
|
||||
++m_stats.rcvd;
|
||||
m_rxBufferSelector = !m_rxBufferSelector;
|
||||
|
@ -207,8 +182,11 @@ void HsUsart::SwitchRxBuffers(void)
|
|||
SetupReceive();
|
||||
}
|
||||
|
||||
///////////////////////////
|
||||
// CrcHandler::ICallback //
|
||||
///////////////////////////
|
||||
|
||||
void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
void PacketUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
{
|
||||
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
|
||||
|
||||
|
@ -223,7 +201,7 @@ void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
|||
}
|
||||
|
||||
|
||||
void HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
void PacketUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
{
|
||||
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
|
||||
buf.busy = buf.error = true;
|
|
@ -19,16 +19,29 @@ UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx,
|
|||
LL_DMA_EnableIT_TC(dma, streamTx);
|
||||
LL_DMA_EnableIT_TE(dma, streamTx);
|
||||
LL_USART_EnableIT_IDLE(usart);
|
||||
LL_USART_EnableIT_ERROR(usart);
|
||||
}
|
||||
|
||||
|
||||
void UsartCore::UsartIsr()
|
||||
{
|
||||
if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(m_usart);
|
||||
ReceiverIdle();
|
||||
} else if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
|
||||
if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(m_usart);
|
||||
TransmissionComplete();
|
||||
} else if(LL_USART_IsEnabledIT_ERROR(m_usart)) {
|
||||
uint32_t status = m_usart->SR;
|
||||
volatile uint32_t tmpreg = m_usart->DR; // clearing some of the error/status bits in the HW
|
||||
(void) tmpreg;
|
||||
|
||||
if(status & USART_SR_IDLE) {
|
||||
ReceiverIdle();
|
||||
}
|
||||
if(status & USART_SR_FE) {
|
||||
FramingError();
|
||||
}
|
||||
if(status & USART_SR_ORE) {
|
||||
Overrun();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue