581 lines
14 KiB
C
581 lines
14 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file stm32f4xx_it.c
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* @brief Interrupt Service Routines.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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#ifdef __cplusplus
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extern "C" {
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "main.h"
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#include "stm32f4xx_it.h"
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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#ifndef USE_CPLUSPLUS
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#include "f4ll_c/usart_handler.h"
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#include "f4ll_c/crc_handler.h"
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#include "f4ll_c/console_handler.h"
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#include "f4ll_c/memcpy_dma.h"
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#endif
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#include "globals.h"
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#include "diag.h"
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}
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#ifdef USE_CPLUSPLUS
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#include "globals_cpp.h"
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#include "f4ll/memcpydma.h"
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#include "f4ll/consolehandler.h"
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#endif
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extern "C" {
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/* USER CODE END Includes */
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/* Private typedef -----------------------------------------------------------*/
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/* USER CODE BEGIN TD */
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#define HardFault_Handler(x) __attribute__((weak)) HardFault_Handler(x)
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#define MemManage_Handler(x) __attribute__((weak)) MemManage_Handler(x)
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#define BusFault_Handler(x) __attribute__((weak)) BusFault_Handler(x)
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#define UsageFault_Handler(x) __attribute__((weak)) UsageFault_Handler(x)
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/* USER CODE END TD */
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/* Private define ------------------------------------------------------------*/
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/* USER CODE BEGIN PD */
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/* USER CODE END PD */
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/* Private macro -------------------------------------------------------------*/
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/* USER CODE BEGIN PM */
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/* USER CODE END PM */
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/* Private variables ---------------------------------------------------------*/
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/* USER CODE BEGIN PV */
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/* USER CODE END PV */
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/* Private function prototypes -----------------------------------------------*/
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/* USER CODE BEGIN PFP */
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/* USER CODE END PFP */
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/* Private user code ---------------------------------------------------------*/
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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/* External variables --------------------------------------------------------*/
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/* USER CODE BEGIN EV */
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/* USER CODE END EV */
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/******************************************************************************/
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/* Cortex-M4 Processor Interruption and Exception Handlers */
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/******************************************************************************/
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/**
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* @brief This function handles Non maskable interrupt.
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*/
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void NMI_Handler(void)
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{
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/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
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/* USER CODE END NonMaskableInt_IRQn 0 */
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/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
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/* USER CODE END NonMaskableInt_IRQn 1 */
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}
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/**
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* @brief This function handles Hard fault interrupt.
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*/
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void HardFault_Handler(void)
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{
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/* USER CODE BEGIN HardFault_IRQn 0 */
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/* USER CODE END HardFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_HardFault_IRQn 0 */
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/* USER CODE END W1_HardFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Memory management fault.
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*/
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void MemManage_Handler(void)
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{
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/* USER CODE BEGIN MemoryManagement_IRQn 0 */
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/* USER CODE END MemoryManagement_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
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/* USER CODE END W1_MemoryManagement_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Pre-fetch fault, memory access fault.
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*/
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void BusFault_Handler(void)
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{
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/* USER CODE BEGIN BusFault_IRQn 0 */
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/* USER CODE END BusFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_BusFault_IRQn 0 */
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/* USER CODE END W1_BusFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Undefined instruction or illegal state.
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*/
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void UsageFault_Handler(void)
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{
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/* USER CODE BEGIN UsageFault_IRQn 0 */
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/* USER CODE END UsageFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
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/* USER CODE END W1_UsageFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles System service call via SWI instruction.
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*/
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void SVC_Handler(void)
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{
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/* USER CODE BEGIN SVCall_IRQn 0 */
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/* USER CODE END SVCall_IRQn 0 */
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/* USER CODE BEGIN SVCall_IRQn 1 */
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/* USER CODE END SVCall_IRQn 1 */
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}
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/**
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* @brief This function handles Debug monitor.
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*/
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void DebugMon_Handler(void)
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{
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/* USER CODE BEGIN DebugMonitor_IRQn 0 */
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/* USER CODE END DebugMonitor_IRQn 0 */
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/* USER CODE BEGIN DebugMonitor_IRQn 1 */
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/* USER CODE END DebugMonitor_IRQn 1 */
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}
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/**
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* @brief This function handles Pendable request for system service.
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*/
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void PendSV_Handler(void)
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{
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/* USER CODE BEGIN PendSV_IRQn 0 */
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/* USER CODE END PendSV_IRQn 0 */
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/* USER CODE BEGIN PendSV_IRQn 1 */
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/* USER CODE END PendSV_IRQn 1 */
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}
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/**
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* @brief This function handles System tick timer.
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*/
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void SysTick_Handler(void)
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{
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/* USER CODE BEGIN SysTick_IRQn 0 */
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/* USER CODE END SysTick_IRQn 0 */
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HAL_IncTick();
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/* USER CODE BEGIN SysTick_IRQn 1 */
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/* USER CODE END SysTick_IRQn 1 */
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}
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/******************************************************************************/
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/* STM32F4xx Peripheral Interrupt Handlers */
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/* Add here the Interrupt Handlers for the used peripherals. */
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/* For the available peripheral interrupt handler names, */
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/* please refer to the startup file (startup_stm32f4xx.s). */
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/******************************************************************************/
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/**
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* @brief This function handles DMA1 stream1 global interrupt.
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*/
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void DMA1_Stream1_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::UsartCore::HandleRxDmaIrq(g_usarts[USART3_OFFSET]);
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#else
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HandleUsartRxDmaIrq(&g_uartStatuses[USART3_OFFSET]);
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#endif
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/* USER CODE END DMA1_Stream1_IRQn 0 */
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/* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
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/* USER CODE END DMA1_Stream1_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream2 global interrupt.
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*/
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void DMA1_Stream2_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
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// console rx
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/* USER CODE END DMA1_Stream2_IRQn 0 */
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/* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
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/* USER CODE END DMA1_Stream2_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream3 global interrupt.
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*/
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void DMA1_Stream3_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART3_OFFSET]);
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#else
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HandleUsartTxDmaIrq(&g_uartStatuses[USART3_OFFSET]);
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#endif
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/* USER CODE END DMA1_Stream3_IRQn 0 */
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/* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
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/* USER CODE END DMA1_Stream3_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream4 global interrupt.
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*/
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void DMA1_Stream4_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::ConsoleHandler::HandleTxDmaIrq(&f4ll::ConsoleHandler::Instance());
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#else
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HandleConsoleUsartTxDmaIrq(&g_ConsoleTxDmaInfo, UART4);
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#endif
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/* USER CODE END DMA1_Stream4_IRQn 0 */
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/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
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/* USER CODE END DMA1_Stream4_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream5 global interrupt.
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*/
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void DMA1_Stream5_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART2_OFFSET]);
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#else
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HandleUsartRxDmaIrq(&g_uartStatuses[USART2_OFFSET]);
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#endif
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/* USER CODE END DMA1_Stream5_IRQn 0 */
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/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
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/* USER CODE END DMA1_Stream5_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 stream6 global interrupt.
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*/
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void DMA1_Stream6_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART2_OFFSET]);
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#else
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HandleUsartTxDmaIrq(&g_uartStatuses[USART2_OFFSET]);
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#endif
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/* USER CODE END DMA1_Stream6_IRQn 0 */
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/* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
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/* USER CODE END DMA1_Stream6_IRQn 1 */
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}
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/**
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* @brief This function handles SPI1 global interrupt.
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*/
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void SPI1_IRQHandler(void)
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{
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/* USER CODE BEGIN SPI1_IRQn 0 */
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/* USER CODE END SPI1_IRQn 0 */
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/* USER CODE BEGIN SPI1_IRQn 1 */
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/* USER CODE END SPI1_IRQn 1 */
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}
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/**
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* @brief This function handles SPI2 global interrupt.
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*/
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void SPI2_IRQHandler(void)
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{
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/* USER CODE BEGIN SPI2_IRQn 0 */
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/* USER CODE END SPI2_IRQn 0 */
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/* USER CODE BEGIN SPI2_IRQn 1 */
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/* USER CODE END SPI2_IRQn 1 */
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}
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/**
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* @brief This function handles USART1 global interrupt.
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*/
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void USART1_IRQHandler(void)
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{
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/* USER CODE BEGIN USART1_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART1_OFFSET]);
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#else
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HandleUsartIrq(&g_uartStatuses[USART1_OFFSET]);
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#endif
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/* USER CODE END USART1_IRQn 0 */
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/* USER CODE BEGIN USART1_IRQn 1 */
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/* USER CODE END USART1_IRQn 1 */
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}
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/**
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* @brief This function handles USART2 global interrupt.
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*/
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void USART2_IRQHandler(void)
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{
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/* USER CODE BEGIN USART2_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART2_OFFSET]);
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#else
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HandleUsartIrq(&g_uartStatuses[USART2_OFFSET]);
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#endif
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/* USER CODE END USART2_IRQn 0 */
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/* USER CODE BEGIN USART2_IRQn 1 */
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/* USER CODE END USART2_IRQn 1 */
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}
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/**
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* @brief This function handles USART3 global interrupt.
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*/
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void USART3_IRQHandler(void)
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{
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/* USER CODE BEGIN USART3_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART3_OFFSET]);
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#else
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HandleUsartIrq(&g_uartStatuses[USART3_OFFSET]);
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#endif
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/* USER CODE END USART3_IRQn 0 */
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/* USER CODE BEGIN USART3_IRQn 1 */
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/* USER CODE END USART3_IRQn 1 */
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}
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/**
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* @brief This function handles UART4 global interrupt.
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*/
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void UART4_IRQHandler(void)
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{
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/* USER CODE BEGIN UART4_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::ConsoleHandler::HandleUsartIrq(&f4ll::ConsoleHandler::Instance());
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#else
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HandleConsoleUsartIrq(UART4);
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#endif
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/* USER CODE END UART4_IRQn 0 */
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/* USER CODE BEGIN UART4_IRQn 1 */
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/* USER CODE END UART4_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream0 global interrupt.
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*/
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void DMA2_Stream0_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
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/* USER CODE END DMA2_Stream0_IRQn 0 */
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/* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
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/* USER CODE END DMA2_Stream0_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream1 global interrupt.
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*/
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void DMA2_Stream1_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream1_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART6_OFFSET]);
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#else
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HandleUsartRxDmaIrq(&g_uartStatuses[USART6_OFFSET]);
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#endif
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/* USER CODE END DMA2_Stream1_IRQn 0 */
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/* USER CODE BEGIN DMA2_Stream1_IRQn 1 */
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/* USER CODE END DMA2_Stream1_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream2 global interrupt.
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*/
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void DMA2_Stream2_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART1_OFFSET]);
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#else
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HandleUsartRxDmaIrq(&g_uartStatuses[USART1_OFFSET]);
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#endif
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/* USER CODE END DMA2_Stream2_IRQn 0 */
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/* USER CODE BEGIN DMA2_Stream2_IRQn 1 */
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/* USER CODE END DMA2_Stream2_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream3 global interrupt.
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*/
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void DMA2_Stream3_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream3_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::MemcpyDma::Instance().DmaTransferCompleted();
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#else
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HandleMemcpyDmaIrq();
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#endif
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/* USER CODE END DMA2_Stream3_IRQn 0 */
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/* USER CODE BEGIN DMA2_Stream3_IRQn 1 */
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/* USER CODE END DMA2_Stream3_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream4 global interrupt.
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*/
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void DMA2_Stream4_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream4_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::CrcHandler::Instance().DmaTransferCompleted();
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#else
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HandleCrcDmaIrq(&g_crcStatus);
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#endif
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/* USER CODE END DMA2_Stream4_IRQn 0 */
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/* USER CODE BEGIN DMA2_Stream4_IRQn 1 */
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/* USER CODE END DMA2_Stream4_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream5 global interrupt.
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*/
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void DMA2_Stream5_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream5_IRQn 0 */
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/* USER CODE END DMA2_Stream5_IRQn 0 */
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/* USER CODE BEGIN DMA2_Stream5_IRQn 1 */
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/* USER CODE END DMA2_Stream5_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream6 global interrupt.
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*/
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void DMA2_Stream6_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream6_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART6_OFFSET]);
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#else
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HandleUsartTxDmaIrq(&g_uartStatuses[USART6_OFFSET]);
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#endif
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/* USER CODE END DMA2_Stream6_IRQn 0 */
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/* USER CODE BEGIN DMA2_Stream6_IRQn 1 */
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/* USER CODE END DMA2_Stream6_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream7 global interrupt.
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*/
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void DMA2_Stream7_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
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#ifdef USE_CPLUSPLUS
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f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART1_OFFSET]);
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#else
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HandleUsartTxDmaIrq(&g_uartStatuses[USART1_OFFSET]);
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#endif
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/* USER CODE END DMA2_Stream7_IRQn 0 */
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/* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
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|
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|
/* USER CODE END DMA2_Stream7_IRQn 1 */
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}
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|
|
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/**
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|
* @brief This function handles USART6 global interrupt.
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|
*/
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|
void USART6_IRQHandler(void)
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|
{
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|
/* USER CODE BEGIN USART6_IRQn 0 */
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|
#ifdef USE_CPLUSPLUS
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|
f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART6_OFFSET]);
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#else
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HandleUsartIrq(&g_uartStatuses[USART6_OFFSET]);
|
|
#endif
|
|
/* USER CODE END USART6_IRQn 0 */
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|
/* USER CODE BEGIN USART6_IRQn 1 */
|
|
|
|
/* USER CODE END USART6_IRQn 1 */
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|
}
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|
|
|
/* USER CODE BEGIN 1 */
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|
|
|
}
|
|
#endif // __cplusplus
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|
/* USER CODE END 1 */
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|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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