HsUsart renamed to PacketUsart, volatile usage review

App/application_cpp.cpp

@@ -8,7 +8,7 @@
 
 #include <string.h>
 #include <stdlib.h>
-#include "f4ll/hsusart.h"
+#include "f4ll/packetusart.h"
 #include "f4ll/crchandler.h"
 #include "f4ll/memcpydma.h"
 #include "f4ll/consolehandler.h"
@@ -30,7 +30,7 @@ extern "C" {
 
 extern "C" void MainLoop()
 {
-	uint8_t const text2Send[]  __attribute__((aligned(4))) =
+	uint8_t const text2Send[]  __attribute__((aligned(16))) =
 			"Megszentsegtelenithetetlensegeskedeseitekert\r\n"
 			"--------------------------------------------\r\n\0\0\0";
 
@@ -38,12 +38,12 @@ extern "C" void MainLoop()
 	f4ll::CrcHandler::Init(DMA2, LL_DMA_STREAM_4);
 	f4ll::ConsoleHandler::Init(UART4, CONSOLE_DMA_ENGINE, 0u, CONSOLE_TX_DMA_STREAM);
 
-	f4ll::HsUsart u1{ USART1, DMA2, LL_DMA_STREAM_2, LL_DMA_STREAM_7 };
+	f4ll::PacketUsart u1{ USART1, DMA2, LL_DMA_STREAM_2, LL_DMA_STREAM_7 };
-	f4ll::HsUsart u2{ USART2, DMA1, LL_DMA_STREAM_5, LL_DMA_STREAM_6 };
+	f4ll::PacketUsart u2{ USART2, DMA1, LL_DMA_STREAM_5, LL_DMA_STREAM_6 };
-	f4ll::HsUsart u3{ USART3, DMA1, LL_DMA_STREAM_1, LL_DMA_STREAM_3 };
+	f4ll::PacketUsart u3{ USART3, DMA1, LL_DMA_STREAM_1, LL_DMA_STREAM_3 };
-	f4ll::HsUsart u6{ USART6, DMA2, LL_DMA_STREAM_1, LL_DMA_STREAM_6 };
+	f4ll::PacketUsart u6{ USART6, DMA2, LL_DMA_STREAM_1, LL_DMA_STREAM_6 };
 
-	f4ll::HsUsart * usarts[] = { &u1, &u2, &u3, &u6 };
+	f4ll::PacketUsart * usarts[] = { &u1, &u2, &u3, &u6 };
 	for(unsigned int i=0; i < sizeof(usarts) / sizeof(usarts[0]); ++i)
 		g_usarts[i] = usarts[i];
 
@@ -81,8 +81,11 @@ extern "C" void MainLoop()
 				//DIAG_EXIT_BUSY();
 			}
 			for(uint16_t rIdx = 0; rIdx < 2; ++rIdx)
-				if(u->IsRxBusy((bool)rIdx) || u->IsRxFailed(rIdx))
+				if(u->IsRxBusy((bool)rIdx) || u->IsRxFailed(rIdx)) {
+					u->GetRxPacketBuffer(rIdx);
+					// ...
 					u->RxProcessed((bool)rIdx);
+				}
 		}
 		if(tick - lastStatsTick > STATS_DELAY_MS) {
 			f4ll::ConsoleHandler::Instance().PrintStats(statId, *usarts[statId]);

App/globals_cpp.cpp

@@ -6,8 +6,8 @@
  */
 #include "globals.h"
 
-#include <f4ll/hsusart.h>
+#include <f4ll/packetusart.h>
 #include <f4ll/memcpydma.h>
 
-f4ll::HsUsart *g_usarts[4];
+f4ll::PacketUsart *g_usarts[4];
 

App/globals_cpp.h

@@ -9,9 +9,9 @@
 #define GLOBALS_CPP_H_
 
 #ifdef __cplusplus
-#include "f4ll/hsusart.h"
+#include "f4ll/packetusart.h"
 
-extern f4ll::HsUsart *g_usarts[4];
+extern f4ll::PacketUsart *g_usarts[4];
 
 #endif	//	__cplusplus
 #endif /* GLOBALS_CPP_H_ */

Src/stm32f4xx_it.c

@@ -261,7 +261,7 @@ void DMA1_Stream3_IRQHandler(void)
 {
   /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleTxDmaIrq(g_usarts[USART3_OFFSET]);
+  f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART3_OFFSET]);
 #else
   HandleUsartTxDmaIrq(&g_uartStatuses[USART3_OFFSET]);
 #endif
@@ -297,7 +297,7 @@ void DMA1_Stream5_IRQHandler(void)
 {
   /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleRxDmaIrq(g_usarts[USART2_OFFSET]);
+  f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART2_OFFSET]);
 #else
   HandleUsartRxDmaIrq(&g_uartStatuses[USART2_OFFSET]);
 #endif
@@ -315,7 +315,7 @@ void DMA1_Stream6_IRQHandler(void)
 {
   /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleTxDmaIrq(g_usarts[USART2_OFFSET]);
+  f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART2_OFFSET]);
 #else
   HandleUsartTxDmaIrq(&g_uartStatuses[USART2_OFFSET]);
 #endif
@@ -359,7 +359,7 @@ void USART1_IRQHandler(void)
 {
   /* USER CODE BEGIN USART1_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleUsartIrq(g_usarts[USART1_OFFSET]);
+  f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART1_OFFSET]);
 #else
   HandleUsartIrq(&g_uartStatuses[USART1_OFFSET]);
 #endif
@@ -376,7 +376,7 @@ void USART2_IRQHandler(void)
 {
   /* USER CODE BEGIN USART2_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-	f4ll::HsUsart::HandleUsartIrq(g_usarts[USART2_OFFSET]);
+	f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART2_OFFSET]);
 #else
 	  HandleUsartIrq(&g_uartStatuses[USART2_OFFSET]);
 #endif
@@ -393,7 +393,7 @@ void USART3_IRQHandler(void)
 {
   /* USER CODE BEGIN USART3_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-	f4ll::HsUsart::HandleUsartIrq(g_usarts[USART3_OFFSET]);
+	f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART3_OFFSET]);
 #else
 	  HandleUsartIrq(&g_uartStatuses[USART3_OFFSET]);
 #endif
@@ -441,7 +441,7 @@ void DMA2_Stream1_IRQHandler(void)
 {
   /* USER CODE BEGIN DMA2_Stream1_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleRxDmaIrq(g_usarts[USART6_OFFSET]);
+  f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART6_OFFSET]);
 #else
   HandleUsartRxDmaIrq(&g_uartStatuses[USART6_OFFSET]);
 #endif
@@ -459,7 +459,7 @@ void DMA2_Stream2_IRQHandler(void)
 {
   /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleRxDmaIrq(g_usarts[USART1_OFFSET]);
+  f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART1_OFFSET]);
 #else
   HandleUsartRxDmaIrq(&g_uartStatuses[USART1_OFFSET]);
 #endif
@@ -527,7 +527,7 @@ void DMA2_Stream6_IRQHandler(void)
 {
   /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleTxDmaIrq(g_usarts[USART6_OFFSET]);
+  f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART6_OFFSET]);
 #else
   HandleUsartTxDmaIrq(&g_uartStatuses[USART6_OFFSET]);
 #endif
@@ -545,7 +545,7 @@ void DMA2_Stream7_IRQHandler(void)
 {
   /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleTxDmaIrq(g_usarts[USART1_OFFSET]);
+  f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART1_OFFSET]);
 #else
   HandleUsartTxDmaIrq(&g_uartStatuses[USART1_OFFSET]);
 #endif
@@ -563,7 +563,7 @@ void USART6_IRQHandler(void)
 {
   /* USER CODE BEGIN USART6_IRQn 0 */
 #ifdef USE_CPLUSPLUS
-  f4ll::HsUsart::HandleUsartIrq(g_usarts[USART6_OFFSET]);
+  f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART6_OFFSET]);
 #else
   HandleUsartIrq(&g_uartStatuses[USART6_OFFSET]);
 #endif

components/f4ll/inc/consolehandler.h

@@ -8,7 +8,7 @@
 #ifndef LL_CONSOLEHANDLER_H_
 #define LL_CONSOLEHANDLER_H_
 
-#include "f4ll/hsusart.h"
+#include "f4ll/packetusart.h"
 #include "singleton.h"
 
 
@@ -19,9 +19,16 @@ class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
 	friend class Singleton<ConsoleHandler>;
 
 public:
+	void PrintStats(uint8_t id, PacketUsart &usart);
+
+private:
+	ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
+
 	// LL_UsartCore pure virtual function implementations
 	virtual void ReceiverIdle(void);
 	virtual void TransmissionComplete(void);
+	virtual void FramingError(void);
+	virtual void Overrun(void);
 	virtual void RxDmaTransferComplete(void);
 	virtual void RxDmaHalfTransfer(void);
 	virtual void RxDmaError(DmaHelper::DmaErrorType reason);
@@ -29,11 +36,6 @@ public:
 	virtual void TxDmaHalfTransfer(void);
 	virtual void TxDmaError(DmaHelper::DmaErrorType reason);
 
-	void PrintStats(uint8_t id, HsUsart &usart);
-
-private:
-	ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
-
 	char		m_buffer[128];
 	uint16_t	m_used = 0;
 };

components/f4ll/inc/crchandler.h

@@ -32,17 +32,17 @@ public:
 		friend class CrcHandler;
 	public:
 		struct CrcTask {
-			void const * volatile     m_address;			// changed to nullptr when execution starts
+			void const * m_address;			// changed to nullptr when execution starts
-			uint16_t volatile         m_wordCount;
+			uint16_t     m_wordCount;
-			ICallback                *m_callback;
+			ICallback   *m_callback;
-			uintptr_t                 m_callbackParam;
+			uintptr_t    m_callbackParam;
 		};
 
 	private:
-		SlotBase *m_next = nullptr;
+		SlotBase volatile *m_next = nullptr;
 		uint8_t   m_taskCount;
 
-		virtual CrcTask& operator[](int index) = 0;
+		virtual CrcTask volatile & operator[](int index) volatile = 0;
 
 	protected:
 		SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
@@ -54,7 +54,7 @@ public:
 	{
 	public:
 		Slot() : SlotBase(n) {}
-		virtual CrcTask& operator[](int index) { return m_tasks[index]; }
+		virtual CrcTask volatile & operator[](int index) volatile { return m_tasks[index]; }
 
 	private:
 		Slot::CrcTask m_tasks[n];
@@ -68,7 +68,7 @@ public:
 	bool     IsQueued(SlotBase &slot, uint8_t task) const;
 	bool     IsRunning(SlotBase &slot, uint8_t task) const;
 
-	void DmaTransferCompleted(void);
+	void     DmaTransferCompleted(void);
 
 private:
 	CrcHandler(DMA_TypeDef *dma, uint32_t stream);
@@ -77,10 +77,10 @@ private:
 	void StartNextTask(void);
 	void WaitResults(SlotBase &slot, uint8_t task) const;
 
-	DmaHelper               m_dma;
+	DmaHelper          m_dma;
-	SlotBase * volatile     m_firstSlot = nullptr;
+	SlotBase volatile *m_firstSlot = nullptr;
-	SlotBase * volatile     m_activeSlot = nullptr;
+	SlotBase volatile *m_activeSlot = nullptr;
-	int	volatile            m_activeTask;
+	int	volatile       m_activeTask;
 };
 
 

components/f4ll/inc/packetusart.h

@@ -15,10 +15,11 @@ namespace f4ll {
 
 struct DMAINFO;
 
-class HsUsart : public CrcHandler::ICallback, public UsartCore
+class PacketUsart : public CrcHandler::ICallback, public UsartCore
 {
+//	friend class UsartCore;
 public:
-	HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
+	PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
 
 	struct PacketHeader {	// !!! size should be multiple of 4 !!!
 		uint8_t startByte;
@@ -33,49 +34,42 @@ public:
 	} __attribute__((aligned));
 
 	struct Stats {
-		uint32_t overrun = 0;
+		uint32_t overrun           = 0;
-		uint32_t hdrError = 0;
+		uint32_t hdrError          = 0;
-		uint32_t payloadErrror = 0;
+		uint32_t payloadErrror     = 0;
-		uint32_t pep1 = 0;
+		uint32_t pep1              = 0;
-		uint32_t pep2 = 0;
+		uint32_t pep2              = 0;
-		uint32_t rxDmaError = 0;
+		uint32_t rxDmaError        = 0;
-		uint32_t txDmaError = 0;
+		uint32_t txDmaError        = 0;
-		uint32_t rcvd = 0;
+		uint32_t rcvd              = 0;
-		uint32_t premature_hdr = 0;
+		uint32_t premature_hdr     = 0;
 		uint32_t premature_payload = 0;
-		uint32_t sent = 0;
+		uint32_t sent              = 0;
-		uint32_t skiped = 0;
+		uint32_t skiped            = 0;
 	};
 
 	struct IHsUsartCallback {
-		virtual bool PacketReceived(HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
+		virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
 	};
 
 	// CRCHandler::ICallback interface functions
 	virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
 	virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
 
-	// UsartCore pure virtual function implementations
-	virtual void ReceiverIdle(void);
-	virtual void TransmissionComplete(void);
-	virtual void RxDmaTransferComplete(void);
-	virtual void RxDmaHalfTransfer(void);
-	virtual void RxDmaError(DmaHelper::DmaErrorType reason);
-	virtual void TxDmaTransferComplete(void);
-	virtual void TxDmaHalfTransfer(void);
-	virtual void TxDmaError(DmaHelper::DmaErrorType reason);
-
 	void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
 	void SetupReceive(void);
 
 	void RxProcessed(bool second);
-	uint8_t* GetTxPacketBuffer(void);
+
-	USART_TypeDef* GetUsart(void);
+	// Getters
-	Stats const & GetStats(void);
+	uint8_t* GetTxPacketBuffer(void)               { return m_txBuffer.packet.payload; }
-	bool IsTxBusy(void);
+	uint8_t const * GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
-	bool IsTxFailed(void);
+	USART_TypeDef* GetUsart(void) const            { return m_usart; }
-	bool IsRxBusy(bool second);
+	Stats const & GetStats(void) const             { return m_stats; }
-	bool IsRxFailed(bool second);
+	inline bool IsTxBusy(void) const               { return m_txBuffer.busy; }
+	inline bool IsTxFailed(void) const             { return m_txBuffer.error; }
+	inline bool IsRxBusy(bool second) const        { return m_rxBuffers[second].busy; }
+	inline bool IsRxFailed(bool second) const      { return m_rxBuffers[second].error; }
 
 	void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
 
@@ -84,13 +78,25 @@ private:
 	bool CheckHeader(PacketHeader &header);
 	void SwitchRxBuffers(void);
 
+	// UsartCore pure virtual function implementations
+	virtual void ReceiverIdle(void);
+	virtual void TransmissionComplete(void);
+	virtual void FramingError(void);
+	virtual void Overrun(void);
+	virtual void RxDmaTransferComplete(void);
+	virtual void RxDmaHalfTransfer(void);
+	virtual void RxDmaError(DmaHelper::DmaErrorType reason);
+	virtual void TxDmaTransferComplete(void);
+	virtual void TxDmaHalfTransfer(void);
+	virtual void TxDmaError(DmaHelper::DmaErrorType reason);
+
 	struct Buffer {
 		Packet packet;
 		//transfer area ends here
-		volatile bool busy = 0;
+		bool volatile busy       = 0;
-		volatile bool error = 0;
+		bool volatile error      = 0;
 		uint16_t requestedLength = 0;
-		uint32_t errorInfo = 0;
+		uint32_t errorInfo       = 0;
 	};
 
 	static const uint8_t STARTMARKER = 0x95;

components/f4ll/inc/usartcore.h

@@ -20,30 +20,34 @@ public:
 	static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
 	static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
 
+	void SetupTransmit(void const *buffer, uint16_t length);
+	void SetupReceive(void *buffer, uint16_t length);
+
 protected:
 	UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
 
-	virtual void ReceiverIdle() = 0;
+	USART_TypeDef *m_usart;
-	virtual void TransmissionComplete() = 0;
+	DmaHelper      m_rxDma;
+	DmaHelper      m_txDma;
 
-	virtual void RxDmaTransferComplete() = 0;
+private:
-	virtual void RxDmaHalfTransfer() = 0;
+	virtual void ReceiverIdle(void)                         = 0;
+	virtual void TransmissionComplete(void)                 = 0;
+	virtual void FramingError(void)                         = 0;
+	virtual void Overrun(void)                              = 0;
+
+	virtual void RxDmaTransferComplete(void)                = 0;
+	virtual void RxDmaHalfTransfer(void)                    = 0;
 	virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
 
-	virtual void TxDmaTransferComplete() = 0;
+	virtual void TxDmaTransferComplete(void)                = 0;
-	virtual void TxDmaHalfTransfer() = 0;
+	virtual void TxDmaHalfTransfer(void)                    = 0;
 	virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
 
-	void SetupTransmit(void const *buffer, uint16_t length);
-	void SetupReceive(void *buffer, uint16_t length);
-
 	void UsartIsr();
 	void RxDmaIsr();
 	void TxDmaIsr();
 
-	USART_TypeDef *m_usart;
-	DmaHelper      m_rxDma;
-	DmaHelper      m_txDma;
 };
 
 } /* namespace f4ll */

components/f4ll/src/consolehandler.cpp

@@ -17,6 +17,8 @@ ConsoleHandler::ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t
 
 void ConsoleHandler::ReceiverIdle(void) {}
 void ConsoleHandler::TransmissionComplete(void) {}
+void ConsoleHandler::FramingError(void) {}
+void ConsoleHandler::Overrun(void) {}
 void ConsoleHandler::RxDmaTransferComplete(void) {}
 void ConsoleHandler::RxDmaHalfTransfer(void) {}
 void ConsoleHandler::RxDmaError(DmaHelper::DmaErrorType reason) {}
@@ -33,11 +35,11 @@ void ConsoleHandler::TxDmaError(DmaHelper::DmaErrorType reason) {}
 	b += strcpy_ex(b,s); \
 	b += uitodec(b,u);
 
-void ConsoleHandler::PrintStats(uint8_t id, HsUsart &usart)
+void ConsoleHandler::PrintStats(uint8_t id, PacketUsart &usart)
 {
 	char ids[] = " : ";
 	char *buffer = m_buffer;
-	HsUsart::Stats const &stats(usart.GetStats());
+	PacketUsart::Stats const &stats(usart.GetStats());
 
 	ids[0] = id + '0';
 	buffer += strcpy_ex(buffer, ids);

components/f4ll/src/crchandler.cpp

@@ -113,7 +113,7 @@ void CrcHandler::StartNextTask(void)
 	uint8_t index = 0;
 
 	do {
-		SlotBase *slot = m_firstSlot;
+		SlotBase volatile *slot = m_firstSlot;
 		moreTasks = false;
 		while(slot) {
 			if(index < slot->m_taskCount) {

components/f4ll/src/packetusart.cpp

@@ -5,7 +5,7 @@
  *      Author: abody
  */
 #include <string.h>
-#include "f4ll/hsusart.h"
+#include "f4ll/packetusart.h"
 
 namespace f4ll {
 
@@ -15,87 +15,28 @@ template<typename T> static inline T RoundUpTo4(T input)
 }
 
 
-HsUsart::HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
+PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
 : UsartCore(usart, dma, streamRx, streamTx)
 {
 	CrcHandler::Instance().AttachSlot(m_crcSlot);
 }
 
 
-uint8_t* HsUsart::GetTxPacketBuffer(void)
+void PacketUsart::RxProcessed(bool second)
-{
-	return m_txBuffer.packet.payload;
-}
-
-
-USART_TypeDef* HsUsart::GetUsart(void)
-{
-	return m_usart;
-}
-
-
-HsUsart::Stats const & HsUsart::GetStats(void)
-{
-	return m_stats;
-}
-
-
-bool HsUsart::IsTxBusy()
-{
-	return m_txBuffer.busy;
-}
-
-
-bool HsUsart::IsTxFailed()
-{
-	return m_txBuffer.error;
-}
-
-
-bool HsUsart::IsRxBusy(bool second)
-{
-	return m_rxBuffers[second].busy;
-}
-
-
-bool HsUsart::IsRxFailed(bool second)
-{
-	return m_rxBuffers[second].error;
-
-}
-
-void HsUsart::RxProcessed(bool second)
 {
 	m_rxBuffers[second].busy = false;
 	m_rxBuffers[second].error = false;
 }
 
-void HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
+
+void PacketUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
 {
 	m_userCallback = callback;
 	m_userCallbackParam = callbackParam;
 }
 
-void HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
-{
-	uint8_t hash = STARTMARKER;
 
-	packet.header.startByte = STARTMARKER;
+void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
-	packet.header.serial = serialNo;
-	hash ^= serialNo;
-	packet.header.payloadLength = length;
-	hash ^= length;
-	packet.header.hash = hash;
-}
-
-
-bool HsUsart::CheckHeader(PacketHeader &header)
-{
-	return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
-}
-
-
-void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
 {
 	uint16_t payloadLength = RoundUpTo4((uint16_t)length);
 
@@ -117,16 +58,21 @@ void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrc
 }
 
 
-void HsUsart::SetupReceive()
+void PacketUsart::SetupReceive()
 {
 	m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
 	UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
 }
 
 
-void HsUsart::ReceiverIdle(void)
+//////////////////////////////////////
+// UsartCore pure virtual functions //
+//////////////////////////////////////
+
+void PacketUsart::ReceiverIdle(void)
 {
 	uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
+
 	if(rcvdLen >= sizeof(PacketHeader)) {
 		if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
 			if(rcvdLen >= sizeof(PacketHeader) +
@@ -144,7 +90,7 @@ void HsUsart::ReceiverIdle(void)
 }
 
 
-void HsUsart::TransmissionComplete(void)
+void PacketUsart::TransmissionComplete(void)
 {
 	LL_USART_DisableDirectionTx(m_usart);	// enforcing an idle frame
 	LL_USART_EnableDirectionTx(m_usart);
@@ -152,7 +98,13 @@ void HsUsart::TransmissionComplete(void)
 }
 
 
-void HsUsart::RxDmaTransferComplete(void)
+void PacketUsart::FramingError(void) {}
+
+
+void PacketUsart::Overrun(void) {}
+
+
+void PacketUsart::RxDmaTransferComplete(void)
 {
 	if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
 		CrcHandler::Instance().Enqueue(m_crcSlot, 1,
@@ -166,38 +118,61 @@ void HsUsart::RxDmaTransferComplete(void)
 	SwitchRxBuffers();
 }
 
-void HsUsart::RxDmaHalfTransfer(void)
+void PacketUsart::RxDmaHalfTransfer(void)
 {
 }
 
 
-void HsUsart::RxDmaError(DmaHelper::DmaErrorType reason)
+void PacketUsart::RxDmaError(DmaHelper::DmaErrorType reason)
 {
 	m_rxBuffers[m_rxBufferSelector].error = 1;
 	++m_stats.rxDmaError;
 	SwitchRxBuffers();
 }
 
-void HsUsart::TxDmaTransferComplete(void)
+void PacketUsart::TxDmaTransferComplete(void)
 {
 	LL_USART_EnableIT_TC(m_usart);
 	LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
 }
 
 
-void HsUsart::TxDmaHalfTransfer(void)
+void PacketUsart::TxDmaHalfTransfer(void)
 {
 }
 
 
-void HsUsart::TxDmaError(DmaHelper::DmaErrorType reason)
+void PacketUsart::TxDmaError(DmaHelper::DmaErrorType reason)
 {
 	m_txBuffer.error = 1;
 	++m_stats.txDmaError;
 }
 
 
-void HsUsart::SwitchRxBuffers(void)
+///////////////////////
+// Private functions //
+///////////////////////
+
+void PacketUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
+{
+	uint8_t hash = STARTMARKER;
+
+	packet.header.startByte = STARTMARKER;
+	packet.header.serial = serialNo;
+	hash ^= serialNo;
+	packet.header.payloadLength = length;
+	hash ^= length;
+	packet.header.hash = hash;
+}
+
+
+bool PacketUsart::CheckHeader(PacketHeader &header)
+{
+	return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
+}
+
+
+void PacketUsart::SwitchRxBuffers(void)
 {
 	++m_stats.rcvd;
 	m_rxBufferSelector = !m_rxBufferSelector;
@@ -207,8 +182,11 @@ void HsUsart::SwitchRxBuffers(void)
 	SetupReceive();
 }
 
+///////////////////////////
+// CrcHandler::ICallback //
+///////////////////////////
 
-void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
+void PacketUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
 {
 	Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
 
@@ -223,7 +201,7 @@ void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
 }
 
 
-void HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
+void PacketUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
 {
 	Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
 	buf.busy = buf.error = true;

components/f4ll/src/usartcore.cpp

@@ -19,16 +19,29 @@ UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx,
 	LL_DMA_EnableIT_TC(dma, streamTx);
 	LL_DMA_EnableIT_TE(dma, streamTx);
 	LL_USART_EnableIT_IDLE(usart);
+	LL_USART_EnableIT_ERROR(usart);
 }
 
+
 void UsartCore::UsartIsr()
 {
-	if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) {	//	receiver idle
+	if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
-		LL_USART_ClearFlag_IDLE(m_usart);
-		ReceiverIdle();
-	} else if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) {	// transmission complete
 		LL_USART_DisableIT_TC(m_usart);
 		TransmissionComplete();
+	} else if(LL_USART_IsEnabledIT_ERROR(m_usart)) {
+		uint32_t status = m_usart->SR;
+		volatile uint32_t tmpreg = m_usart->DR; // clearing some of the error/status bits in the HW
+		(void) tmpreg;
+
+		if(status & USART_SR_IDLE) {
+			ReceiverIdle();
+		}
+		if(status & USART_SR_FE) {
+			FramingError();
+		}
+		if(status & USART_SR_ORE) {
+			Overrun();
+		}
 	}
 }