Embedded package update
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54 changed files with 3660 additions and 1918 deletions
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@ -232,7 +232,6 @@
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*/
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static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
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LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
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static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
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static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
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static ErrorStatus UTILS_PLL_IsBusy(void);
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/**
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@ -328,6 +327,144 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
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SystemCoreClock = HCLKFrequency;
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}
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/**
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* @brief Update number of Flash wait states in line with new frequency and current
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voltage range.
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* @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
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* @param HCLK_Frequency HCLK frequency
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: Latency has been modified
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* - ERROR: Latency cannot be modified
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*/
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ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
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{
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uint32_t timeout;
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uint32_t getlatency;
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uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
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ErrorStatus status = SUCCESS;
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/* Frequency cannot be equal to 0 */
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if(HCLK_Frequency == 0U)
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{
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status = ERROR;
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}
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else
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{
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if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
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{
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#if defined (UTILS_SCALE1_LATENCY5_FREQ)
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_5;
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}
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#endif /*UTILS_SCALE1_LATENCY5_FREQ */
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#if defined (UTILS_SCALE1_LATENCY4_FREQ)
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_4;
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}
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#endif /* UTILS_SCALE1_LATENCY4_FREQ */
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#if defined (UTILS_SCALE1_LATENCY3_FREQ)
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_3;
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}
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#endif /* UTILS_SCALE1_LATENCY3_FREQ */
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#if defined (UTILS_SCALE1_LATENCY2_FREQ)
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_2;
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}
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else
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{
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_1;
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}
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}
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#endif /* UTILS_SCALE1_LATENCY2_FREQ */
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}
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if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
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{
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#if defined (UTILS_SCALE2_LATENCY5_FREQ)
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_5;
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}
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#endif /*UTILS_SCALE1_LATENCY5_FREQ */
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#if defined (UTILS_SCALE2_LATENCY4_FREQ)
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_4;
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}
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#endif /*UTILS_SCALE1_LATENCY4_FREQ */
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#if defined (UTILS_SCALE2_LATENCY3_FREQ)
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_3;
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}
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#endif /*UTILS_SCALE1_LATENCY3_FREQ */
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_2;
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}
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else
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{
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_1;
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}
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}
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}
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#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
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if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
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{
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#if defined (UTILS_SCALE3_LATENCY3_FREQ)
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if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_3;
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}
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#endif /*UTILS_SCALE1_LATENCY3_FREQ */
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#if defined (UTILS_SCALE3_LATENCY2_FREQ)
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if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_2;
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}
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else
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{
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if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_1;
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}
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}
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}
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#endif /*UTILS_SCALE1_LATENCY2_FREQ */
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#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
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LL_FLASH_SetLatency(latency);
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/* Check that the new number of wait states is taken into account to access the Flash
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memory by reading the FLASH_ACR register */
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timeout = 2;
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do
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{
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/* Wait for Flash latency to be updated */
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getlatency = LL_FLASH_GetLatency();
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timeout--;
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} while ((getlatency != latency) && (timeout > 0));
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if(getlatency != latency)
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{
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status = ERROR;
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}
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else
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{
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status = SUCCESS;
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}
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}
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return status;
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}
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/**
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* @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
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* @note The application need to ensure that PLL is disabled.
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@ -465,131 +602,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
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/** @addtogroup UTILS_LL_Private_Functions
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* @{
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*/
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/**
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* @brief Update number of Flash wait states in line with new frequency and current
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voltage range.
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* @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
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* @param HCLK_Frequency HCLK frequency
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: Latency has been modified
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* - ERROR: Latency cannot be modified
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*/
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static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
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{
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ErrorStatus status = SUCCESS;
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uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
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/* Frequency cannot be equal to 0 */
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if(HCLK_Frequency == 0U)
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{
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status = ERROR;
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}
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else
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{
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if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
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{
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#if defined (UTILS_SCALE1_LATENCY5_FREQ)
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_5;
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}
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#endif /*UTILS_SCALE1_LATENCY5_FREQ */
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#if defined (UTILS_SCALE1_LATENCY4_FREQ)
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_4;
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}
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#endif /* UTILS_SCALE1_LATENCY4_FREQ */
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#if defined (UTILS_SCALE1_LATENCY3_FREQ)
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_3;
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}
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#endif /* UTILS_SCALE1_LATENCY3_FREQ */
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#if defined (UTILS_SCALE1_LATENCY2_FREQ)
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_2;
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}
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else
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{
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if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_1;
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}
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}
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#endif /* UTILS_SCALE1_LATENCY2_FREQ */
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}
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if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
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{
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#if defined (UTILS_SCALE2_LATENCY5_FREQ)
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_5;
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}
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#endif /*UTILS_SCALE1_LATENCY5_FREQ */
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#if defined (UTILS_SCALE2_LATENCY4_FREQ)
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_4;
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}
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#endif /*UTILS_SCALE1_LATENCY4_FREQ */
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#if defined (UTILS_SCALE2_LATENCY3_FREQ)
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_3;
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}
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#endif /*UTILS_SCALE1_LATENCY3_FREQ */
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_2;
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}
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else
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{
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if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_1;
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}
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}
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}
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#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
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if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
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{
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#if defined (UTILS_SCALE3_LATENCY3_FREQ)
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if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_3;
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}
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#endif /*UTILS_SCALE1_LATENCY3_FREQ */
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#if defined (UTILS_SCALE3_LATENCY2_FREQ)
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if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_2;
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}
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else
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{
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if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
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{
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latency = LL_FLASH_LATENCY_1;
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}
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}
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}
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#endif /*UTILS_SCALE1_LATENCY2_FREQ */
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#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
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LL_FLASH_SetLatency(latency);
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/* Check that the new number of wait states is taken into account to access the Flash
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memory by reading the FLASH_ACR register */
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if(LL_FLASH_GetLatency() != latency)
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{
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status = ERROR;
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}
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}
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return status;
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}
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/**
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* @brief Function to check that PLL can be modified
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* @param PLL_InputFrequency PLL input frequency (in Hz)
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@ -683,7 +695,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_
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if(SystemCoreClock < hclk_frequency)
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{
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/* Set FLASH latency to highest latency */
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status = UTILS_SetFlashLatency(hclk_frequency);
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status = LL_SetFlashLatency(hclk_frequency);
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}
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/* Update system clock configuration */
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@ -713,7 +725,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_
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if(SystemCoreClock > hclk_frequency)
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{
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/* Set FLASH latency to lowest latency */
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status = UTILS_SetFlashLatency(hclk_frequency);
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status = LL_SetFlashLatency(hclk_frequency);
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}
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/* Update SystemCoreClock variable */
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