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This commit is contained in:
Attila Body 2021-10-29 21:40:31 +02:00
parent 46a5748e75
commit 411b895bf7
54 changed files with 3660 additions and 1918 deletions
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16
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
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@ -100,11 +100,19 @@ void HAL_PWR_DeInit(void)
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @note The following sequence is required to bypass the delay between
* DBP bit programming and the effective enabling of the backup domain.
* Please check the Errata Sheet for more details under "Possible delay
* in backup domain protection disabling/enabling after programming the
* DBP bit" section.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
__IO uint32_t dummyread;
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
dummyread = PWR->CR;
UNUSED(dummyread);
}
/**
@ -112,11 +120,19 @@ void HAL_PWR_EnableBkUpAccess(void)
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @note The following sequence is required to bypass the delay between
* DBP bit programming and the effective disabling of the backup domain.
* Please check the Errata Sheet for more details under "Possible delay
* in backup domain protection disabling/enabling after programming the
* DBP bit" section.
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
{
__IO uint32_t dummyread;
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
dummyread = PWR->CR;
UNUSED(dummyread);
}
/**