Embedded package update
This commit is contained in:
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46a5748e75
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411b895bf7
54 changed files with 3660 additions and 1918 deletions
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@ -50,11 +50,11 @@
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* @{
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*/
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/**
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* @brief STM32F4xx HAL Driver version number V1.7.7
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* @brief STM32F4xx HAL Driver version number V1.7.13
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*/
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#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
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#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
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#define __STM32F4xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
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#define __STM32F4xx_HAL_VERSION_SUB2 (0x0DU) /*!< [15:8] sub2 version */
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#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
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|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
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@ -199,12 +199,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
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assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
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assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
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}
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/* Allocate lock resource */
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__HAL_UNLOCK(hdma);
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Allocate lock resource */
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__HAL_UNLOCK(hdma);
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/* Disable the peripheral */
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__HAL_DMA_DISABLE(hdma);
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@ -550,12 +550,12 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
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/* Update error code */
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hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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/* Change the DMA state */
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hdma->State = HAL_DMA_STATE_TIMEOUT;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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return HAL_TIMEOUT;
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}
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}
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@ -563,11 +563,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
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/* Clear all interrupt flags at correct offset within the register */
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regs->IFCR = 0x3FU << hdma->StreamIndex;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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/* Change the DMA state*/
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hdma->State = HAL_DMA_STATE_READY;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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}
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return HAL_OK;
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}
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@ -657,13 +657,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
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{
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/* Update error code */
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hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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/* Change the DMA state */
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hdma->State = HAL_DMA_STATE_READY;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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return HAL_TIMEOUT;
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}
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}
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@ -708,12 +708,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
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/* Clear the half transfer and transfer complete flags */
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regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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/* Change the DMA state */
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hdma->State= HAL_DMA_STATE_READY;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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return HAL_ERROR;
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}
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}
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@ -724,10 +724,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
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/* Clear the half transfer and transfer complete flags */
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regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
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hdma->State = HAL_DMA_STATE_READY;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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hdma->State = HAL_DMA_STATE_READY;
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}
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else
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{
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@ -863,12 +863,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
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/* Clear all interrupt flags at correct offset within the register */
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regs->IFCR = 0x3FU << hdma->StreamIndex;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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/* Change the DMA state */
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hdma->State = HAL_DMA_STATE_READY;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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if(hdma->XferAbortCallback != NULL)
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{
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hdma->XferAbortCallback(hdma);
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@ -905,11 +905,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
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/* Disable the transfer complete interrupt */
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hdma->Instance->CR &= ~(DMA_IT_TC);
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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/* Change the DMA state */
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hdma->State = HAL_DMA_STATE_READY;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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}
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if(hdma->XferCpltCallback != NULL)
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@ -940,11 +940,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
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}
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while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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/* Change the DMA state */
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hdma->State = HAL_DMA_STATE_READY;
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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}
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if(hdma->XferErrorCallback != NULL)
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@ -276,6 +276,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
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pExtiConfig->Mode |= EXTI_MODE_EVENT;
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}
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/* Get default Trigger and GPIOSel configuration */
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pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
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pExtiConfig->GPIOSel = 0x00u;
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/* 2] Get trigger for configurable lines : rising */
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if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
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{
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@ -284,10 +288,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
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{
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pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
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}
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else
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{
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pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
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}
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/* Get falling configuration */
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/* Check if configuration of selected line is enable */
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@ -304,16 +304,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
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regval = SYSCFG->EXTICR[linepos >> 2u];
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pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
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}
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else
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{
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pExtiConfig->GPIOSel = 0x00u;
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}
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}
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else
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{
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/* No Trigger selected */
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pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
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pExtiConfig->GPIOSel = 0x00u;
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}
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return HAL_OK;
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File diff suppressed because it is too large
Load diff
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@ -123,13 +123,6 @@
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/** @addtogroup GPIO_Private_Constants GPIO Private Constants
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* @{
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*/
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#define GPIO_MODE 0x00000003U
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#define EXTI_MODE 0x10000000U
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#define GPIO_MODE_IT 0x00010000U
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#define GPIO_MODE_EVT 0x00020000U
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#define RISING_EDGE 0x00100000U
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#define FALLING_EDGE 0x00200000U
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#define GPIO_OUTPUT_TYPE 0x00000010U
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#define GPIO_NUMBER 16U
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/**
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@ -179,7 +172,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
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assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
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assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
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assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
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/* Configure the port pins */
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for(position = 0U; position < GPIO_NUMBER; position++)
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@ -193,8 +185,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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{
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/*--------------------- GPIO Mode Configuration ------------------------*/
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/* In case of Output or Alternate function mode selection */
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if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
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(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
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if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
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(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
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{
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/* Check the Speed parameter */
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assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
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@ -207,18 +199,24 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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/* Configure the IO Output Type */
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temp = GPIOx->OTYPER;
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temp &= ~(GPIO_OTYPER_OT_0 << position) ;
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temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
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temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
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GPIOx->OTYPER = temp;
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}
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/* Activate the Pull-up or Pull down resistor for the current IO */
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temp = GPIOx->PUPDR;
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temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
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temp |= ((GPIO_Init->Pull) << (position * 2U));
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GPIOx->PUPDR = temp;
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if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
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{
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/* Check the parameters */
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assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
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/* Activate the Pull-up or Pull down resistor for the current IO */
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temp = GPIOx->PUPDR;
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temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
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temp |= ((GPIO_Init->Pull) << (position * 2U));
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GPIOx->PUPDR = temp;
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}
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/* In case of Alternate function mode selection */
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if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
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if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
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{
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/* Check the Alternate function parameter */
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assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
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@ -237,7 +235,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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/*--------------------- EXTI Mode Configuration ------------------------*/
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/* Configure the External Interrupt or event for the current IO */
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if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
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if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
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{
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/* Enable SYSCFG Clock */
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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@ -250,7 +248,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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/* Clear EXTI line configuration */
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temp = EXTI->IMR;
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temp &= ~((uint32_t)iocurrent);
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if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
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if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
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{
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temp |= iocurrent;
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}
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@ -258,7 +256,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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temp = EXTI->EMR;
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temp &= ~((uint32_t)iocurrent);
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if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
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if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
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{
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temp |= iocurrent;
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}
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@ -267,7 +265,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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/* Clear Rising Falling edge configuration */
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temp = EXTI->RTSR;
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temp &= ~((uint32_t)iocurrent);
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if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
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if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
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{
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temp |= iocurrent;
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}
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@ -275,7 +273,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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temp = EXTI->FTSR;
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temp &= ~((uint32_t)iocurrent);
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if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
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if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
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{
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temp |= iocurrent;
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}
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@ -434,17 +432,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
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*/
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void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
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{
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uint32_t odr;
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/* Check the parameters */
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assert_param(IS_GPIO_PIN(GPIO_Pin));
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if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
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{
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GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
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}
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else
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{
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GPIOx->BSRR = GPIO_Pin;
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}
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/* get current Ouput Data Register value */
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odr = GPIOx->ODR;
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/* Set selected pins that were at low level, and reset ones that were high */
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GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
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}
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/**
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@ -100,11 +100,19 @@ void HAL_PWR_DeInit(void)
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* backup data registers and backup SRAM).
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* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @note The following sequence is required to bypass the delay between
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* DBP bit programming and the effective enabling of the backup domain.
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* Please check the Errata Sheet for more details under "Possible delay
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* in backup domain protection disabling/enabling after programming the
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* DBP bit" section.
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* @retval None
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*/
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void HAL_PWR_EnableBkUpAccess(void)
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{
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__IO uint32_t dummyread;
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
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dummyread = PWR->CR;
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UNUSED(dummyread);
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}
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/**
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@ -112,11 +120,19 @@ void HAL_PWR_EnableBkUpAccess(void)
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* backup data registers and backup SRAM).
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* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @note The following sequence is required to bypass the delay between
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* DBP bit programming and the effective disabling of the backup domain.
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* Please check the Errata Sheet for more details under "Possible delay
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* in backup domain protection disabling/enabling after programming the
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* DBP bit" section.
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* @retval None
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*/
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void HAL_PWR_DisableBkUpAccess(void)
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{
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__IO uint32_t dummyread;
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
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dummyread = PWR->CR;
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UNUSED(dummyread);
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}
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/**
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@ -539,12 +539,23 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
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else
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{
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/* Do not return HAL_ERROR if request repeats the current configuration */
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pll_config = RCC->CFGR;
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if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
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pll_config = RCC->PLLCFGR;
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#if defined (RCC_PLLCFGR_PLLR)
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if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
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#else
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if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
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(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
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#endif
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{
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return HAL_ERROR;
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}
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@ -3334,7 +3334,13 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
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*/
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HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
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{
|
||||
uint32_t tickstart = 0U;
|
||||
uint32_t tickstart, pll_config;
|
||||
|
||||
/* Check Null pointer */
|
||||
if(RCC_OscInitStruct == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
||||
|
@ -3612,13 +3618,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
}
|
||||
|
||||
/* Configure the main PLL clock source, multiplication and division factors. */
|
||||
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
||||
RCC_OscInitStruct->PLL.PLLM,
|
||||
RCC_OscInitStruct->PLL.PLLN,
|
||||
RCC_OscInitStruct->PLL.PLLP,
|
||||
RCC_OscInitStruct->PLL.PLLQ,
|
||||
RCC_OscInitStruct->PLL.PLLR);
|
||||
|
||||
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
||||
RCC_OscInitStruct->PLL.PLLM | \
|
||||
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
||||
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
||||
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
|
||||
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
|
||||
/* Enable the main PLL. */
|
||||
__HAL_RCC_PLL_ENABLE();
|
||||
|
||||
|
@ -3654,7 +3659,35 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
/* Check if there is a request to disable the PLL used as System clock source */
|
||||
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do not return HAL_ERROR if request repeats the current configuration */
|
||||
pll_config = RCC->PLLCFGR;
|
||||
#if defined (RCC_PLLCFGR_PLLR)
|
||||
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
||||
#else
|
||||
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
||||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
||||
#endif
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
|
|
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
@ -26,7 +26,7 @@
|
|||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
#endif/* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32F4xx_LL_Driver
|
||||
* @{
|
||||
|
|
|
@ -63,45 +63,42 @@
|
|||
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
|
||||
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
|
||||
|
||||
/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
|
||||
#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
|
||||
|
||||
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
|
||||
|
||||
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|
||||
|| ((__VALUE__) == LL_USART_PARITY_ODD))
|
||||
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|
||||
|| ((__VALUE__) == LL_USART_PARITY_ODD))
|
||||
|
||||
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|
||||
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
|
||||
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
|
||||
|
||||
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|
||||
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
|
||||
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
|
||||
|
||||
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|
||||
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
|
||||
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
|
||||
|
||||
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|
||||
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
|
||||
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
|
||||
|
||||
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|
||||
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
|
||||
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
|
||||
|
||||
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|
||||
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
|
||||
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
|
||||
|
||||
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_2))
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_2))
|
||||
|
||||
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -375,9 +372,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
|
|||
|
||||
/* Check BRR is greater than or equal to 16d */
|
||||
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
|
||||
|
||||
/* Check BRR is greater than or equal to 16d */
|
||||
assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
|
||||
}
|
||||
}
|
||||
/* Endif (=> USART not in Disabled state => return ERROR) */
|
||||
|
|
|
@ -232,7 +232,6 @@
|
|||
*/
|
||||
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
|
||||
static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
|
||||
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
static ErrorStatus UTILS_PLL_IsBusy(void);
|
||||
/**
|
||||
|
@ -328,6 +327,144 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
|
|||
SystemCoreClock = HCLKFrequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update number of Flash wait states in line with new frequency and current
|
||||
voltage range.
|
||||
* @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
|
||||
* @param HCLK_Frequency HCLK frequency
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Latency has been modified
|
||||
* - ERROR: Latency cannot be modified
|
||||
*/
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
|
||||
{
|
||||
uint32_t timeout;
|
||||
uint32_t getlatency;
|
||||
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
|
||||
/* Frequency cannot be equal to 0 */
|
||||
if(HCLK_Frequency == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
|
||||
{
|
||||
#if defined (UTILS_SCALE1_LATENCY5_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_5;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY5_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY4_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_4;
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY4_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY3_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY2_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY2_FREQ */
|
||||
}
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
|
||||
{
|
||||
#if defined (UTILS_SCALE2_LATENCY5_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_5;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY5_FREQ */
|
||||
#if defined (UTILS_SCALE2_LATENCY4_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_4;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY4_FREQ */
|
||||
#if defined (UTILS_SCALE2_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY3_FREQ */
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
|
||||
{
|
||||
#if defined (UTILS_SCALE3_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY3_FREQ */
|
||||
#if defined (UTILS_SCALE3_LATENCY2_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY2_FREQ */
|
||||
#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
|
||||
|
||||
LL_FLASH_SetLatency(latency);
|
||||
/* Check that the new number of wait states is taken into account to access the Flash
|
||||
memory by reading the FLASH_ACR register */
|
||||
timeout = 2;
|
||||
do
|
||||
{
|
||||
/* Wait for Flash latency to be updated */
|
||||
getlatency = LL_FLASH_GetLatency();
|
||||
timeout--;
|
||||
} while ((getlatency != latency) && (timeout > 0));
|
||||
|
||||
if(getlatency != latency)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SUCCESS;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
|
@ -465,131 +602,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
|
|||
/** @addtogroup UTILS_LL_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Update number of Flash wait states in line with new frequency and current
|
||||
voltage range.
|
||||
* @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
|
||||
* @param HCLK_Frequency HCLK frequency
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Latency has been modified
|
||||
* - ERROR: Latency cannot be modified
|
||||
*/
|
||||
static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
|
||||
|
||||
/* Frequency cannot be equal to 0 */
|
||||
if(HCLK_Frequency == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
|
||||
{
|
||||
#if defined (UTILS_SCALE1_LATENCY5_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_5;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY5_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY4_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_4;
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY4_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY3_FREQ */
|
||||
#if defined (UTILS_SCALE1_LATENCY2_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
#endif /* UTILS_SCALE1_LATENCY2_FREQ */
|
||||
}
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
|
||||
{
|
||||
#if defined (UTILS_SCALE2_LATENCY5_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_5;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY5_FREQ */
|
||||
#if defined (UTILS_SCALE2_LATENCY4_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_4;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY4_FREQ */
|
||||
#if defined (UTILS_SCALE2_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY3_FREQ */
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
|
||||
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
|
||||
{
|
||||
#if defined (UTILS_SCALE3_LATENCY3_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_3;
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY3_FREQ */
|
||||
#if defined (UTILS_SCALE3_LATENCY2_FREQ)
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
|
||||
{
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /*UTILS_SCALE1_LATENCY2_FREQ */
|
||||
#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
|
||||
|
||||
LL_FLASH_SetLatency(latency);
|
||||
|
||||
/* Check that the new number of wait states is taken into account to access the Flash
|
||||
memory by reading the FLASH_ACR register */
|
||||
if(LL_FLASH_GetLatency() != latency)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to check that PLL can be modified
|
||||
* @param PLL_InputFrequency PLL input frequency (in Hz)
|
||||
|
@ -683,7 +695,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_
|
|||
if(SystemCoreClock < hclk_frequency)
|
||||
{
|
||||
/* Set FLASH latency to highest latency */
|
||||
status = UTILS_SetFlashLatency(hclk_frequency);
|
||||
status = LL_SetFlashLatency(hclk_frequency);
|
||||
}
|
||||
|
||||
/* Update system clock configuration */
|
||||
|
@ -713,7 +725,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_
|
|||
if(SystemCoreClock > hclk_frequency)
|
||||
{
|
||||
/* Set FLASH latency to lowest latency */
|
||||
status = UTILS_SetFlashLatency(hclk_frequency);
|
||||
status = LL_SetFlashLatency(hclk_frequency);
|
||||
}
|
||||
|
||||
/* Update SystemCoreClock variable */
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue