diff --git a/.cproject b/.cproject
index 0a729c4..6db3336 100644
--- a/.cproject
+++ b/.cproject
@@ -23,7 +23,7 @@
-
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@@ -34,17 +34,25 @@
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diff --git a/.mxproject b/.mxproject
index f3e47c8..5970180 100644
--- a/.mxproject
+++ b/.mxproject
@@ -1,14 +1,14 @@
-[PreviousGenFiles]
-HeaderPath=/mnt/userdata/compi/work/private/stm32/NeoPixelF103MVP/Inc
-HeaderFiles=gpio.h;dma.h;spi.h;stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h;
-SourcePath=/mnt/userdata/compi/work/private/stm32/NeoPixelF103MVP/Src
-SourceFiles=gpio.c;dma.c;spi.c;stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c;
-
[PreviousLibFiles]
-LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
[PreviousUsedCubeIDEFiles]
-SourceFiles=Src/main.c;Src/gpio.c;Src/dma.c;Src/spi.c;Src/stm32f1xx_it.c;Src/stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Src/system_stm32f1xx.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;;
-HeaderPath=Drivers/STM32F1xx_HAL_Driver/Inc;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F1xx/Include;Drivers/CMSIS/Include;Inc;
-CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;USE_HAL_DRIVER;
+SourceFiles=Src/main.c;Src/gpio.c;Src/dma.c;Src/spi.c;Src/stm32f1xx_it.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c;Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c;Src/system_stm32f1xx.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;;
+HeaderPath=Drivers/STM32F1xx_HAL_Driver/Inc;Drivers/CMSIS/Device/ST/STM32F1xx/Include;Drivers/CMSIS/Include;Inc;
+CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;HSI_VALUE:8000000;LSI_VALUE:40000;VDD_VALUE:3300;PREFETCH_ENABLE:1;STM32F103xB;USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;HSI_VALUE:8000000;LSI_VALUE:40000;VDD_VALUE:3300;PREFETCH_ENABLE:1;
+
+[PreviousGenFiles]
+HeaderPath=/mnt/userdata/compi/work/private/stm32/NeoPixelF103MVP/Inc
+HeaderFiles=gpio.h;dma.h;spi.h;stm32f1xx_it.h;stm32_assert.h;main.h;
+SourcePath=/mnt/userdata/compi/work/private/stm32/NeoPixelF103MVP/Src
+SourceFiles=gpio.c;dma.c;spi.c;stm32f1xx_it.c;main.c;
diff --git a/App/App.cpp b/App/App.cpp
index 0d76864..4a586c2 100644
--- a/App/App.cpp
+++ b/App/App.cpp
@@ -5,8 +5,9 @@
* Author: abody
*/
+#include
+
#include "main.h"
-#include "stm32f1xx_hal.h"
#include "dma.h"
#include "spi.h"
#include "gpio.h"
@@ -18,8 +19,10 @@
#include "LedBuffers.h"
#include "Sparkle.h"
-Sparkle g_s[NUMSPARKLES];
-volatile uint8_t g_done = 0;
+Sparkle g_sparkles[NUMSPARKLES];
+volatile uint8_t g_spi_idle = 0;
+
+volatile uint32_t g_tick = 0;
void convert(uint8_t *src, uint8_t *dst, uint16_t size)
{
@@ -48,7 +51,7 @@ uint16_t ChoosePixel()
do {
chosen = rr(NUMPIXELS);
for(spi=0; spi(g_s[spi]) && static_cast(g_s[spi]) == &g_pixels[chosen])
+ if(static_cast(g_sparkles[spi]) && static_cast(g_sparkles[spi]) == &g_pixels[chosen])
break;
}
} while(spi < NUMSPARKLES);
@@ -63,11 +66,25 @@ void StartSparkle( Sparkle &s )
s.Start(g_pixels+ChoosePixel(), Pixel(255,255,255), Pixel(rr(8)+3,rr(8)+3,rr(8)+3));
}
-extern "C" void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+extern "C" void HandleSystick()
{
- if(hspi == &hspi1) {
- g_done = true;
- }
+ ++ g_tick;
+}
+
+extern "C" uint32_t GetTick()
+{
+ return g_tick;
+}
+
+extern "C" void HandleSpiDmaIrq()
+{
+ if(LL_DMA_IsActiveFlag_TC3(DMA1)) {
+ LL_DMA_ClearFlag_TC3(DMA1);
+ g_spi_idle = true;
+ LL_SPI_DisableDMAReq_TX(SPI1);
+ LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_3);
+ } else if(LL_DMA_IsActiveFlag_TE3(DMA1))
+ LL_DMA_ClearFlag_TE3(DMA1);
}
extern "C" void App()
@@ -77,28 +94,38 @@ extern "C" void App()
for(uint16_t px = 0; px < NUMPIXELS; ++px)
g_pixels[px] = Pixel( DEFAULT_COLOR );
- uint32_t lastTick = HAL_GetTick();
+ uint32_t lastTick = GetTick();
+
+ LL_SYSTICK_EnableIT();
+ LL_SPI_Enable(SPI1);
while(1)
{
- while(HAL_GetTick() - lastTick < FRAMETIME );
+ while(GetTick() - lastTick < FRAMETIME );
lastTick += FRAMETIME;
- HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
+ LL_GPIO_TogglePin(GPIOC, LL_GPIO_PIN_13);
for(int16_t spi = 0; spi < NUMSPARKLES; ++spi) {
- if(static_cast(g_s[spi]))
- g_s[spi].Step();
+ if(static_cast(g_sparkles[spi]))
+ g_sparkles[spi].Step();
else
- StartSparkle(g_s[spi]);
+ StartSparkle(g_sparkles[spi]);
}
- HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
+ LL_GPIO_TogglePin(GPIOC, LL_GPIO_PIN_13);
convert((uint8_t*)g_pixels, g_spibuffer, sizeof(g_pixels));
- HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
+ LL_GPIO_TogglePin(GPIOC, LL_GPIO_PIN_13);
- g_done = false;
- HAL_SPI_Transmit_DMA(&hspi1, g_spibuffer, sizeof(g_spibuffer));
- while(!g_done);
- HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
+ g_spi_idle = false;
+// HAL_SPI_Transmit_DMA(&hspi1, g_ledBits, sizeof(g_ledBits));
+ LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_3, (uint32_t)g_spibuffer, LL_SPI_DMA_GetRegAddr(SPI1), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+ LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_3, sizeof(g_spibuffer));
+ LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_3);
+ LL_SPI_EnableDMAReq_TX(SPI1);
+ LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_3);
+ LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_3);
+
+ while(!g_spi_idle);
+ LL_GPIO_TogglePin(GPIOC, LL_GPIO_PIN_13);
}
}
diff --git a/App/App.h b/App/App.h
new file mode 100644
index 0000000..caf5a10
--- /dev/null
+++ b/App/App.h
@@ -0,0 +1,15 @@
+#ifndef __APP_H_INCLUDED__
+#define __APP_H_INCLUDED__
+
+#ifdef __cplusplus
+extern"C" {
+#endif
+
+void HandleSystick();
+void HandleSpiDmaIrq();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APP_H_INCLUDED__ */
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index 43cafcb..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,3783 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_hal_legacy.h
- * @author MCD Application Team
- * @brief This file contains aliases definition for the STM32Cube HAL constants
- * macros and functions maintained for legacy purpose.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32_HAL_LEGACY
-#define STM32_HAL_LEGACY
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-/**
- * @}
- */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP ADC_REGULAR_GROUP
-#define INJECTED_GROUP ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT ADC_AWD_EVENT
-#define AWD1_EVENT ADC_AWD1_EVENT
-#define AWD2_EVENT ADC_AWD2_EVENT
-#define AWD3_EVENT ADC_AWD3_EVENT
-#define OVR_EVENT ADC_OVR_EVENT
-#define JQOVF_EVENT ADC_JQOVF_EVENT
-#define ALL_CHANNELS ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
-
-#if defined(STM32H7)
-#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
-#endif /* STM32H7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
-#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
-#endif
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
-/* to the second dedicated IO (only for COMP2). */
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
-/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
- * @{
- */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define DAC1_CHANNEL_1 DAC_CHANNEL_1
-#define DAC1_CHANNEL_2 DAC_CHANNEL_2
-#define DAC2_CHANNEL_1 DAC_CHANNEL_1
-#define DAC_WAVE_NONE 0x00000000U
-#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-
-#if defined(STM32G4) || defined(STM32H7)
-#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
-#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
-#endif
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
-#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
-#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-#if defined(STM32L4)
-
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
-#endif
-
-#endif /* STM32L4 */
-
-#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
-#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
-#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
-
-#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
-#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
-#endif
-
-#if defined(STM32H7)
-
-#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
-#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
-#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
-
-#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
-#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
-
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW OB_IWDG_SW
-#define OB_WDG_HW OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
-#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
-#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
-#else
-#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
-#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
-#endif
-#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32H7)
-#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
-#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
-#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
-#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
-#if defined(STM32G4)
-
-#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
-#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
-#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
-#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
-#endif /* STM32G4 */
-/**
- * @}
- */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
- * @{
- */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
-#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
-#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
- * @}
- */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
-/**
- * @}
- */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
- * @{
- */
-#define GET_GPIO_SOURCE GPIO_GET_INDEX
-#define GET_GPIO_INDEX GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32H7)
-#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
-#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
-#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
-#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
-#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
-#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-
-#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
- defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
-#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
-#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
-#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
-#endif /* STM32H7 */
-
-#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
-
-#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
-
-#if defined(STM32G4)
-#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
-#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
-#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
-#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
-#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
-#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
-#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
-#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
-#endif /* STM32G4 */
-
-#if defined(STM32H7)
-#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-
-#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-#endif /* STM32H7 */
-
-#if defined(STM32F3)
-/** @brief Constants defining available sources associated to external events.
- */
-#define HRTIM_EVENTSRC_1 (0x00000000U)
-#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
-#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
-#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-
-/** @brief Constants defining the events that can be selected to configure the
- * set/reset crossbar of a timer output
- */
-#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
-#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
-#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
-#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
-#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
-#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
-#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
-#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
-#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
-
-#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
-#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
-#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
-#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
-#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
-#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
-#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
-#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
-#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
-
-/** @brief Constants defining the event filtering applied to external events
- * by a timer
- */
-#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-
-/** @brief Constants defining the DLL calibration periods (in micro seconds)
- */
-#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
-#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
-#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
-#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
-
-#endif /* STM32F3 */
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define KR_KEY_RELOAD IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE IWDG_KEY_ENABLE
-#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
- * @}
- */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
-/**
- * @}
- */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
- * @{
- */
-#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE NOR_WRITE
-#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
-/**
- * @}
- */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
-#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
-#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
-#endif
-
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-
-#if defined(STM32H7)
- #define I2S_IT_TXE I2S_IT_TXP
- #define I2S_IT_RXNE I2S_IT_RXP
-
- #define I2S_FLAG_TXE I2S_FLAG_TXP
- #define I2S_FLAG_RXNE I2S_FLAG_RXP
-#endif
-
-#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA ATA_DATA
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD ATA_CARD_HEAD
-#define CF_STATUS_CMD ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FORMAT_BIN RTC_FORMAT_BIN
-#define FORMAT_BCD RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-
-#if defined(STM32H7)
-#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
-#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
-
-#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
-#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
-#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
-
-#if defined(STM32H7)
-
- #define SPI_FLAG_TXE SPI_FLAG_TXP
- #define SPI_FLAG_RXNE SPI_FLAG_RXP
-
- #define SPI_IT_TXE SPI_IT_TXP
- #define SPI_IT_RXNE SPI_IT_RXP
-
- #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
- #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
- #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
- #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
-
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1 TIM_DMABASE_CR1
-#define TIM_DMABase_CR2 TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER TIM_DMABASE_DIER
-#define TIM_DMABase_SR TIM_DMABASE_SR
-#define TIM_DMABase_EGR TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER TIM_DMABASE_CCER
-#define TIM_DMABase_CNT TIM_DMABASE_CNT
-#define TIM_DMABase_PSC TIM_DMABASE_PSC
-#define TIM_DMABase_ARR TIM_DMABASE_ARR
-#define TIM_DMABase_RCR TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1 TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2 TIM_DMABASE_OR2
-#define TIM_DMABase_OR3 TIM_DMABASE_OR3
-#define TIM_DMABase_OR TIM_DMABASE_OR
-
-#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
-
-#if defined(STM32L0)
-#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
-#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
-#endif
-
-#if defined(STM32F3)
-#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
-#endif
-
-#if defined(STM32H7)
-#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
-#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
-#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
-#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
-#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
-#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
-#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
-#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
-#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
-#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
-#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
-#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
-#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
-#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
-#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
- * @{
- */
-#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
-
-#define __DIV_LPUART UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED USART_NACK_ENABLE
-#define USARTNACK_DISABLED USART_NACK_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CFR_BASE WWDG_CFR_BASE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define VLAN_TAG ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR 0x00000100U
-#define ETH_MMCRIR 0x00000104U
-#define ETH_MMCTIR 0x00000108U
-#define ETH_MMCRIMR 0x0000010CU
-#define ETH_MMCTIMR 0x00000110U
-#define ETH_MMCTGFSCCR 0x0000014CU
-#define ETH_MMCTGFMSCCR 0x00000150U
-#define ETH_MMCTGFCR 0x00000168U
-#define ETH_MMCRFCECR 0x00000194U
-#define ETH_MMCRFAECR 0x00000198U
-#define ETH_MMCRGUFCR 0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
-
-/**
- * @}
- */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
- || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
- || defined(STM32H7)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
- * @{
- */
-#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
-#define CM_RGB888 DMA2D_INPUT_RGB888
-#define CM_RGB565 DMA2D_INPUT_RGB565
-#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
-#define CM_L8 DMA2D_INPUT_L8
-#define CM_AL44 DMA2D_INPUT_AL44
-#define CM_AL88 DMA2D_INPUT_AL88
-#define CM_L4 DMA2D_INPUT_L4
-#define CM_A8 DMA2D_INPUT_A8
-#define CM_A4 DMA2D_INPUT_A4
-/**
- * @}
- */
-#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-
-#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
-#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
-#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
-#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
-
-#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
-#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
-#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
-#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
-#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
-#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
-#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
-#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
-#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
-#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-
-#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
-#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
-#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
-#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
-#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
-#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
-
- /**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
-#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
-#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
-#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
-#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
-#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
-#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-
-#if defined(STM32F4)
-#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
-#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
-#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
-#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
-#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
-#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
-#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
-#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
-#endif /* STM32F4 */
- /**
- * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
-#endif
-#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
-#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
-#define CR_PMODE_BB CR_VOS_BB
-
-#define DBP_BitNumber DBP_BIT_NUMBER
-#define PVDE_BitNumber PVDE_BIT_NUMBER
-#define PMODE_BitNumber PMODE_BIT_NUMBER
-#define EWUP_BitNumber EWUP_BIT_NUMBER
-#define FPDS_BitNumber FPDS_BIT_NUMBER
-#define ODEN_BitNumber ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
-#define BRE_BitNumber BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
-
- /**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError TIM_DMAError
-#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
-#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
-#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
-#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
-#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
-#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
-#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define AES_IT_CC CRYP_IT_CC
-#define AES_IT_ERR CRYP_IT_ERR
-#define AES_FLAG_CCF CRYP_FLAG_CCF
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __ADC_ENABLE __HAL_ADC_ENABLE
-#define __ADC_DISABLE __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
-#define __ADC_IS_ENABLED ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1 ADC_SQR1
-#define __HAL_ADC_SMPR1 ADC_SMPR1
-#define __HAL_ADC_SMPR2 ADC_SMPR2
-#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
-#define __HAL_ADC_JSQR ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#if defined(STM32H7)
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
-#else
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#endif /* STM32H7 */
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined(STM32F3)
-#define COMP_START __HAL_COMP_ENABLE
-#define COMP_STOP __HAL_COMP_DISABLE
-#define COMP_LOCK __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro */
-/* is COMP_FLAG_LOCK. */
-/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
-/* argument. */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
- * @}
- */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
- * @}
- */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_WRPAREA IS_OB_WRPAREA
-#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE IS_FLASH_TYPEERASE
-#define IS_NBSECTORS IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
-#define __HAL_I2C_SPEED I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
-
-#if defined(STM32H7)
- #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __IRDA_DISABLE __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
- * @}
- */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
- * @}
- */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
- * @{
- */
-
-#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-
-#if defined(STM32WB)
-#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
-#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
-#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
-#define QSPI_IRQHandler QUADSPI_IRQHandler
-#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
-
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-
-#if defined(STM32H7)
-#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
-#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
-
-#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
-#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
-
-
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
-#endif
-
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-
-#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
-#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
-#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32L1)
-#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#endif /* STM32L1 */
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14 RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE RCC_IT_LSECSS
-#define RCC_IT_CSSHSE RCC_IT_CSS
-
-#define RCC_PLLMUL_3 RCC_PLL_MUL3
-#define RCC_PLLMUL_4 RCC_PLL_MUL4
-#define RCC_PLLMUL_6 RCC_PLL_MUL6
-#define RCC_PLLMUL_8 RCC_PLL_MUL8
-#define RCC_PLLMUL_12 RCC_PLL_MUL12
-#define RCC_PLLMUL_16 RCC_PLL_MUL16
-#define RCC_PLLMUL_24 RCC_PLL_MUL24
-#define RCC_PLLMUL_32 RCC_PLL_MUL32
-#define RCC_PLLMUL_48 RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2 RCC_PLL_DIV2
-#define RCC_PLLDIV_3 RCC_PLL_DIV3
-#define RCC_PLLDIV_4 RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV RCC_MCODIV_1
-#define RCC_MCO_DIV1 RCC_MCODIV_1
-#define RCC_MCO_DIV2 RCC_MCODIV_2
-#define RCC_MCO_DIV4 RCC_MCODIV_4
-#define RCC_MCO_DIV8 RCC_MCODIV_8
-#define RCC_MCO_DIV16 RCC_MCODIV_16
-#define RCC_MCO_DIV32 RCC_MCODIV_32
-#define RCC_MCO_DIV64 RCC_MCODIV_64
-#define RCC_MCO_DIV128 RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
-#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#else
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
-#endif
-
-#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB RCC_CR_HSION_BB
-#define CR_CSSON_BB RCC_CR_CSSON_BB
-#define CR_PLLON_BB RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB RCC_CR_MSION_BB
-#define CSR_LSION_BB RCC_CSR_LSION_BB
-#define CSR_LSEON_BB RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB RCC_CR_HSEON_BB
-#define CSR_RMVF_BB RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
-#else
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
-#endif
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif /* STM32F1 */
-
-#define IS_ALARM IS_RTC_ALARM
-#define IS_ALARM_MASK IS_RTC_ALARM_MASK
-#define IS_TAMPER IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4) || defined(STM32F2)
-#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
-#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define SDMMC1_IRQn SDIO_IRQn
-#define SDMMC1_IRQHandler SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
-#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
-#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
-#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
-#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
-#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
-#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
-#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
-#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
-#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
-#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
-#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
-#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
-#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
-#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define SDIO_IRQn SDMMC1_IRQn
-#define SDIO_IRQHandler SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
-#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
-#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
-#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
-#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
-#endif
-
-#if defined(STM32H7) || defined(STM32L5)
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
-
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
-#define __USART_ENABLE __HAL_USART_ENABLE
-#define __USART_DISABLE __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
- * @{
- */
-#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
- * @}
- */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined(STM32H7)
-#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
-#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
-#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
- * @{
- */
-#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif /* STM32L4 || STM32F4 || STM32F7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
deleted file mode 100644
index 6228edb..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal.h
- * @author MCD Application Team
- * @brief This file contains all the functions prototypes for the HAL
- * module driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_H
-#define __STM32F1xx_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_conf.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HAL
- * @{
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
- * @{
- */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
- * @{
- */
-typedef enum
-{
- HAL_TICK_FREQ_10HZ = 100U,
- HAL_TICK_FREQ_100HZ = 10U,
- HAL_TICK_FREQ_1KHZ = 1U,
- HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
-/**
- * @}
- */
-/* Exported types ------------------------------------------------------------*/
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern HAL_TickFreqTypeDef uwTickFreq;
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
- * @{
- */
-
-/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
- * @brief Freeze/Unfreeze Peripherals in Debug mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @{
- */
-
-/* Peripherals on APB1 */
-/**
- * @brief TIM2 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
-
-/**
- * @brief TIM3 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
-
-#if defined (DBGMCU_CR_DBG_TIM4_STOP)
-/**
- * @brief TIM4 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM5_STOP)
-/**
- * @brief TIM5 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM6_STOP)
-/**
- * @brief TIM6 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM7_STOP)
-/**
- * @brief TIM7 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM12_STOP)
-/**
- * @brief TIM12 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM13_STOP)
-/**
- * @brief TIM13 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM14_STOP)
-/**
- * @brief TIM14 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
-#endif
-
-/**
- * @brief WWDG Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
-
-/**
- * @brief IWDG Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
-
-/**
- * @brief I2C1 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
-
-#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-/**
- * @brief I2C2 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-#endif
-
-#if defined (DBGMCU_CR_DBG_CAN1_STOP)
-/**
- * @brief CAN1 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_CAN2_STOP)
-/**
- * @brief CAN2 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
-#endif
-
-/* Peripherals on APB2 */
-#if defined (DBGMCU_CR_DBG_TIM1_STOP)
-/**
- * @brief TIM1 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM8_STOP)
-/**
- * @brief TIM8 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM9_STOP)
-/**
- * @brief TIM9 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM10_STOP)
-/**
- * @brief TIM10 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM11_STOP)
-/**
- * @brief TIM11 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
-#endif
-
-
-#if defined (DBGMCU_CR_DBG_TIM15_STOP)
-/**
- * @brief TIM15 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM16_STOP)
-/**
- * @brief TIM16 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM17_STOP)
-/**
- * @brief TIM17 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Private_Macros HAL Private Macros
- * @{
- */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
- ((FREQ) == HAL_TICK_FREQ_100HZ) || \
- ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions
- * @{
- */
-/** @addtogroup HAL_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Variables HAL Private Variables
- * @{
- */
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Constants HAL Private Constants
- * @{
- */
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
deleted file mode 100644
index ce96197..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CORTEX_H
-#define __STM32F1xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CORTEX
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
- * @{
- */
-
-#if (__MPU_PRESENT == 1U)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
- * @brief MPU Region initialization structure
- * @{
- */
-typedef struct
-{
- uint8_t Enable; /*!< Specifies the status of the region.
- This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
- uint8_t Number; /*!< Specifies the number of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Number */
- uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
- uint8_t Size; /*!< Specifies the size of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Size */
- uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint8_t TypeExtField; /*!< Specifies the TEX field level.
- This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
- uint8_t AccessPermission; /*!< Specifies the region access permission type.
- This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
- uint8_t DisableExec; /*!< Specifies the instruction access status.
- This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
- This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
-}MPU_Region_InitTypeDef;
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
- * @{
- */
-#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
- * @{
- */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
-#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
-
-/**
- * @}
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
- * @{
- */
-#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
-#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
-#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
-#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
- * @{
- */
-#define MPU_REGION_ENABLE ((uint8_t)0x01)
-#define MPU_REGION_DISABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
- * @{
- */
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
- * @{
- */
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
- * @{
- */
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
- * @{
- */
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
- * @{
- */
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
- * @{
- */
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
- * @{
- */
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
- * @{
- */
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-
-/* Exported Macros -----------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
- * @{
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
- * @}
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
- * @{
- */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1U)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
- ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
- ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
- ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
- ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
- ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
- ((TYPE) == MPU_TEX_LEVEL1) || \
- ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RW) || \
- ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
- ((TYPE) == MPU_REGION_FULL_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RO) || \
- ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
- ((NUMBER) == MPU_REGION_NUMBER1) || \
- ((NUMBER) == MPU_REGION_NUMBER2) || \
- ((NUMBER) == MPU_REGION_NUMBER3) || \
- ((NUMBER) == MPU_REGION_NUMBER4) || \
- ((NUMBER) == MPU_REGION_NUMBER5) || \
- ((NUMBER) == MPU_REGION_NUMBER6) || \
- ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
- ((SIZE) == MPU_REGION_SIZE_64B) || \
- ((SIZE) == MPU_REGION_SIZE_128B) || \
- ((SIZE) == MPU_REGION_SIZE_256B) || \
- ((SIZE) == MPU_REGION_SIZE_512B) || \
- ((SIZE) == MPU_REGION_SIZE_1KB) || \
- ((SIZE) == MPU_REGION_SIZE_2KB) || \
- ((SIZE) == MPU_REGION_SIZE_4KB) || \
- ((SIZE) == MPU_REGION_SIZE_8KB) || \
- ((SIZE) == MPU_REGION_SIZE_16KB) || \
- ((SIZE) == MPU_REGION_SIZE_32KB) || \
- ((SIZE) == MPU_REGION_SIZE_64KB) || \
- ((SIZE) == MPU_REGION_SIZE_128KB) || \
- ((SIZE) == MPU_REGION_SIZE_256KB) || \
- ((SIZE) == MPU_REGION_SIZE_512KB) || \
- ((SIZE) == MPU_REGION_SIZE_1MB) || \
- ((SIZE) == MPU_REGION_SIZE_2MB) || \
- ((SIZE) == MPU_REGION_SIZE_4MB) || \
- ((SIZE) == MPU_REGION_SIZE_8MB) || \
- ((SIZE) == MPU_REGION_SIZE_16MB) || \
- ((SIZE) == MPU_REGION_SIZE_32MB) || \
- ((SIZE) == MPU_REGION_SIZE_64MB) || \
- ((SIZE) == MPU_REGION_SIZE_128MB) || \
- ((SIZE) == MPU_REGION_SIZE_256MB) || \
- ((SIZE) == MPU_REGION_SIZE_512MB) || \
- ((SIZE) == MPU_REGION_SIZE_1GB) || \
- ((SIZE) == MPU_REGION_SIZE_2GB) || \
- ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CORTEX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
deleted file mode 100644
index 6ff1109..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_def.h
- * @author MCD Application Team
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DEF
-#define __STM32F1xx_HAL_DEF
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-#include "Legacy/stm32_hal_legacy.h"
-#include
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL Status structures definition
- */
-typedef enum
-{
- HAL_OK = 0x00U,
- HAL_ERROR = 0x01U,
- HAL_BUSY = 0x02U,
- HAL_TIMEOUT = 0x03U
-} HAL_StatusTypeDef;
-
-/**
- * @brief HAL Lock structures definition
- */
-typedef enum
-{
- HAL_UNLOCKED = 0x00U,
- HAL_LOCKED = 0x01U
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-#define HAL_MAX_DELAY 0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
- do{ \
- (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
- (__DMA_HANDLE__).Parent = (__HANDLE__); \
- } while(0U)
-
-#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
-
-/** @brief Reset the Handle's State field.
- * @param __HANDLE__ specifies the Peripheral Handle.
- * @note This macro can be used for the following purpose:
- * - When the Handle is declared as local variable; before passing it as parameter
- * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
- * to set to 0 the Handle's "State" field.
- * Otherwise, "State" field may have any random value and the first time the function
- * HAL_PPP_Init() is called, the low level hardware initialization will be missed
- * (i.e. HAL_PPP_MspInit() will not be executed).
- * - When there is a need to reconfigure the low level hardware: instead of calling
- * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
- * In this later function, when the Handle's "State" field is set to 0, it will execute the function
- * HAL_PPP_MspInit() which will reconfigure the low level hardware.
- * @retval None
- */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-
-#if (USE_RTOS == 1U)
-/* Reserved for future use */
-#error "USE_RTOS should be 0 in the current HAL release"
-#else
-#define __HAL_LOCK(__HANDLE__) \
- do{ \
- if((__HANDLE__)->Lock == HAL_LOCKED) \
- { \
- return HAL_BUSY; \
- } \
- else \
- { \
- (__HANDLE__)->Lock = HAL_LOCKED; \
- } \
- }while (0U)
-
-#define __HAL_UNLOCK(__HANDLE__) \
- do{ \
- (__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0U)
-#endif /* USE_RTOS */
-
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-#ifndef __weak
-#define __weak __attribute__((weak))
-#endif
-#ifndef __packed
-#define __packed __attribute__((packed))
-#endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-#ifndef __weak
-#define __weak __attribute__((weak))
-#endif /* __weak */
-#ifndef __packed
-#define __packed __attribute__((__packed__))
-#endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-#ifndef __ALIGN_BEGIN
-#define __ALIGN_BEGIN
-#endif
-#ifndef __ALIGN_END
-#define __ALIGN_END __attribute__ ((aligned (4)))
-#endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-#ifndef __ALIGN_END
-#define __ALIGN_END __attribute__ ((aligned (4)))
-#endif /* __ALIGN_END */
-#ifndef __ALIGN_BEGIN
-#define __ALIGN_BEGIN
-#endif /* __ALIGN_BEGIN */
-#else
-#ifndef __ALIGN_END
-#define __ALIGN_END
-#endif /* __ALIGN_END */
-#ifndef __ALIGN_BEGIN
-#if defined (__CC_ARM) /* ARM Compiler V5*/
-#define __ALIGN_BEGIN __align(4)
-#elif defined (__ICCARM__) /* IAR Compiler */
-#define __ALIGN_BEGIN
-#endif /* __CC_ARM */
-#endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-
-/**
- * @brief __RAM_FUNC definition
- */
-#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-/* ARM Compiler V4/V5 and V6
- --------------------------
- RAM functions are defined using the toolchain options.
- Functions that are executed in RAM should reside in a separate source module.
- Using the 'Options for File' dialog you can simply change the 'Code / Const'
- area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the 'Options for Target'
- dialog.
-*/
-#define __RAM_FUNC
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
- ---------------
- RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc
-
-#elif defined ( __GNUC__ )
-/* GNU Compiler
- ------------
- RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC __attribute__((section(".RamFunc")))
-
-#endif
-
-/**
- * @brief __NOINLINE definition
- */
-#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
-/* ARM V4/V5 and V6 & GNU Compiler
- -------------------------------
-*/
-#define __NOINLINE __attribute__ ( (noinline) )
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
- ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32F1xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
deleted file mode 100644
index 7b2304d..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
+++ /dev/null
@@ -1,457 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DMA_H
-#define __STM32F1xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
- * @{
- */
-
-/**
- * @brief DMA Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_Data_transfer_direction */
-
- uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
- uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
- This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
- uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_Peripheral_data_size */
-
- uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_Memory_data_size */
-
- uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_mode
- @note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
-
- uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
- * @brief HAL DMA State structures definition
- */
-typedef enum
-{
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
-}HAL_DMA_StateTypeDef;
-
-/**
- * @brief HAL DMA Error Code structure definition
- */
-typedef enum
-{
- HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/**
- * @brief HAL DMA Callback ID structure definition
- */
-typedef enum
-{
- HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
- HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
- HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
- HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
- HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
-
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
- * @brief DMA handle Structure definition
- */
-typedef struct __DMA_HandleTypeDef
-{
- DMA_Channel_TypeDef *Instance; /*!< Register base address */
-
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA locking object */
-
- HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
- void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
- void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
-
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
-
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
- DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
-
- uint32_t ChannelIndex; /*!< DMA Channel Index */
-
-} DMA_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
- * @{
- */
-
-/** @defgroup DMA_Error_Code DMA Error Code
- * @{
- */
-#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
-#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */
-#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
-#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
- * @{
- */
-#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
- * @{
- */
-#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
- * @{
- */
-#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
- * @{
- */
-#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
-#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @{
- */
-#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
-#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_mode DMA mode
- * @{
- */
-#define DMA_NORMAL 0x00000000U /*!< Normal mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Priority_level DMA Priority level
- * @{
- */
-#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
-#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
-#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
- * @{
- */
-#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
-#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
-#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
-/**
- * @}
- */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
- * @{
- */
-#define DMA_FLAG_GL1 0x00000001U
-#define DMA_FLAG_TC1 0x00000002U
-#define DMA_FLAG_HT1 0x00000004U
-#define DMA_FLAG_TE1 0x00000008U
-#define DMA_FLAG_GL2 0x00000010U
-#define DMA_FLAG_TC2 0x00000020U
-#define DMA_FLAG_HT2 0x00000040U
-#define DMA_FLAG_TE2 0x00000080U
-#define DMA_FLAG_GL3 0x00000100U
-#define DMA_FLAG_TC3 0x00000200U
-#define DMA_FLAG_HT3 0x00000400U
-#define DMA_FLAG_TE3 0x00000800U
-#define DMA_FLAG_GL4 0x00001000U
-#define DMA_FLAG_TC4 0x00002000U
-#define DMA_FLAG_HT4 0x00004000U
-#define DMA_FLAG_TE4 0x00008000U
-#define DMA_FLAG_GL5 0x00010000U
-#define DMA_FLAG_TC5 0x00020000U
-#define DMA_FLAG_HT5 0x00040000U
-#define DMA_FLAG_TE5 0x00080000U
-#define DMA_FLAG_GL6 0x00100000U
-#define DMA_FLAG_TC6 0x00200000U
-#define DMA_FLAG_HT6 0x00400000U
-#define DMA_FLAG_TE6 0x00800000U
-#define DMA_FLAG_GL7 0x01000000U
-#define DMA_FLAG_TC7 0x02000000U
-#define DMA_FLAG_HT7 0x04000000U
-#define DMA_FLAG_TE7 0x08000000U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @brief Reset DMA handle state.
- * @param __HANDLE__: DMA handle
- * @retval None
- */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
- * @brief Enable the specified DMA Channel.
- * @param __HANDLE__: DMA handle
- * @retval None
- */
-#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
-
-/**
- * @brief Disable the specified DMA Channel.
- * @param __HANDLE__: DMA handle
- * @retval None
- */
-#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
-
-
-/* Interrupt & Flag management */
-
-/**
- * @brief Enables the specified DMA Channel interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
-
-/**
- * @brief Disable the specified DMA Channel interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
-
-/**
- * @brief Check whether the specified DMA Channel interrupt is enabled or not.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval The state of DMA_IT (SET or RESET).
- */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Return the number of remaining data units in the current DMA Channel transfer.
- * @param __HANDLE__: DMA handle
- * @retval The number of remaining data units in the current DMA Channel transfer.
- */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
- * @}
- */
-
-/* Include DMA HAL Extension module */
-#include "stm32f1xx_hal_dma_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
- * @{
- */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
deleted file mode 100644
index d861f50..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_dma_ex.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DMA_EX_H
-#define __STM32F1xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMAEx DMAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
- * @{
- */
-/* Interrupt & Flag management */
-#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
- defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
- * @{
- */
-
-/**
- * @brief Returns the current DMA Channel transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer complete flag index.
- */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
- DMA_FLAG_TC5)
-
-/**
- * @brief Returns the current DMA Channel half transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
- DMA_FLAG_HT5)
-
-/**
- * @brief Returns the current DMA Channel transfer error flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
- DMA_FLAG_TE5)
-
-/**
- * @brief Return the current DMA Channel Global interrupt flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
- DMA_FLAG_GL5)
-
-/**
- * @brief Get the DMA Channel pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
- (DMA1->ISR & (__FLAG__)))
-
-/**
- * @brief Clears the DMA Channel pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
- (DMA1->IFCR = (__FLAG__)))
-
-/**
- * @}
- */
-
-#else
-/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
- * @{
- */
-
-/**
- * @brief Returns the current DMA Channel transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer complete flag index.
- */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- DMA_FLAG_TC7)
-
-/**
- * @brief Return the current DMA Channel half transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- DMA_FLAG_HT7)
-
-/**
- * @brief Return the current DMA Channel transfer error flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- DMA_FLAG_TE7)
-
-/**
- * @brief Return the current DMA Channel Global interrupt flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
- DMA_FLAG_GL7)
-
-/**
- * @brief Get the DMA Channel pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * @arg DMA_FLAG_GLx: Global interrupt flag
- * Where x can be 1_7 to select the DMA Channel flag.
- * @retval The state of FLAG (SET or RESET).
- */
-
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
-
-/**
- * @brief Clear the DMA Channel pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * @arg DMA_FLAG_GLx: Global interrupt flag
- * Where x can be 1_7 to select the DMA Channel flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
-
-/**
- * @}
- */
-
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
- /* STM32F103xG || STM32F105xC || STM32F107xC */
-
-#endif /* __STM32F1xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
deleted file mode 100644
index 5d3b049..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F1xx_HAL_EXTI_H
-#define STM32F1xx_HAL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup EXTI EXTI
- * @brief EXTI HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Types EXTI Exported Types
- * @{
- */
-
-/**
- * @brief HAL EXTI common Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_EXTI_COMMON_CB_ID = 0x00U
-} EXTI_CallbackIDTypeDef;
-
-/**
- * @brief EXTI Handle structure definition
- */
-typedef struct
-{
- uint32_t Line; /*!< Exti line number */
- void (* PendingCallback)(void); /*!< Exti pending callback */
-} EXTI_HandleTypeDef;
-
-/**
- * @brief EXTI Configuration structure definition
- */
-typedef struct
-{
- uint32_t Line; /*!< The Exti line to be configured. This parameter
- can be a value of @ref EXTI_Line */
- uint32_t Mode; /*!< The Exit Mode to be configured for a core.
- This parameter can be a combination of @ref EXTI_Mode */
- uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
- can be a value of @ref EXTI_Trigger */
- uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
- This parameter is only possible for line 0 to 15. It
- can be a value of @ref EXTI_GPIOSel */
-} EXTI_ConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_Line EXTI Line
- * @{
- */
-#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
-#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
-#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
-#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
-#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
-#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
-#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
-#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
-#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
-#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
-#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
-#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
-#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
-#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
-#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
-#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
-#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#if defined(EXTI_IMR_IM18)
-#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */
-#endif /* EXTI_IMR_IM18 */
-#if defined(EXTI_IMR_IM19)
-#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#endif /* EXTI_IMR_IM19 */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Mode EXTI Mode
- * @{
- */
-#define EXTI_MODE_NONE 0x00000000u
-#define EXTI_MODE_INTERRUPT 0x00000001u
-#define EXTI_MODE_EVENT 0x00000002u
-/**
- * @}
- */
-
-/** @defgroup EXTI_Trigger EXTI Trigger
- * @{
- */
-#define EXTI_TRIGGER_NONE 0x00000000u
-#define EXTI_TRIGGER_RISING 0x00000001u
-#define EXTI_TRIGGER_FALLING 0x00000002u
-#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-/**
- * @}
- */
-
-/** @defgroup EXTI_GPIOSel EXTI GPIOSel
- * @brief
- * @{
- */
-#define EXTI_GPIOA 0x00000000u
-#define EXTI_GPIOB 0x00000001u
-#define EXTI_GPIOC 0x00000002u
-#define EXTI_GPIOD 0x00000003u
-#if defined (GPIOE)
-#define EXTI_GPIOE 0x00000004u
-#endif /* GPIOE */
-#if defined (GPIOF)
-#define EXTI_GPIOF 0x00000005u
-#endif /* GPIOF */
-#if defined (GPIOG)
-#define EXTI_GPIOG 0x00000006u
-#endif /* GPIOG */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
- * @{
- */
-/**
- * @brief EXTI Line property definition
- */
-#define EXTI_PROPERTY_SHIFT 24u
-#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
-#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
-
-/**
- * @brief EXTI bit usage
- */
-#define EXTI_PIN_MASK 0x0000001Fu
-
-/**
- * @brief EXTI Mask for interrupt & event mode
- */
-#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
-
-/**
- * @brief EXTI Mask for trigger possibilities
- */
-#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-
-/**
- * @brief EXTI Line number
- */
-#if defined(EXTI_IMR_IM19)
-#define EXTI_LINE_NB 20UL
-#elif defined(EXTI_IMR_IM18)
-#define EXTI_LINE_NB 19UL
-#else /* EXTI_IMR_IM17 */
-#define EXTI_LINE_NB 18UL
-#endif /* EXTI_IMR_IM19 */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
- * @{
- */
-#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
- ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
-
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
- (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
-
-#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
-
-#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
-
-#if defined (GPIOG)
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || \
- ((__PORT__) == EXTI_GPIOF) || \
- ((__PORT__) == EXTI_GPIOG))
-#elif defined (GPIOF)
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || \
- ((__PORT__) == EXTI_GPIOF))
-#elif defined (GPIOE)
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE))
-#else
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD))
-#endif /* GPIOG */
-
-#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
- * @brief EXTI Exported Functions
- * @{
- */
-
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
- * @brief Configuration functions
- * @{
- */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F1xx_HAL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
deleted file mode 100644
index 8cd21b1..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_flash.h
- * @author MCD Application Team
- * @brief Header file of Flash HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_FLASH_H
-#define __STM32F1xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/** @addtogroup FLASH_Private_Constants
- * @{
- */
-#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Private_Macros
- * @{
- */
-
-#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
-
-#if defined(FLASH_ACR_LATENCY)
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
- ((__LATENCY__) == FLASH_LATENCY_1) || \
- ((__LATENCY__) == FLASH_LATENCY_2))
-
-#else
-#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
-#endif /* FLASH_ACR_LATENCY */
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Procedure structure definition
- */
-typedef enum
-{
- FLASH_PROC_NONE = 0U,
- FLASH_PROC_PAGEERASE = 1U,
- FLASH_PROC_MASSERASE = 2U,
- FLASH_PROC_PROGRAMHALFWORD = 3U,
- FLASH_PROC_PROGRAMWORD = 4U,
- FLASH_PROC_PROGRAMDOUBLEWORD = 5U
-} FLASH_ProcedureTypeDef;
-
-/**
- * @brief FLASH handle Structure definition
- */
-typedef struct
-{
- __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
-
- __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
-
- __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
-
- __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
-
- HAL_LockTypeDef Lock; /*!< FLASH locking object */
-
- __IO uint32_t ErrorCode; /*!< FLASH error code
- This parameter can be a value of @ref FLASH_Error_Codes */
-} FLASH_ProcessTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
- * @{
- */
-
-/** @defgroup FLASH_Error_Codes FLASH Error Codes
- * @{
- */
-
-#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
-#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
-#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
-#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
- * @{
- */
-#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA)
-
-/**
- * @brief Disable the FLASH half cycle access.
- * @note half cycle access can only be used with a low-frequency clock of less than
- 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
- * @retval None
- */
-#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
-
-/**
- * @}
- */
-
-#if defined(FLASH_ACR_LATENCY)
-/** @defgroup FLASH_EM_Latency FLASH Latency
- * @brief macros to handle FLASH Latency
- * @{
- */
-
-/**
- * @brief Set the FLASH Latency.
- * @param __LATENCY__ FLASH Latency
- * The value of this parameter depend on device used within the same series
- * @retval None
- */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
-
-
-/**
- * @brief Get the FLASH Latency.
- * @retval FLASH Latency
- * The value of this parameter depend on device used within the same series
- */
-#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
- * @}
- */
-
-#endif /* FLASH_ACR_LATENCY */
-/** @defgroup FLASH_Prefetch FLASH Prefetch
- * @brief macros to handle FLASH Prefetch buffer
- * @{
- */
-/**
- * @brief Enable the FLASH prefetch buffer.
- * @retval None
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
-
-/**
- * @brief Disable the FLASH prefetch buffer.
- * @retval None
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Include FLASH HAL Extended module */
-#include "stm32f1xx_hal_flash_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
- * @{
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group1
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-
-/* FLASH IRQ handler function */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-void HAL_FLASH_OB_Launch(void);
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_FLASH_GetError(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private function -------------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-#if defined(FLASH_BANK2_END)
-HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
-#endif /* FLASH_BANK2_END */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
deleted file mode 100644
index 1dcaeed..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
+++ /dev/null
@@ -1,786 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_flash_ex.h
- * @author MCD Application Team
- * @brief Header file of Flash HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_FLASH_EX_H
-#define __STM32F1xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASHEx
- * @{
- */
-
-/** @addtogroup FLASHEx_Private_Constants
- * @{
- */
-
-#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
-#define OBR_REG_INDEX 1U
-#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Private_Macros
- * @{
- */
-
-#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
-
-#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
-
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
-
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#if defined(FLASH_BANK2_END)
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-#endif /* FLASH_BANK2_END */
-
-/* Low Density */
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-
-/* Medium Density */
-#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
-
-/* High Density */
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
-
-/* XL Density */
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
-#endif /* FLASH_BANK2_END */
-
-/* Connectivity Line */
-#if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
-#endif /* STM32F105xC || STM32F107xC */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
-
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2) || \
- ((BANK) == FLASH_BANK_BOTH))
-#else
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#endif /* FLASH_BANK2_END */
-
-/* Low Density */
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
-
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-
-/* Medium Density */
-#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
- ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
- ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
-
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
-
-/* High Density */
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
- ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
-
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
-
-/* XL Density */
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
- ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
-
-#endif /* FLASH_BANK2_END */
-
-/* Connectivity Line */
-#if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
- ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Erase structure definition
- */
-typedef struct
-{
- uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
- This parameter can be a value of @ref FLASHEx_Type_Erase */
-
- uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
- This parameter must be a value of @ref FLASHEx_Banks */
-
- uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
- This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
- (x = 1 or 2 depending on devices)*/
-
- uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
- This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
-
-} FLASH_EraseInitTypeDef;
-
-/**
- * @brief FLASH Options bytes program structure definition
- */
-typedef struct
-{
- uint32_t OptionType; /*!< OptionType: Option byte to be configured.
- This parameter can be a value of @ref FLASHEx_OB_Type */
-
- uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
- This parameter can be a value of @ref FLASHEx_OB_WRP_State */
-
- uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
- This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
-
- uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
- This parameter must be a value of @ref FLASHEx_Banks */
-
- uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
- This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
-
-#if defined(FLASH_BANK2_END)
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
- IWDG / STOP / STDBY / BOOT1
- This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
- @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
-#else
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
- IWDG / STOP / STDBY
- This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
- @ref FLASHEx_OB_nRST_STDBY */
-#endif /* FLASH_BANK2_END */
-
- uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
- This parameter can be a value of @ref FLASHEx_OB_Data_Address */
-
- uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-} FLASH_OBProgramInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
- * @{
- */
-
-/** @defgroup FLASHEx_Constants FLASH Constants
- * @{
- */
-
-/** @defgroup FLASHEx_Page_Size Page Size
- * @{
- */
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define FLASH_PAGE_SIZE 0x400U
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
- /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
-#define FLASH_PAGE_SIZE 0x800U
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
- /* STM32F101xG || STM32F103xG */
- /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Type_Erase Type Erase
- * @{
- */
-#define FLASH_TYPEERASE_PAGES 0x00U /*!CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
- /* Enable Bank2 IT */ \
- SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
- } while(0U)
-
-/**
- * @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
- * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
- * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
- * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
- * @retval none
- */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
- /* Disable Bank1 IT */ \
- CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
- /* Disable Bank2 IT */ \
- CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
- } while(0U)
-
-/**
- * @brief Get the specified FLASH flag status.
- * @param __FLAG__ specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
- * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
- * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
- * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
- * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
- * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
- * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
- * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
- (FLASH->OBR & FLASH_OBR_OPTERR) : \
- ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
- (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
- (FLASH->SR2 & ((__FLAG__) >> 16U))))
-
-/**
- * @brief Clear the specified FLASH flag.
- * @param __FLAG__ specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
- * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
- * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
- * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
- * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
- * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
- * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
- * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
- * @retval none
- */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
- /* Clear FLASH_FLAG_OPTVERR flag */ \
- if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
- { \
- CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
- } \
- else { \
- /* Clear Flag in Bank1 */ \
- if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
- { \
- FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
- } \
- /* Clear Flag in Bank2 */ \
- if (((__FLAG__) >> 16U) != RESET) \
- { \
- FLASH->SR2 = ((__FLAG__) >> 16U); \
- } \
- } \
- } while(0U)
-#else
-/**
- * @brief Enable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
- * @arg @ref FLASH_IT_ERR Error Interrupt
- * @retval none
- */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
- * @arg @ref FLASH_IT_ERR Error Interrupt
- * @retval none
- */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Get the specified FLASH flag status.
- * @param __FLAG__ specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
- * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
- * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
- * @arg @ref FLASH_FLAG_BSY FLASH Busy flag
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
- (FLASH->OBR & FLASH_OBR_OPTERR) : \
- (FLASH->SR & (__FLAG__)))
-/**
- * @brief Clear the specified FLASH flag.
- * @param __FLAG__ specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
- * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
- * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
- * @retval none
- */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
- /* Clear FLASH_FLAG_OPTVERR flag */ \
- if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
- { \
- CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
- } \
- else { \
- /* Clear Flag in Bank1 */ \
- FLASH->SR = (__FLAG__); \
- } \
- } while(0U)
-
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
deleted file mode 100644
index 2973944..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F1xx_HAL_GPIO_H
-#define STM32F1xx_HAL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
- * @{
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_mode_define */
-
- uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
- This parameter can be a value of @ref GPIO_pull_define */
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_speed_define */
-} GPIO_InitTypeDef;
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum
-{
- GPIO_PIN_RESET = 0u,
- GPIO_PIN_SET
-} GPIO_PinState;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define GPIO pins define
- * @{
- */
-#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
-
-#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */
-/**
- * @}
- */
-
-/** @defgroup GPIO_mode_define GPIO mode define
- * @brief GPIO Configuration Mode
- * Elements values convention: 0xX0yz00YZ
- * - X : GPIO mode or EXTI Mode
- * - y : External IT or Event trigger detection
- * - z : IO configuration on External IT or Event
- * - Y : Output type (Push Pull or Open Drain)
- * - Z : IO Direction mode (Input, Output, Alternate or Analog)
- * @{
- */
-#define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */
-#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
-
-#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */
-
-#define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_speed_define GPIO speed define
- * @brief GPIO Output Maximum frequency
- * @{
- */
-#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
-#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
-#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_pull_define GPIO pull define
- * @brief GPIO Pull-Up or Pull-Down Activation
- * @{
- */
-#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
-#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param __EXTI_LINE__: specifies the EXTI line flag to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param __EXTI_LINE__: specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param __EXTI_LINE__: specifies the EXTI lines to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-/**
- * @}
- */
-
-/* Include GPIO HAL Extension module */
-#include "stm32f1xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
-/**
- * @}
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
- * @{
- */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u))
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
- ((MODE) == GPIO_MODE_AF_PP) ||\
- ((MODE) == GPIO_MODE_AF_OD) ||\
- ((MODE) == GPIO_MODE_IT_RISING) ||\
- ((MODE) == GPIO_MODE_IT_FALLING) ||\
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING) ||\
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
- ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
- ((PULL) == GPIO_PULLDOWN))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Functions GPIO Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F1xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
deleted file mode 100644
index 56bcb85..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,894 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_gpio_ex.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F1xx_HAL_GPIO_EX_H
-#define STM32F1xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIOEx GPIOEx
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
- * @{
- */
-
-/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
- * @brief This section propose definition to use the Cortex EVENTOUT signal.
- * @{
- */
-
-/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
- * @{
- */
-
-#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
-#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
-#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
-#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
-#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
-#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
-#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
-#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
-#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
-#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
-#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
-#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
-#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
-#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
-#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
-#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
-
-#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_15))
-/**
- * @}
- */
-
-/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
- * @{
- */
-
-#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
-#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
-#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
-#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
-#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
-
-#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
- ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
- ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
- ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
- ((__PORT__) == AFIO_EVENTOUT_PORT_E))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
- * @brief This section propose definition to remap the alternate function to some other port/pins.
- * @{
- */
-
-/**
- * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
- * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
-
-/**
- * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
- * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
-
-/**
- * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
- * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
-
-/**
- * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
- * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
-
-/**
- * @brief Enable the remapping of USART1 alternate function TX and RX.
- * @note ENABLE: Remap (TX/PB6, RX/PB7)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
-
-/**
- * @brief Disable the remapping of USART1 alternate function TX and RX.
- * @note DISABLE: No remap (TX/PA9, RX/PA10)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
-
-/**
- * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
- * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
-
-/**
- * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
- * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
-
-/**
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
-
-/**
- * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
-
-/**
- * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
- * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
- * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
- * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
-
-/**
- * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
- * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
- * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
- * @note TIM4_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
-
-/**
- * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
- * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
- * @note TIM4_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
-
-#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
-
-#endif
-
-/**
- * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
- * on 100-pin and 144-pin packages, no need for remapping).
- * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
-
-/**
- * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
- * on 100-pin and 144-pin packages, no need for remapping).
- * @note DISABLE: No remapping of PD0 and PD1
- * @retval None
- */
-#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
-
-#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
-/**
- * @brief Enable the remapping of TIM5CH4.
- * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
- * @note This function is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
-
-/**
- * @brief Disable the remapping of TIM5CH4.
- * @note DISABLE: TIM5_CH4 is connected to PA3
- * @note This function is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
-#endif
-
-#if defined(AFIO_MAPR_ETH_REMAP)
-/**
- * @brief Enable the remapping of Ethernet MAC connections with the PHY.
- * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
-
-/**
- * @brief Disable the remapping of Ethernet MAC connections with the PHY.
- * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_CAN2_REMAP)
-
-/**
- * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
- * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
-
-/**
- * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
- * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_MII_RMII_SEL)
-/**
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
- * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
-
-/**
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
- * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
-#endif
-
-/**
- * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
- * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
-
-/**
- * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
- * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
-
-/**
- * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
- * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
-
-/**
- * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
- * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
-
-#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
- * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
- * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-#endif
-
-#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
-#endif
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
- * @retval None
- */
-
-#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
-
-/**
- * @brief Disable the Serial wire JTAG configuration
- * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
-
-#if defined(AFIO_MAPR_SPI3_REMAP)
-
-/**
- * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
- * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
-
-/**
- * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
- * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
-
-/**
- * @brief Control of TIM2_ITR1 internal mapping.
- * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
-
-/**
- * @brief Control of TIM2_ITR1 internal mapping.
- * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
-#endif
-
-#if defined(AFIO_MAPR_PTP_PPS_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @note ENABLE: PTP_PPS is output on PB5 pin.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @note DISABLE: PTP_PPS not output on PB5 pin.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM9_REMAP)
-
-/**
- * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
- * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
-
-/**
- * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
- * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM10_REMAP)
-
-/**
- * @brief Enable the remapping of TIM10_CH1.
- * @note ENABLE: Remap (TIM10_CH1 on PF6).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
-
-/**
- * @brief Disable the remapping of TIM10_CH1.
- * @note DISABLE: No remap (TIM10_CH1 on PB8).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM11_REMAP)
-/**
- * @brief Enable the remapping of TIM11_CH1.
- * @note ENABLE: Remap (TIM11_CH1 on PF7).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
-
-/**
- * @brief Disable the remapping of TIM11_CH1.
- * @note DISABLE: No remap (TIM11_CH1 on PB9).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM13_REMAP)
-
-/**
- * @brief Enable the remapping of TIM13_CH1.
- * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
-
-/**
- * @brief Disable the remapping of TIM13_CH1.
- * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM14_REMAP)
-
-/**
- * @brief Enable the remapping of TIM14_CH1.
- * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
-
-/**
- * @brief Disable the remapping of TIM14_CH1.
- * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
-
-/**
- * @brief Controls the use of the optional FSMC_NADV signal.
- * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
- * @retval None
- */
-#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
-
-/**
- * @brief Controls the use of the optional FSMC_NADV signal.
- * @note CONNECTED: The NADV signal is connected to the output (default).
- * @retval None
- */
-#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM15_REMAP)
-
-/**
- * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
- * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
-
-/**
- * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
- * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM16_REMAP)
-
-/**
- * @brief Enable the remapping of TIM16_CH1.
- * @note ENABLE: Remap (TIM16_CH1 on PA6).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
-
-/**
- * @brief Disable the remapping of TIM16_CH1.
- * @note DISABLE: No remap (TIM16_CH1 on PB8).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM17_REMAP)
-
-/**
- * @brief Enable the remapping of TIM17_CH1.
- * @note ENABLE: Remap (TIM17_CH1 on PA7).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
-
-/**
- * @brief Disable the remapping of TIM17_CH1.
- * @note DISABLE: No remap (TIM17_CH1 on PB9).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_CEC_REMAP)
-
-/**
- * @brief Enable the remapping of CEC.
- * @note ENABLE: Remap (CEC on PB10).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
-
-/**
- * @brief Disable the remapping of CEC.
- * @note DISABLE: No remap (CEC on PB8).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
- * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
- * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
- * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
- * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM12_REMAP)
-
-/**
- * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
- * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
-
-/**
- * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
- * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_MISC_REMAP)
-
-/**
- * @brief Miscellaneous features remapping.
- * This bit is set and cleared by software. It controls miscellaneous features.
- * The DMA2 channel 5 interrupt position in the vector table.
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
- * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
- * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
-
-/**
- * @brief Miscellaneous features remapping.
- * This bit is set and cleared by software. It controls miscellaneous features.
- * The DMA2 channel 5 interrupt position in the vector table.
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
- * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
- * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
- * @{
- */
-#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :3uL)
-#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :\
- ((__GPIOx__) == (GPIOD))? 3uL :4uL)
-#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :\
- ((__GPIOx__) == (GPIOD))? 3uL :\
- ((__GPIOx__) == (GPIOE))? 4uL :\
- ((__GPIOx__) == (GPIOF))? 5uL :6uL)
-#endif
-
-#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
- tmpreg |= AFIO_MAPR_SWJ_CFG; \
- tmpreg |= REMAP_PIN; \
- AFIO->MAPR = tmpreg; \
- }while(0u)
-
-#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
- tmpreg |= AFIO_MAPR_SWJ_CFG; \
- tmpreg &= ~REMAP_PIN; \
- AFIO->MAPR = tmpreg; \
- }while(0u)
-
-#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \
- tmpreg &= ~REMAP_PIN_MASK; \
- tmpreg |= AFIO_MAPR_SWJ_CFG; \
- tmpreg |= REMAP_PIN; \
- AFIO->MAPR = tmpreg; \
- }while(0u)
-
-#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \
- tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
- tmpreg |= DBGAFR_SWJCFG; \
- AFIO->MAPR = tmpreg; \
- }while(0u)
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup GPIOEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIOEx_Exported_Functions_Group1
- * @{
- */
-void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
-void HAL_GPIOEx_EnableEventout(void);
-void HAL_GPIOEx_DisableEventout(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F1xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
deleted file mode 100644
index 2b1b4ed..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
+++ /dev/null
@@ -1,388 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PWR_H
-#define __STM32F1xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
- * @{
- */
-
-/**
- * @brief PWR PVD configuration structure definition
- */
-typedef struct
-{
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
- This parameter can be a value of @ref PWR_PVD_detection_level */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-
-/**
- * @}
- */
-
-
-/* Internal constants --------------------------------------------------------*/
-
-/** @addtogroup PWR_Private_Constants
- * @{
- */
-
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-
-/**
- * @}
- */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
- * @{
- */
-#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
-#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
-#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
-#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
-#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
-#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
-#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
-#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
-
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
- * @{
- */
-#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
-
-/**
- * @}
- */
-
-
-/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
- * @{
- */
-
-#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
- * @{
- */
-#define PWR_MAINREGULATOR_ON 0x00000000U
-#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
-
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
- * @{
- */
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
- * @{
- */
-#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
-#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag PWR Flag
- * @{
- */
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @brief Check PWR flag is set or not.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
- * was received from the WKUP pin or from the RTC alarm
- * An additional wakeup event is detected if the WKUP pin is enabled
- * (by setting the EWUP bit) when the WKUP pin level is already high.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
- * resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the PWR's pending flags.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
-
-/**
- * @brief Enable interrupt on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable interrupt on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable event on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable event on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief PVD EXTI line configuration: set falling edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Disable the PVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief PVD EXTI line configuration: set rising edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising Trigger.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief PVD EXTI line configuration: set rising & falling edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
-
-
-
-/**
- * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
- * @retval EXTI PVD Line Status.
- */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Clear the PVD EXTI flag.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
- * @{
- */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
- ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
- ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
- ((MODE) == PWR_PVD_MODE_NORMAL))
-
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-
-/**
- * @}
- */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/**
- * @}
- */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-/* #define HAL_PWR_ConfigPVD 12*/
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-
-
-
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
deleted file mode 100644
index f0097cb..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
+++ /dev/null
@@ -1,1378 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RCC_H
-#define __STM32F1xx_HAL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
- * @{
- */
-
-/**
- * @brief RCC PLL configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLState; /*!< PLLState: The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
- uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
- This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
-} RCC_PLLInitTypeDef;
-
-/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t ClockType; /*!< The clock to be configured.
- This parameter can be a value of @ref RCC_System_Clock_Type */
-
- uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
- This parameter can be a value of @ref RCC_System_Clock_Source */
-
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-} RCC_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
- * @{
- */
-
-#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
- * @{
- */
-#define RCC_OSCILLATORTYPE_NONE 0x00000000U
-#define RCC_OSCILLATORTYPE_HSE 0x00000001U
-#define RCC_OSCILLATORTYPE_HSI 0x00000002U
-#define RCC_OSCILLATORTYPE_LSE 0x00000004U
-#define RCC_OSCILLATORTYPE_LSI 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Config HSE Config
- * @{
- */
-#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
-#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
-#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Config LSE Config
- * @{
- */
-#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
-#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
-#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Config HSI Config
- * @{
- */
-#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
-#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-
-#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Config LSI Config
- * @{
- */
-#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
-#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Config PLL Config
- * @{
- */
-#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */
-#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
-#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
- * @{
- */
-#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
- * @{
- */
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
- * @{
- */
-#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
-/**
- * @}
- */
-
-
-/** @defgroup RCC_MCO_Index MCO Index
- * @{
- */
-#define RCC_MCO1 0x00000000U
-#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
-
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
- * @{
- */
-#define RCC_MCODIV_1 0x00000000U
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt Interrupts
- * @{
- */
-#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
-#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
-#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
-#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag Flags
- * Elements values convention: XXXYYYYYb
- * - YYYYY : Flag position in the register
- * - XXX : Register index
- * - 001: CR register
- * - 010: BDCR register
- * - 011: CSR register
- * @{
- */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
-#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CRC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
-#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
-#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
-#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
-#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
-#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
-#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
-#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USART2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_BKP_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_PWR_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-
-#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
-#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
-#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
-#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
-#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
-#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-
-#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
-#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-
-#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
-#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-
-#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
-#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
-#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
-#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-
-#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
-#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
-#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
-
-#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
-
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
- * (default is RCC_HSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 0x1F.
- */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
- (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Configuration LSI Configuration
- * @{
- */
-
-/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- */
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
-
-/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE).
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param __STATE__ specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
- * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
- */
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \
- do{ \
- if ((__STATE__) == RCC_HSE_ON) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else if ((__STATE__) == RCC_HSE_OFF) \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- else if ((__STATE__) == RCC_HSE_BYPASS) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- }while(0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE).
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param __STATE__ specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
- */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- do{ \
- if ((__STATE__) == RCC_LSE_ON) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else if ((__STATE__) == RCC_LSE_OFF) \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- else if ((__STATE__) == RCC_LSE_BYPASS) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- }while(0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
- * @{
- */
-
-/** @brief Macro to enable the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
-
-/** @brief Macro to disable the main PLL.
- * @note The main PLL can not be disabled if it is used as system clock source
- */
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-
-/** @brief Macro to configure the main PLL clock source and multiplication factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
- * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
- * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
- @if STM32F105xC
- * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
- @elseif STM32F107xC
- * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
- @else
- * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
- * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
- * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
- * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
- * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
- * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
- * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
- * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
- * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
- @endif
- * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
- * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
- *
- */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
-
-/** @brief Get oscillator clock selected as PLL input clock
- * @retval The clock source used for PLL entry. The returned value can be one
- * of the following:
- * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
- * @{
- */
-
-/**
- * @brief Macro to configure the system clock source.
- * @param __SYSCLKSOURCE__ specifies the system clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
- * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
- * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
- */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
- * @{
- */
-
-#if defined(RCC_CFGR_MCO_3)
-/** @brief Macro to configure the MCO clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
- */
-#else
-/** @brief Macro to configure the MCO clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
- */
-#endif
-
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
-
-
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
-* @{
-*/
-
-/** @brief Macro to configure the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
- * a Power On Reset (POR).
- *
- * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- */
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
-
-/** @brief Macro to get the RTC clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
- */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
-
-/** @brief Macro to enable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
-
-/** @brief Macro to disable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
-
-/** @brief Macro to force the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_BDCR register.
- */
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
-
-/** @brief Macros to release the Backup domain reset.
- */
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
-/** @brief Enable RCC interrupt.
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
- @if STM32F105xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @elsif STM32F107xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @endif
- */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt.
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
- @if STM32F105xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @elsif STM32F107xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @endif
- */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief Clear the RCC's interrupt pending bits.
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
- @if STM32F105xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @elsif STM32F107xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @endif
- * @arg @ref RCC_IT_CSS Clock Security System interrupt
- */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief Check the RCC's interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
- @if STM32F105xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @elsif STM32F107xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @endif
- * @arg @ref RCC_IT_CSS Clock Security System interrupt
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
- * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
-
-/** @brief Check RCC flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
- * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
- * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
- @if STM32F105xx
- * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
- * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
- @elsif STM32F107xx
- * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
- * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
- @endif
- * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
- * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
- * @arg @ref RCC_FLAG_PINRST Pin reset.
- * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
- * @arg @ref RCC_FLAG_SFTRST Software reset.
- * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
- * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
- * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
- ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
- RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Include RCC HAL Extension module */
-#include "stm32f1xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Exported_Functions_Group2
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-void HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Private_Constants
- * @{
- */
-
-/** @defgroup RCC_Timeout RCC Timeout
- * @{
- */
-
-/* Disable Backup domain write protection state change timeout */
-#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
-/* LSE state change timeout */
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Register_Offset Register offsets
- * @{
- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-#define RCC_CR_OFFSET 0x00U
-#define RCC_CFGR_OFFSET 0x04U
-#define RCC_CIR_OFFSET 0x08U
-#define RCC_BDCR_OFFSET 0x20U
-#define RCC_CSR_OFFSET 0x24U
-
-/**
- * @}
- */
-
-/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
- * @brief RCC registers bit address in the alias region
- * @{
- */
-#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
-#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
-#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
-#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
-#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
-
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
-#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
-/* Alias word address of HSEON bit */
-#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
-#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
-#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
-#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
-#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
-
-/* Alias word address of RMVF bit */
-#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
-#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
-
-/* --- BDCR Registers ---*/
-/* Alias word address of LSEON bit */
-#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
-#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
-
-/* Alias word address of LSEON bit */
-#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
-#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
-
-/* Alias word address of RTCEN bit */
-#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
-#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
-
-/* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
-#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
-
-/**
- * @}
- */
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
-
-/* Defines used for Flags */
-#define CR_REG_INDEX ((uint8_t)1)
-#define BDCR_REG_INDEX ((uint8_t)2)
-#define CSR_REG_INDEX ((uint8_t)3)
-
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Private_Macros
- * @{
- */
-/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
- * @{
- */
-#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-/**
- * @}
- */
-
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
- ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
- ((__HSE__) == RCC_HSE_BYPASS))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
- ((__LSE__) == RCC_LSE_BYPASS))
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
- ((__PLL__) == RCC_PLL_ON))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
- (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
- ((__HCLK__) == RCC_SYSCLK_DIV512))
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
- ((__PCLK__) == RCC_HCLK_DIV16))
-#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
deleted file mode 100644
index d0d0830..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,1908 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_rcc_ex.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RCC_EX_H
-#define __STM32F1xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCCEx
- * @{
- */
-
-/** @addtogroup RCCEx_Private_Constants
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos
-#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))
-/* Alias word address of PLL2ON bit */
-#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos
-#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))
-
-#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */
-#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-
-#define CR_REG_INDEX ((uint8_t)1)
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Private_Macros
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
- ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
-
-#else
-#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
- ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
- ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
- ((__MUL__) == RCC_PLL_MUL6_5))
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
-
-#else
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
- ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
- ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
- ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
- ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
- ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
- ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
- ((__MUL__) == RCC_PLL_MUL16))
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
-
-#endif /* STM32F105xC || STM32F107xC*/
-
-#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
- ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
-
-#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
-
-#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
-
-#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
- ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
- ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
- ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
- ((__MUL__) == RCC_PLLI2S_MUL20))
-
-#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
-
-#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
- ((__PLL__) == RCC_PLL2_ON))
-
-#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
- ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
- ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
- ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
- ((__MUL__) == RCC_PLL2_MUL20))
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
-
-#elif defined(STM32F103xE) || defined(STM32F103xG)
-
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
-
-#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
-
-
-#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
-
-#else
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-
-#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/**
- * @brief RCC PLL2 configuration structure definition
- */
-typedef struct
-{
- uint32_t PLL2State; /*!< The new state of the PLL2.
- This parameter can be a value of @ref RCCEx_PLL2_Config */
-
- uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
- This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
- This parameter can be a value of @ref RCCEx_Prediv2_Factor */
-
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_PLL2InitTypeDef;
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
- */
-typedef struct
-{
- uint32_t OscillatorType; /*!< The oscillators to be configured.
- This parameter can be a value of @ref RCC_Oscillator_Type */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t Prediv1Source; /*!< The Prediv1 source value.
- This parameter can be a value of @ref RCCEx_Prediv1_Source */
-#endif /* STM32F105xC || STM32F107xC */
-
- uint32_t HSEState; /*!< The new state of the HSE.
- This parameter can be a value of @ref RCC_HSE_Config */
-
- uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
- This parameter can be a value of @ref RCCEx_Prediv1_Factor */
-
- uint32_t LSEState; /*!< The new state of the LSE.
- This parameter can be a value of @ref RCC_LSE_Config */
-
- uint32_t HSIState; /*!< The new state of the HSI.
- This parameter can be a value of @ref RCC_HSI_Config */
-
- uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
- uint32_t LSIState; /*!< The new state of the LSI.
- This parameter can be a value of @ref RCC_LSI_Config */
-
- RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_OscInitTypeDef;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/**
- * @brief RCC PLLI2S configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
- This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
- This parameter can be a value of @ref RCCEx_Prediv2_Factor */
-
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_PLLI2SInitTypeDef;
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @brief RCC extended clocks structure definition
- */
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t AdcClockSelection; /*!< ADC clock source
- This parameter can be a value of @ref RCCEx_ADC_Prescaler */
-
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
- uint32_t I2s2ClockSelection; /*!< I2S2 clock source
- This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
-
- uint32_t I2s3ClockSelection; /*!< I2S3 clock source
- This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
- This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
-
-#endif /* STM32F105xC || STM32F107xC */
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t UsbClockSelection; /*!< USB clock source
- This parameter can be a value of @ref RCCEx_USB_Prescaler */
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-} RCC_PeriphCLKInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
- * @{
- */
-
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
- * @{
- */
-#define RCC_PERIPHCLK_RTC 0x00000001U
-#define RCC_PERIPHCLK_ADC 0x00000002U
-#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_PERIPHCLK_I2S2 0x00000004U
-#define RCC_PERIPHCLK_I2S3 0x00000008U
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_PERIPHCLK_USB 0x00000010U
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
- * @{
- */
-#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
-#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
-#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
-#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
-
-/**
- * @}
- */
-
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
- * @{
- */
-#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
- * @{
- */
-#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-
-/** @defgroup RCCEx_USB_Prescaler USB Prescaler
- * @{
- */
-#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
-#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U
-
-/**
- * @}
- */
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_USB_Prescaler USB Prescaler
- * @{
- */
-#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
-#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
- * @{
- */
-
-#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
-#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
-#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
-#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
-#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
-#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
-#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
-#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
-#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
- * @{
- */
-
-#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
-#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
- * @{
- */
-
-#define RCC_HSE_PREDIV_DIV1 0x00000000U
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
-#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
-#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
-#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
-#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
-#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
-#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
-#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
-#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
-#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
-#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
-#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
-#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
-#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
-#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
-#else
-#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
- * @{
- */
-
-#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
-#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
-#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
-#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
-#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
-#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
-#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
-#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
-#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
-#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
-#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
-#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
-#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
-#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
-#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
-#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_PLL2_Config PLL Config
- * @{
- */
-#define RCC_PLL2_NONE 0x00000000U
-#define RCC_PLL2_OFF 0x00000001U
-#define RCC_PLL2_ON 0x00000002U
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
- * @{
- */
-
-#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
-#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
-#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
-#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
-#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
-#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
-#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
-#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
-#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
-
-/**
- * @}
- */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#else
-#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
-#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
-#endif /* STM32F105xC || STM32F107xC */
-#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
-#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
-#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
-#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
-#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
-#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
-#else
-#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
-#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
-#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
-#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
-#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
-#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
-#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
- * @{
- */
-#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
-#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
-#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
-#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
-#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
-#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
-#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
-#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
-#endif /* STM32F105xC || STM32F107xC*/
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Interrupt RCCEx Interrupt
- * @{
- */
-#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
-#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Flag RCCEx Flag
- * Elements values convention: 0XXYYYYYb
- * - YYYYY : Flag position in the register
- * - XX : Register index
- * - 01: CR register
- * @{
- */
-/* Flags in the CR register */
-#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos))
-#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos))
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC*/
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
- || defined (STM32F100xE)
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined (STM32F100xE)
-#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-
-#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
-#endif /* STM32F105xC || STM32F107xC*/
-
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
-
-/**
- * @brief Enable ETHERNET clock.
- */
-#define __HAL_RCC_ETH_CLK_ENABLE() do { \
- __HAL_RCC_ETHMAC_CLK_ENABLE(); \
- __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
- __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
- } while(0U)
-/**
- * @brief Disable ETHERNET clock.
- */
-#define __HAL_RCC_ETH_CLK_DISABLE() do { \
- __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
- __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
- __HAL_RCC_ETHMAC_CLK_DISABLE(); \
- } while(0U)
-
-#endif /* STM32F107xC*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
- || defined (STM32F100xE)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined (STM32F100xE)
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
-#endif /* STM32F103xE || STM32F103xG */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
-#endif /* STM32F105xC || STM32F107xC*/
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
-#endif /* STM32F107xC*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined (STM32F100xE)
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CEC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
-#endif /* STM32F100xB || STM32F100xE */
-
-#ifdef STM32F100xE
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#endif /* STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
-#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F100xB) || defined (STM32F100xE)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
-#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
-#endif /* STM32F100xB || STM32F100xE */
-#ifdef STM32F100xE
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#endif /* STM32F100xE */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#endif /* STM32F105xC || STM32F107xC */
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
-#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
-#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
-#endif /* STM32F100xE */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
-#endif /* STM32F100xB || STM32F100xE */
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
-#endif /* STM32F103xE || STM32F103xG */
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
-#endif /* STM32F100xE */
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
- * @brief Force or release AHB peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
-#endif /* STM32F107xC */
-
-#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
-#endif /* STM32F107xC */
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-
-#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-
-#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined (STM32F100xE)
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined (STM32F100xE)
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#endif /* STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-
-#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
-
-#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
-#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
-#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
-
-#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
-#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
-#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
-
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
-
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
-#endif /* STM32F100xE */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-
-#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_HSE_Configuration HSE Configuration
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
- * @note Predivision factor can not be changed if PLL is used as system clock
- * In this case, you have to select another source of the system clock, disable the PLL and
- * then change the HSE predivision factor.
- * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
- * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
- */
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
-#else
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
- * @note Predivision factor can not be changed if PLL is used as system clock
- * In this case, you have to select another source of the system clock, disable the PLL and
- * then change the HSE predivision factor.
- * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
- * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
- */
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
- MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-/**
- * @brief Macro to get prediv1 factor for PLL.
- */
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
-
-#else
-/**
- * @brief Macro to get prediv1 factor for PLL.
- */
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
-
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
- * @{
- */
-
-/** @brief Macros to enable the main PLLI2S.
- * @note After enabling the main PLLI2S, the application software should wait on
- * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
- * be used as system clock source.
- * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
-
-/** @brief Macros to disable the main PLLI2S.
- * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
-
-/** @brief macros to configure the main PLLI2S multiplication factor.
- * @note This function must be used only when the main PLLI2S is disabled.
- *
- * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
- * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
- * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
- * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
- * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
- * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
- * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
- * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
- * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
- *
- */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
-
-/**
- * @}
- */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
- * @brief Macros to configure clock source of different peripherals.
- * @{
- */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-/** @brief Macro to configure the USB clock.
- * @param __USBCLKSOURCE__ specifies the USB clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
- */
-#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
-
-/** @brief Macro to get the USB clock (USBCLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
- */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @brief Macro to configure the USB OTSclock.
- * @param __USBCLKSOURCE__ specifies the USB clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
- */
-#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
-
-/** @brief Macro to get the USB clock (USBCLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
- */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
- * @param __ADCCLKSOURCE__ specifies the ADC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
- */
-#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
-
-/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
- */
-#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @addtogroup RCCEx_HSE_Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
- * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
- * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
- * then change the PREDIV2 factor.
- * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
- * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
- */
-#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
-
-/**
- * @brief Macro to get prediv2 factor for PLL2 & PLL3.
- */
-#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_PLLI2S_Configuration
- * @{
- */
-
-/** @brief Macros to enable the main PLL2.
- * @note After enabling the main PLL2, the application software should wait on
- * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
- * be used as system clock source.
- * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
-
-/** @brief Macros to disable the main PLL2.
- * @note The main PLL2 can not be disabled if it is used indirectly as system clock source
- * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
-
-/** @brief macros to configure the main PLL2 multiplication factor.
- * @note This function must be used only when the main PLL2 is disabled.
- *
- * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
- * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
- * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
- * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
- * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
- * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
- * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
- * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
- * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
- *
- */
-#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S_Configuration I2S Configuration
- * @brief Macros to configure clock source of I2S peripherals.
- * @{
- */
-
-/** @brief Macro to configure the I2S2 clock.
- * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
- * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
- */
-#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
-
-/** @brief Macro to get the I2S2 clock (I2S2CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
- * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
- */
-#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
-
-/** @brief Macro to configure the I2S3 clock.
- * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
- * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
- */
-#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
-
-/** @brief Macro to get the I2S3 clock (I2S3CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
- * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
- */
-#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
-
-/**
- * @}
- */
-
-#endif /* STM32F105xC || STM32F107xC */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @addtogroup RCCEx_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group3
- * @{
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h
deleted file mode 100644
index 49f223c..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h
+++ /dev/null
@@ -1,731 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F1xx_HAL_SPI_H
-#define STM32F1xx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
- * @{
- */
-
-/**
- * @brief SPI Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_Mode */
-
- uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
- This parameter can be a value of @ref SPI_Direction */
-
- uint32_t DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_Data_Size */
-
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
- This parameter can be a value of @ref SPI_TI_mode */
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_CRC_Calculation */
-
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
-} SPI_InitTypeDef;
-
-/**
- * @brief HAL SPI State structure definition
- */
-typedef enum
-{
- HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
- HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
-} HAL_SPI_StateTypeDef;
-
-/**
- * @brief SPI handle Structure definition
- */
-typedef struct __SPI_HandleTypeDef
-{
- SPI_TypeDef *Instance; /*!< SPI registers base address */
-
- SPI_InitTypeDef Init; /*!< SPI communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SPI Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SPI Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
-
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
-
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
-
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
-
- __IO uint32_t ErrorCode; /*!< SPI Error code */
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
- void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
- void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
- void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
- void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
- void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
- void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
- void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
- void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
- void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-} SPI_HandleTypeDef;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
- * @brief HAL SPI Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
- HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
- HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
- HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
- HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
- HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
- HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
- HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
- HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
- HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
-
-} HAL_SPI_CallbackIDTypeDef;
-
-/**
- * @brief HAL SPI Callback pointer definition
- */
-typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_Error_Code SPI Error Code
- * @{
- */
-#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
-#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
-#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
-#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */
-#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup SPI_Mode SPI Mode
- * @{
- */
-#define SPI_MODE_SLAVE (0x00000000U)
-#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
- * @}
- */
-
-/** @defgroup SPI_Direction SPI Direction Mode
- * @{
- */
-#define SPI_DIRECTION_2LINES (0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
-/**
- * @}
- */
-
-/** @defgroup SPI_Data_Size SPI Data Size
- * @{
- */
-#define SPI_DATASIZE_8BIT (0x00000000U)
-#define SPI_DATASIZE_16BIT SPI_CR1_DFF
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
- * @{
- */
-#define SPI_POLARITY_LOW (0x00000000U)
-#define SPI_POLARITY_HIGH SPI_CR1_CPOL
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
- * @{
- */
-#define SPI_PHASE_1EDGE (0x00000000U)
-#define SPI_PHASE_2EDGE SPI_CR1_CPHA
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
- * @{
- */
-#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
- * @{
- */
-#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
- * @{
- */
-#define SPI_FIRSTBIT_MSB (0x00000000U)
-#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
-/**
- * @}
- */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
- * @{
- */
-#define SPI_TIMODE_DISABLE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
- * @{
- */
-#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
-/**
- * @}
- */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
- * @{
- */
-#define SPI_IT_TXE SPI_CR2_TXEIE
-#define SPI_IT_RXNE SPI_CR2_RXNEIE
-#define SPI_IT_ERR SPI_CR2_ERRIE
-/**
- * @}
- */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
- * @{
- */
-#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
-#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\
- | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @brief Reset SPI handle state.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
-/** @brief Enable the specified SPI interrupts.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Disable the specified SPI interrupts.
- * @param __HANDLE__ specifies the SPI handle.
- * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Check whether the specified SPI interrupt source is enabled or not.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
- & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF: Mode fault flag
- * @arg SPI_FLAG_OVR: Overrun flag
- * @arg SPI_FLAG_BSY: Busy flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the SPI CRCERR pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief Clear the SPI MODF pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_modf = 0x00U; \
- tmpreg_modf = (__HANDLE__)->Instance->SR; \
- CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
- UNUSED(tmpreg_modf); \
- } while(0U)
-
-/** @brief Clear the SPI OVR pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
- } while(0U)
-
-/** @brief Enable the SPI peripheral.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief Disable the SPI peripheral.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
- * @{
- */
-#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
-#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
- * @{
- */
-
-/** @brief Set the SPI transmit-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief Set the SPI receive-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief Reset the CRC calculation of the SPI.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __SR__ copy of SPI SR register.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF: Mode fault flag
- * @arg SPI_FLAG_OVR: Overrun flag
- * @arg SPI_FLAG_BSY: Busy flag
- * @retval SET or RESET.
- */
-#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
- ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
-
-/** @brief Check whether the specified SPI Interrupt is set or not.
- * @param __CR2__ copy of SPI CR2 register.
- * @param __INTERRUPT__ specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval SET or RESET.
- */
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
- (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks if SPI Mode parameter is in allowed range.
- * @param __MODE__ specifies the SPI Mode.
- * This parameter can be a value of @ref SPI_Mode
- * @retval None
- */
-#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
- ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief Checks if SPI Direction Mode parameter is in allowed range.
- * @param __MODE__ specifies the SPI Direction Mode.
- * This parameter can be a value of @ref SPI_Direction
- * @retval None
- */
-#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
- ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief Checks if SPI Direction Mode parameter is 2 lines.
- * @param __MODE__ specifies the SPI Direction Mode.
- * @retval None
- */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
- * @param __MODE__ specifies the SPI Direction Mode.
- * @retval None
- */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
- ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief Checks if SPI Data Size parameter is in allowed range.
- * @param __DATASIZE__ specifies the SPI Data Size.
- * This parameter can be a value of @ref SPI_Data_Size
- * @retval None
- */
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_8BIT))
-
-/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
- * @param __CPOL__ specifies the SPI serial clock steady state.
- * This parameter can be a value of @ref SPI_Clock_Polarity
- * @retval None
- */
-#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
- ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief Checks if SPI Clock Phase parameter is in allowed range.
- * @param __CPHA__ specifies the SPI Clock Phase.
- * This parameter can be a value of @ref SPI_Clock_Phase
- * @retval None
- */
-#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
- ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief Checks if SPI Slave Select parameter is in allowed range.
- * @param __NSS__ specifies the SPI Slave Select management parameter.
- * This parameter can be a value of @ref SPI_Slave_Select_management
- * @retval None
- */
-#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
- ((__NSS__) == SPI_NSS_HARD_INPUT) || \
- ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
- * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
- * This parameter can be a value of @ref SPI_BaudRate_Prescaler
- * @retval None
- */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
- * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
- * This parameter can be a value of @ref SPI_MSB_LSB_transmission
- * @retval None
- */
-#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
- ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-/** @brief Checks if SPI TI mode parameter is disabled.
- * @param __MODE__ SPI_TIMODE_DISABLE. Device not support Ti Mode.
- * This parameter can be a value of @ref SPI_TI_mode
- * @retval None
- */
-#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
-
-/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
- * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
- * This parameter can be a value of @ref SPI_CRC_Calculation
- * @retval None
- */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
- ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
- * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
- * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
- * @retval None
- */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
- ((__POLYNOMIAL__) <= 0xFFFFU) && \
- (((__POLYNOMIAL__)&0x1U) != 0U))
-
-/** @brief Checks if DMA handle is valid.
- * @param __HANDLE__ specifies a DMA Handle.
- * @retval None
- */
-#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
- * @{
- */
-uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F1xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
deleted file mode 100644
index f06ca5c..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
+++ /dev/null
@@ -1,2123 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F1xx_HAL_TIM_H
-#define STM32F1xx_HAL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
- * @{
- */
-
-/**
- * @brief TIM Time base Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_ClockDivision */
-
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
- This parameter can be a value of @ref TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
- * @brief TIM Output Compare Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
- This parameter can be a value of @ref TIM_Output_Fast_State
- @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-} TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM One Pulse Mode Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-/**
- * @brief TIM Input Capture Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
- * @brief TIM Encoder Configuration Structure definition
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Mode */
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
- uint32_t IC1Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
- uint32_t IC2Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-/**
- * @brief Clock Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClockSource; /*!< TIM clock sources
- This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
- This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
- This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClockConfigTypeDef;
-
-/**
- * @brief TIM Clear Input Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClearInputState; /*!< TIM clear Input state
- This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref TIM_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
- This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClearInputConfigTypeDef;
-
-/**
- * @brief TIM Master configuration Structure definition
- */
-typedef struct
-{
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode
- @note When the Master/slave mode is enabled, the effect of
- an event on the trigger input (TRGI) is delayed to allow a
- perfect synchronization between the current timer and its
- slaves (through TRGO). It is not mandatory in case of timer
- synchronization mode. */
-} TIM_MasterConfigTypeDef;
-
-/**
- * @brief TIM Slave configuration Structure definition
- */
-typedef struct
-{
- uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
- uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
- uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
- uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-} TIM_SlaveConfigTypeDef;
-
-/**
- * @brief TIM Break input(s) and Dead time configuration Structure definition
- * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
- * filter and polarity.
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t BreakFilter; /*!< Specifies the break input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-} HAL_TIM_StateTypeDef;
-
-/**
- * @brief TIM Channel States definition
- */
-typedef enum
-{
- HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
- HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
- HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
-} HAL_TIM_ChannelStateTypeDef;
-
-/**
- * @brief DMA Burst States definition
- */
-typedef enum
-{
- HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
- HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
- HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
-} HAL_TIM_DMABurstStateTypeDef;
-
-/**
- * @brief HAL Active channel structures definition
- */
-typedef enum
-{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-} HAL_TIM_ActiveChannel;
-
-/**
- * @brief TIM Time Base Handle Structure definition
- */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-typedef struct __TIM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
- __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
- __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
- __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
- void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
- void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
- void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
- void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
- void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
- void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
- void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
- void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
- void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
- void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
- void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
- void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
- void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
- void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
- void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
- void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
- void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
- void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
- void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
- void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
- void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
- void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
- void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
- void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
- void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
- void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-} TIM_HandleTypeDef;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL TIM Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
- , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
- , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
- , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
-} HAL_TIM_CallbackIDTypeDef;
-
-/**
- * @brief HAL TIM Callback pointer definition
- */
-typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
-
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
-#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
- * @{
- */
-#define TIM_DMABASE_CR1 0x00000000U
-#define TIM_DMABASE_CR2 0x00000001U
-#define TIM_DMABASE_SMCR 0x00000002U
-#define TIM_DMABASE_DIER 0x00000003U
-#define TIM_DMABASE_SR 0x00000004U
-#define TIM_DMABASE_EGR 0x00000005U
-#define TIM_DMABASE_CCMR1 0x00000006U
-#define TIM_DMABASE_CCMR2 0x00000007U
-#define TIM_DMABASE_CCER 0x00000008U
-#define TIM_DMABASE_CNT 0x00000009U
-#define TIM_DMABASE_PSC 0x0000000AU
-#define TIM_DMABASE_ARR 0x0000000BU
-#define TIM_DMABASE_RCR 0x0000000CU
-#define TIM_DMABASE_CCR1 0x0000000DU
-#define TIM_DMABASE_CCR2 0x0000000EU
-#define TIM_DMABASE_CCR3 0x0000000FU
-#define TIM_DMABASE_CCR4 0x00000010U
-#define TIM_DMABASE_BDTR 0x00000011U
-#define TIM_DMABASE_DCR 0x00000012U
-#define TIM_DMABASE_DMAR 0x00000013U
-/**
- * @}
- */
-
-/** @defgroup TIM_Event_Source TIM Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
- * @{
- */
-#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
- * @{
- */
-#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
- * @{
- */
-#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
- * @{
- */
-#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
- * @{
- */
-#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
-#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
-#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
- * @{
- */
-#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
-#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
- * @{
- */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
- * @{
- */
-#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
-#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
- * @{
- */
-#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
-#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
- * @{
- */
-#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
-#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
- * @{
- */
-#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
-#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
- * @{
- */
-#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
-#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
- * @{
- */
-#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
-#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
- * @{
- */
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
- * @{
- */
-#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
-#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
- * @{
- */
-#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
- * @{
- */
-#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
- * @{
- */
-#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
-#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
- * @{
- */
-#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
-/**
- * @}
- */
-
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
- * @{
- */
-#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
-#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
-#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
-#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
-#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
-#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
-#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
-#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
-/**
- * @}
- */
-
-/** @defgroup TIM_Commutation_Source TIM Commutation Source
- * @{
- */
-#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
-#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
- * @{
- */
-#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
-#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
-#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
-#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
-#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
-#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
-#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
-/**
- * @}
- */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
- * @{
- */
-#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
-#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
-#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
-#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
-#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
-#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
-#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
-#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
-#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
-#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
-#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
-#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel TIM Channel
- * @{
- */
-#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
-#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
-#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
-#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
-#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
- * @{
- */
-#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
-#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
-#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
-#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
-#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
-#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
-#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
-#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
-#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
- * @{
- */
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
- * @{
- */
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
- * @{
- */
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
- * @{
- */
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
- * @{
- */
-#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
-#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
- * @{
- */
-#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
-#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
-/**
- * @}
- */
-/** @defgroup TIM_Lock_level TIM Lock level
- * @{
- */
-#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
-#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
-#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
-#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
- * @{
- */
-#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
-#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
- * @{
- */
-#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
-#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
- * @{
- */
-#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
- (if none of the break inputs BRK and BRK2 is active) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
- * @{
- */
-#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
-#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
-#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
-#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
- * @{
- */
-#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
-#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode TIM Slave mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
-#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
-#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
-#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
-#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
- * @{
- */
-#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
-#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
-#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
-#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
-#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
-#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
-#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
-#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
- * @{
- */
-#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
-#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
-#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
-#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
-#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
-#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
-#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
-#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
-#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
- * @{
- */
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
- * @{
- */
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
- * @{
- */
-#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
-#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
- * @{
- */
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-/**
- * @}
- */
-
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
- * @{
- */
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
- * @}
- */
-
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
- * @{
- */
-#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
-#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
-#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
-#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @brief Reset TIM handle state.
- * @param __HANDLE__ TIM handle.
- * @retval None
- */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
- (__HANDLE__)->Base_MspInitCallback = NULL; \
- (__HANDLE__)->Base_MspDeInitCallback = NULL; \
- (__HANDLE__)->IC_MspInitCallback = NULL; \
- (__HANDLE__)->IC_MspDeInitCallback = NULL; \
- (__HANDLE__)->OC_MspInitCallback = NULL; \
- (__HANDLE__)->OC_MspDeInitCallback = NULL; \
- (__HANDLE__)->PWM_MspInitCallback = NULL; \
- (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
- } while(0)
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
- * @brief Enable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/**
- * @brief Disable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
- */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled unconditionally
- */
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
-
-/** @brief Enable the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/** @brief Disable the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/** @brief Enable the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to enable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/** @brief Disable the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to disable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/** @brief Check whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified TIM interrupt flag.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to clear.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
- * @brief Check whether the specified TIM interrupt source is enabled or not.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval The state of TIM_IT (SET or RESET).
- */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
- == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clear the TIM interrupt pending bits.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
- * @brief Indicates whether or not the TIM Counter is used as downcounter.
- * @param __HANDLE__ TIM handle.
- * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
- */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
- * @brief Set the TIM Prescaler on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __PRESC__ specifies the Prescaler new value.
- * @retval None
- */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
- * @brief Set the TIM Counter Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __COUNTER__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
- * @brief Get the TIM Counter Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
- */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
-
-/**
- * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __AUTORELOAD__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
-
-/**
- * @brief Get the TIM Autoreload Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
- */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
-
-/**
- * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __CKD__ specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- * @retval None
- */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
-
-/**
- * @brief Get the TIM Clock Division value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval The clock division can be one of the following values:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
-
-/**
- * @brief Get the TIM Input Capture prescaler on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
- * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
- * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
- * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval The input capture prescaler can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-
-/**
- * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
-
-/**
- * @brief Get the TIM Capture Compare Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__HANDLE__)->Instance->CCR4))
-
-/**
- * @brief Set the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
-
-/**
- * @brief Reset the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
-
-/**
- * @brief Enable fast mode for a given channel.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @note When fast mode is enabled an active edge on the trigger input acts
- * like a compare match on CCx output. Delay to sample the trigger
- * input and to activate CCx output is reduced to 3 clock cycles.
- * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
-
-/**
- * @brief Disable fast mode for a given channel.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @note When fast mode is disabled CCx output behaves normally depending
- * on counter and CCRx values even when the trigger is ON. The minimum
- * delay to activate CCx output when an active edge occurs on the
- * trigger input is 5 clock cycles.
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
-
-/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__ TIM handle.
- * @note When the URS bit of the TIMx_CR1 register is set, only counter
- * overflow/underflow generates an update interrupt or DMA request (if
- * enabled)
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
-
-/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__ TIM handle.
- * @note When the URS bit of the TIMx_CR1 register is reset, any of the
- * following events generate an update interrupt or DMA request (if
- * enabled):
- * _ Counter overflow underflow
- * _ Setting the UG bit
- * _ Update generation through the slave mode controller
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
-
-/**
- * @brief Set the TIM Capture x input polarity on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__ Polarity for TIx source
- * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
- * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
- * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @retval None
- */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
-
-/**
- * @}
- */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
- ((__BASE__) == TIM_DMABASE_CR2) || \
- ((__BASE__) == TIM_DMABASE_SMCR) || \
- ((__BASE__) == TIM_DMABASE_DIER) || \
- ((__BASE__) == TIM_DMABASE_SR) || \
- ((__BASE__) == TIM_DMABASE_EGR) || \
- ((__BASE__) == TIM_DMABASE_CCMR1) || \
- ((__BASE__) == TIM_DMABASE_CCMR2) || \
- ((__BASE__) == TIM_DMABASE_CCER) || \
- ((__BASE__) == TIM_DMABASE_CNT) || \
- ((__BASE__) == TIM_DMABASE_PSC) || \
- ((__BASE__) == TIM_DMABASE_ARR) || \
- ((__BASE__) == TIM_DMABASE_RCR) || \
- ((__BASE__) == TIM_DMABASE_CCR1) || \
- ((__BASE__) == TIM_DMABASE_CCR2) || \
- ((__BASE__) == TIM_DMABASE_CCR3) || \
- ((__BASE__) == TIM_DMABASE_CCR4) || \
- ((__BASE__) == TIM_DMABASE_BDTR))
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
- ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
- ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
- ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
- ((__MODE__) == TIM_ENCODERMODE_TI2) || \
- ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3) || \
- ((__CHANNEL__) == TIM_CHANNEL_4) || \
- ((__CHANNEL__) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3))
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
- ((__STATE__) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
- ((__STATE__) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
-
-#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
- ((__STATE__) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
- ((__SOURCE__) == TIM_TRGO_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO_UPDATE) || \
- ((__SOURCE__) == TIM_TRGO_OC1) || \
- ((__SOURCE__) == TIM_TRGO_OC1REF) || \
- ((__SOURCE__) == TIM_TRGO_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
- ((__MODE__) == TIM_SLAVEMODE_RESET) || \
- ((__MODE__) == TIM_SLAVEMODE_GATED) || \
- ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
- ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
- ((__MODE__) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
- ((__MODE__) == TIM_OCMODE_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_INACTIVE) || \
- ((__MODE__) == TIM_OCMODE_TOGGLE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
- ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
-
-#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
-
-#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
- ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
-
-#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
- (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
- (__HANDLE__)->ChannelState[3])
-
-#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
- ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
- } while(0)
-
-#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
- (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
- (__HANDLE__)->ChannelNState[3])
-
-#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
- ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
- } while(0)
-
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32f1xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- * @{
- */
-/* Timer Output Compare functions *********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- * @{
- */
-/* Timer PWM functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- * @{
- */
-/* Timer Input Capture functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- * @{
- */
-/* Timer One Pulse functions **************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- * @{
- */
-/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
- uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- * @{
- */
-/* Interrupt Handler functions ***********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
- uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
- uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
- uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- * @{
- */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
- pTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief Peripheral State functions
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/* Peripheral Channel state functions ************************************************/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-void TIM_ResetCallback(TIM_HandleTypeDef *htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F1xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
deleted file mode 100644
index 6f1b5e5..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_tim_ex.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F1xx_HAL_TIM_EX_H
-#define STM32F1xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIMEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
- * @{
- */
-
-/**
- * @brief TIM Hall sensor Configuration Structure definition
- */
-
-typedef struct
-{
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-} TIM_HallSensor_InitTypeDef;
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
- * @{
- */
-
-/** @defgroup TIMEx_Remap TIM Extended Remapping
- * @{
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-/* End of exported macro -----------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
- * @{
- */
-
-/**
- * @}
- */
-/* End of private macro ------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- * @{
- */
-/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- * @{
- */
-/* Timer Complementary Output Compare functions *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- * @{
- */
-/* Timer Complementary PWM functions ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- * @{
- */
-/* Timer Complementary One Pulse functions **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- * @{
- */
-/* Extended Callback **********************************************************/
-void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- * @{
- */
-/* Extended Peripheral State functions ***************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
- * @{
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F1xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h
new file mode 100644
index 0000000..e17f1af
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h
@@ -0,0 +1,1015 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_bus.h
+ * @author MCD Application Team
+ * @brief Header file of BUS LL module.
+
+ @verbatim
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_BUS_H
+#define __STM32F1xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+#if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
+#define RCC_AHBRSTR_SUPPORT
+#endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+ * @{
+ */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
+#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
+#if defined(DMA2)
+#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
+#endif /*DMA2*/
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
+#endif /*ETH*/
+#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
+#if defined(FSMC_Bank1)
+#define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
+#endif /*FSMC_Bank1*/
+#if defined(USB_OTG_FS)
+#define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
+#endif /*USB_OTG_FS*/
+#if defined(SDIO)
+#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
+#endif /*SDIO*/
+#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
+#if defined(CAN1)
+#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
+#endif /*CAN1*/
+#if defined(CAN2)
+#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
+#endif /*CAN2*/
+#if defined(CEC)
+#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
+#endif /*CEC*/
+#if defined(DAC)
+#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
+#endif /*DAC*/
+#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
+#if defined(I2C2)
+#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
+#endif /*I2C2*/
+#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
+#endif /*SPI2*/
+#if defined(SPI3)
+#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
+#endif /*SPI3*/
+#if defined(TIM12)
+#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
+#endif /*TIM12*/
+#if defined(TIM13)
+#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
+#endif /*TIM13*/
+#if defined(TIM14)
+#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
+#endif /*TIM14*/
+#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
+#endif /*TIM4*/
+#if defined(TIM5)
+#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
+#endif /*TIM5*/
+#if defined(TIM6)
+#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
+#endif /*TIM6*/
+#if defined(TIM7)
+#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
+#endif /*TIM7*/
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
+#endif /*UART4*/
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
+#endif /*UART5*/
+#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
+#if defined(USART3)
+#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
+#endif /*USART3*/
+#if defined(USB)
+#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
+#endif /*USB*/
+#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
+#if defined(ADC2)
+#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
+#endif /*ADC2*/
+#if defined(ADC3)
+#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
+#endif /*ADC3*/
+#define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
+#define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
+#define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
+#define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
+#define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
+#if defined(GPIOE)
+#define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
+#endif /*GPIOE*/
+#if defined(GPIOF)
+#define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
+#endif /*GPIOF*/
+#if defined(GPIOG)
+#define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
+#endif /*GPIOG*/
+#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
+#if defined(TIM10)
+#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
+#endif /*TIM10*/
+#if defined(TIM11)
+#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
+#endif /*TIM11*/
+#if defined(TIM15)
+#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
+#endif /*TIM15*/
+#if defined(TIM16)
+#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
+#endif /*TIM16*/
+#if defined(TIM17)
+#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
+#endif /*TIM17*/
+#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
+#endif /*TIM8*/
+#if defined(TIM9)
+#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
+#endif /*TIM9*/
+#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ * @{
+ */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+ * @{
+ */
+
+/**
+ * @brief Enable AHB1 peripherals clock.
+ * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHBENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clock is enabled or not
+ * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable AHB1 peripherals clock.
+ * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHBENR, Periphs);
+}
+
+#if defined(RCC_AHBRSTR_SUPPORT)
+/**
+ * @brief Force AHB1 peripherals reset.
+ * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHBRSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB1 peripherals reset.
+ * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHBRSTR, Periphs);
+}
+#endif /* RCC_AHBRSTR_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+ * @{
+ */
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+ * @{
+ */
+
+/**
+ * @brief Enable APB2 peripherals clock.
+ * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB2 peripheral clock is enabled or not
+ * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+ * @brief Force APB2 peripherals reset.
+ * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB2 peripherals reset.
+ * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h
new file mode 100644
index 0000000..7baf2ac
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h
@@ -0,0 +1,640 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL CORTEX driver contains a set of generic APIs that can be
+ used by user:
+ (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+ functions
+ (+) Low power mode configuration (SCB register of Cortex-MCU)
+ (+) MPU API to configure and enable regions
+ (MPU services provided only on some devices)
+ (+) API to access to MCU info (CPUID register)
+ (+) API to enable fault handler (SHCSR accesses)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_CORTEX_H
+#define __STM32F1xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+ * @{
+ */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+ * @{
+ */
+#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+ * @{
+ */
+#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+ * @{
+ */
+#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+ * @{
+ */
+#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+ * @{
+ */
+
+/**
+ * @brief This function checks if the Systick counter flag is active or not.
+ * @note It can be used in timeout function on application side.
+ * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+ return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+ * @brief Configures the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+ if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+ {
+ SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+ else
+ {
+ CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+}
+
+/**
+ * @brief Get the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+ return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+ * @brief Enable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Disable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Checks if the SYSTICK interrupt is enabled or disabled.
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+ return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+ * @{
+ */
+
+/**
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Processor uses deep sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
+ * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+ * empty main application.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Do not sleep when returning to Thread mode.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
+ * processor.
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+ /* Set SEVEONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+ * excluded
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+ /* Clear SEVEONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+ * @{
+ */
+
+/**
+ * @brief Enable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+ /* Enable the system handler fault */
+ SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @brief Disable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+ /* Disable the system handler fault */
+ CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+ * @{
+ */
+
+/**
+ * @brief Get Implementer code
+ * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
+ * @retval Value should be equal to 0x41 for ARM
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+ * @brief Get Variant number (The r value in the rnpn product revision identifier)
+ * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
+ * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+ * @brief Get Constant number
+ * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
+ * @retval Value should be equal to 0xF for Cortex-M3 devices
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+ * @brief Get Part number
+ * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
+ * @retval Value should be equal to 0xC23 for Cortex-M3
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+ * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+ * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
+ * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param Options This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+ /* Enable the MPU*/
+ WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+ /* Ensure MPU settings take effects */
+ __DSB();
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+ return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Enable the MPU region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Configure and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RASR XN LL_MPU_ConfigRegion\n
+ * MPU_RASR AP LL_MPU_ConfigRegion\n
+ * MPU_RASR S LL_MPU_ConfigRegion\n
+ * MPU_RASR C LL_MPU_ConfigRegion\n
+ * MPU_RASR B LL_MPU_ConfigRegion\n
+ * MPU_RASR SIZE LL_MPU_ConfigRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Address Value of region base address
+ * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+ * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+ * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+ * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+ * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+ * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+ * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+ * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+ * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+ * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+ * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+ /* Configure MPU */
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+ * @brief Disable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * MPU_RASR ENABLE LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h
new file mode 100644
index 0000000..9ebff4e
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h
@@ -0,0 +1,1960 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_DMA_H
+#define __STM32F1xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+ * @{
+ */
+/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] =
+{
+ (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+};
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
+ or as Source base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
+ or as Destination base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref DMA_LL_EC_MODE
+ @note: The circular buffer mode cannot be used if the memory to memory
+ data transfer direction is configured on the selected Channel
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set in PeripheralSize
+ or MemorySize parameters depending in the transfer direction.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+ uint32_t Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ * @{
+ */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_WriteReg function
+ * @{
+ */
+#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
+#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
+#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
+#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
+#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
+#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
+#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
+#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_ReadReg function
+ * @{
+ */
+#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
+#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
+#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
+#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
+#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
+#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
+#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
+#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
+ * @{
+ */
+#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
+#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ * @{
+ */
+#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+ * @{
+ */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+ * @{
+ */
+#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
+#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+ * @{
+ */
+#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+ * @{
+ */
+#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
+#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+ * @{
+ */
+#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
+#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+ * @{
+ */
+#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
+#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+ * @{
+ */
+#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
+#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
+#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
+#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+ * @{
+ */
+
+/**
+ * @brief Convert DMAx_Channely into DMAx
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval DMAx
+ */
+#if defined(DMA2)
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
+#else
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
+#endif
+
+/**
+ * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval LL_DMA_CHANNEL_y
+ */
+#if defined (DMA2)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+
+/**
+ * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+ * @param __DMA_INSTANCE__ DMAx
+ * @param __CHANNEL__ LL_DMA_CHANNEL_y
+ * @retval DMAx_Channely
+ */
+#if defined (DMA2)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable DMA channel.
+ * @rmtoll CCR EN LL_DMA_EnableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Disable DMA channel.
+ * @rmtoll CCR EN LL_DMA_DisableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Check if DMA channel is enabled or disabled.
+ * @rmtoll CCR EN LL_DMA_IsEnabledChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_EN) == (DMA_CCR_EN));
+}
+
+/**
+ * @brief Configure all parameters link to DMA transfer.
+ * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
+ * CCR MEM2MEM LL_DMA_ConfigTransfer\n
+ * CCR CIRC LL_DMA_ConfigTransfer\n
+ * CCR PINC LL_DMA_ConfigTransfer\n
+ * CCR MINC LL_DMA_ConfigTransfer\n
+ * CCR PSIZE LL_DMA_ConfigTransfer\n
+ * CCR MSIZE LL_DMA_ConfigTransfer\n
+ * CCR PL LL_DMA_ConfigTransfer
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+ * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+ * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+ Configuration);
+}
+
+/**
+ * @brief Set Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_SetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+ * @brief Get Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_GetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+ * @brief Set DMA mode circular or normal.
+ * @note The circular buffer mode cannot be used if the memory-to-memory
+ * data transfer is configured on the selected Channel.
+ * @rmtoll CCR CIRC LL_DMA_SetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ Mode);
+}
+
+/**
+ * @brief Get DMA mode circular or normal.
+ * @rmtoll CCR CIRC LL_DMA_GetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_CIRC));
+}
+
+/**
+ * @brief Set Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ PeriphOrM2MSrcIncMode);
+}
+
+/**
+ * @brief Get Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PINC));
+}
+
+/**
+ * @brief Set Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ MemoryOrM2MDstIncMode);
+}
+
+/**
+ * @brief Get Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_MINC));
+}
+
+/**
+ * @brief Set Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+ PeriphOrM2MSrcDataSize);
+}
+
+/**
+ * @brief Get Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PSIZE));
+}
+
+/**
+ * @brief Set Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+ MemoryOrM2MDstDataSize);
+}
+
+/**
+ * @brief Get Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_MSIZE));
+}
+
+/**
+ * @brief Set Channel priority level.
+ * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Priority This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ Priority);
+}
+
+/**
+ * @brief Get Channel priority level.
+ * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PL));
+}
+
+/**
+ * @brief Set Number of data to transfer.
+ * @note This action has no effect if
+ * channel is enabled.
+ * @rmtoll CNDTR NDT LL_DMA_SetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ DMA_CNDTR_NDT, NbData);
+}
+
+/**
+ * @brief Get Number of data to transfer.
+ * @note Once the channel is enabled, the return value indicate the
+ * remaining bytes to be transmitted.
+ * @rmtoll CNDTR NDT LL_DMA_GetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ DMA_CNDTR_NDT));
+}
+
+/**
+ * @brief Configure the Source and Destination addresses.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
+ * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
+ * CMAR MA LL_DMA_ConfigAddresses
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t Direction)
+{
+ /* Direction Memory to Periph */
+ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+ {
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
+ }
+ /* Direction Periph to Memory and Memory to Memory */
+ else
+ {
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
+ }
+}
+
+/**
+ * @brief Set the Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
+}
+
+/**
+ * @brief Get Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+}
+
+/**
+ * @brief Get Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+}
+
+/**
+ * @brief Set the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+}
+
+/**
+ * @brief Get the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+}
+
+/**
+ * @brief Get the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Channel 1 global interrupt flag.
+ * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
+}
+
+/**
+ * @brief Get Channel 2 global interrupt flag.
+ * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
+}
+
+/**
+ * @brief Get Channel 3 global interrupt flag.
+ * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
+}
+
+/**
+ * @brief Get Channel 4 global interrupt flag.
+ * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
+}
+
+/**
+ * @brief Get Channel 5 global interrupt flag.
+ * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
+}
+
+/**
+ * @brief Get Channel 6 global interrupt flag.
+ * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
+}
+
+/**
+ * @brief Get Channel 7 global interrupt flag.
+ * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
+}
+
+/**
+ * @brief Get Channel 1 transfer complete flag.
+ * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
+}
+
+/**
+ * @brief Get Channel 2 transfer complete flag.
+ * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
+}
+
+/**
+ * @brief Get Channel 3 transfer complete flag.
+ * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
+}
+
+/**
+ * @brief Get Channel 4 transfer complete flag.
+ * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
+}
+
+/**
+ * @brief Get Channel 5 transfer complete flag.
+ * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
+}
+
+/**
+ * @brief Get Channel 6 transfer complete flag.
+ * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
+}
+
+/**
+ * @brief Get Channel 7 transfer complete flag.
+ * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
+}
+
+/**
+ * @brief Get Channel 1 half transfer flag.
+ * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
+}
+
+/**
+ * @brief Get Channel 2 half transfer flag.
+ * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
+}
+
+/**
+ * @brief Get Channel 3 half transfer flag.
+ * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
+}
+
+/**
+ * @brief Get Channel 4 half transfer flag.
+ * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
+}
+
+/**
+ * @brief Get Channel 5 half transfer flag.
+ * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
+}
+
+/**
+ * @brief Get Channel 6 half transfer flag.
+ * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
+}
+
+/**
+ * @brief Get Channel 7 half transfer flag.
+ * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
+}
+
+/**
+ * @brief Get Channel 1 transfer error flag.
+ * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
+}
+
+/**
+ * @brief Get Channel 2 transfer error flag.
+ * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
+}
+
+/**
+ * @brief Get Channel 3 transfer error flag.
+ * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
+}
+
+/**
+ * @brief Get Channel 4 transfer error flag.
+ * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
+}
+
+/**
+ * @brief Get Channel 5 transfer error flag.
+ * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
+}
+
+/**
+ * @brief Get Channel 6 transfer error flag.
+ * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
+}
+
+/**
+ * @brief Get Channel 7 transfer error flag.
+ * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
+}
+
+/**
+ * @brief Clear Channel 1 global interrupt flag.
+ * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+ * @brief Clear Channel 2 global interrupt flag.
+ * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+ * @brief Clear Channel 3 global interrupt flag.
+ * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+ * @brief Clear Channel 4 global interrupt flag.
+ * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+ * @brief Clear Channel 5 global interrupt flag.
+ * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+/**
+ * @brief Clear Channel 6 global interrupt flag.
+ * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+
+/**
+ * @brief Clear Channel 7 global interrupt flag.
+ * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer complete flag.
+ * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer complete flag.
+ * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer complete flag.
+ * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer complete flag.
+ * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer complete flag.
+ * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer complete flag.
+ * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer complete flag.
+ * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+
+/**
+ * @brief Clear Channel 1 half transfer flag.
+ * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+ * @brief Clear Channel 2 half transfer flag.
+ * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+ * @brief Clear Channel 3 half transfer flag.
+ * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+ * @brief Clear Channel 4 half transfer flag.
+ * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+ * @brief Clear Channel 5 half transfer flag.
+ * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+/**
+ * @brief Clear Channel 6 half transfer flag.
+ * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+
+/**
+ * @brief Clear Channel 7 half transfer flag.
+ * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer error flag.
+ * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer error flag.
+ * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer error flag.
+ * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer error flag.
+ * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer error flag.
+ * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer error flag.
+ * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer error flag.
+ * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Enable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Enable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Disable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Disable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Disable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Check if Transfer complete Interrupt is enabled.
+ * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_TCIE) == (DMA_CCR_TCIE));
+}
+
+/**
+ * @brief Check if Half transfer Interrupt is enabled.
+ * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_HTIE) == (DMA_CCR_HTIE));
+}
+
+/**
+ * @brief Check if Transfer error Interrupt is enabled.
+ * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_TEIE) == (DMA_CCR_TEIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h
new file mode 100644
index 0000000..612e005
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h
@@ -0,0 +1,888 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_LL_EXTI_H
+#define STM32F1xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+ * @{
+ */
+typedef struct
+{
+
+ uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+ FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+
+ uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+ uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+ * @{
+ */
+#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
+#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
+#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
+#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
+#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
+#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
+#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
+#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
+#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
+#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
+#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
+#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
+#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
+#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
+#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
+#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
+#endif
+#if defined(EXTI_IMR_IM19)
+#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
+#endif
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
+#endif
+#if defined(EXTI_IMR_IM23)
+#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
+#endif
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ * @{
+ */
+#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
+
+/**
+ * @}
+ */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in EXTI register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in EXTI register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+ * @{
+ */
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 0 to 31
+ * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* EXTI */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h
new file mode 100644
index 0000000..8cc7832
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h
@@ -0,0 +1,2347 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_LL_GPIO_H
+#define STM32F1xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
+
+/** @defgroup GPIO_LL GPIO
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
+ * @{
+ */
+/* Defines used for Pin Mask Initialization */
+#define GPIO_PIN_MASK_POS 8U
+#define GPIO_PIN_NB 16U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL GPIO Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+ uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \
+ LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \
+ LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \
+ LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
+ LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
+ LL_GPIO_PIN_15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */
+#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */
+#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */
+#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ * @{
+ */
+#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+ * @{
+ */
+#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */
+#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */
+#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */
+/**
+ * @}
+ */
+
+#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ * @{
+ */
+#define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */
+#define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
+ * @{
+ */
+
+#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
+#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
+#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
+#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
+#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
+#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
+#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
+#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
+#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
+#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
+#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
+#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
+#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
+#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
+#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
+#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
+ * @{
+ */
+
+#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
+#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
+#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
+#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
+#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
+ * @{
+ */
+#define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */
+#define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */
+#define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */
+#define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */
+#define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */
+#define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */
+#define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
+ * @{
+ */
+#define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
+#define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
+#define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
+#define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
+#define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
+#define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
+#define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
+#define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
+#define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
+#define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
+#define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
+#define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
+#define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
+ * Alternate function Output.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll CRL CNFy LL_GPIO_SetPinMode
+ * @rmtoll CRL MODEy LL_GPIO_SetPinMode
+ * @rmtoll CRH CNFy LL_GPIO_SetPinMode
+ * @rmtoll CRH MODEy LL_GPIO_SetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @arg @ref LL_GPIO_MODE_FLOATING
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
+ MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
+ * Alternate function Output.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll CRL CNFy LL_GPIO_GetPinMode
+ * @rmtoll CRL MODEy LL_GPIO_GetPinMode
+ * @rmtoll CRH CNFy LL_GPIO_GetPinMode
+ * @rmtoll CRH MODEy LL_GPIO_GetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @arg @ref LL_GPIO_MODE_FLOATING
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
+ return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium or Fast speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
+ * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Speed This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
+ MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
+ (Speed << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
+ * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
+ return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
+ * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @param OutputType This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
+ MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
+ (OutputType << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
+ * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
+ return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+
+}
+
+/**
+ * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll ODR ODR LL_GPIO_SetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Pull This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @arg @ref LL_GPIO_PULL_UP
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+ MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
+}
+
+/**
+ * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll ODR ODR LL_GPIO_GetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @arg @ref LL_GPIO_PULL_UP
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
+}
+
+/**
+ * @brief Lock configuration of several pins for a dedicated port.
+ * @note When the lock sequence has been applied on a port bit, the
+ * value of this port bit can no longer be modified until the
+ * next reset.
+ * @note Each lock bit freezes a specific configuration register
+ * (control and alternate function registers).
+ * @rmtoll LCKR LCKK LL_GPIO_LockPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ __IO uint32_t temp;
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
+ WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
+ temp = READ_REG(GPIOx->LCKR);
+ (void) temp;
+}
+
+/**
+ * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+ * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
+}
+
+/**
+ * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
+ * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
+ * @param GPIOx GPIO Port
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+ return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_GPIO_ReadInputPort
+ * @param GPIOx GPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+ return (READ_REG(GPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
+ * @param GPIOx GPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+ WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
+ * @param GPIOx GPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_TogglePin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
+ WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
+ * @brief This section propose definition to remap the alternate function to some other port/pins.
+ * @{
+ */
+
+/**
+ * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
+ * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
+ * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if SPI1 has been remaped or not
+ * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
+}
+
+/**
+ * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
+ * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
+ * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
+ * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
+ * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if I2C1 has been remaped or not
+ * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
+}
+
+/**
+ * @brief Enable the remapping of USART1 alternate function TX and RX.
+ * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
+ * @note ENABLE: Remap (TX/PB6, RX/PB7)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of USART1 alternate function TX and RX.
+ * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
+ * @note DISABLE: No remap (TX/PA9, RX/PA10)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if USART1 has been remaped or not
+ * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
+}
+
+/**
+ * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
+ * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
+ * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if USART2 has been remaped or not
+ * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
+}
+
+#if defined (AFIO_MAPR_USART3_REMAP)
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
+ * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
+ * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
+ * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
+}
+#endif
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
+ * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
+ * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
+ * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
+ * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
+ * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
+ * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
+ * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
+ * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
+ * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
+ * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
+ * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
+}
+
+#if defined(AFIO_MAPR_TIM4_REMAP)
+/**
+ * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
+ * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
+ * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
+ * @note TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+/**
+ * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
+ * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
+ * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
+ * @note TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if TIM4 has been remaped or not
+ * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
+ * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
+ * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG));
+}
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
+ * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG));
+}
+#endif
+
+/**
+ * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ * on 100-pin and 144-pin packages, no need for remapping).
+ * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
+ * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ * on 100-pin and 144-pin packages, no need for remapping).
+ * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
+ * @note DISABLE: No remapping of PD0 and PD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if PD01 has been remaped or not
+ * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
+}
+
+#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
+/**
+ * @brief Enable the remapping of TIM5CH4.
+ * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
+ * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
+ * @note This function is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of TIM5CH4.
+ * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
+ * @note DISABLE: TIM5_CH4 is connected to PA3
+ * @note This function is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if TIM5CH4 has been remaped or not
+ * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_ETH_REMAP)
+/**
+ * @brief Enable the remapping of Ethernet MAC connections with the PHY.
+ * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
+ * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of Ethernet MAC connections with the PHY.
+ * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
+ * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if ETH has been remaped or not
+ * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
+ * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+/**
+ * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
+ * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if CAN2 has been remaped or not
+ * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_MII_RMII_SEL)
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
+ * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
+ * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+#endif
+
+#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+/**
+ * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
+ * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
+ * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if ADC1_ETRGINJ has been remaped or not
+ * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
+/**
+ * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
+ * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
+ * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if ADC1_ETRGREG has been remaped or not
+ * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
+ * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
+ * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if ADC2_ETRGINJ has been remaped or not
+ * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
+}
+#endif
+
+#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
+ * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
+ * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if ADC2_ETRGREG has been remaped or not
+ * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
+}
+#endif
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
+ * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
+{
+ CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
+}
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
+ * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
+{
+ CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
+}
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
+ * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
+{
+ CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
+}
+
+/**
+ * @brief Disable the Serial wire JTAG configuration
+ * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
+ * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
+{
+ CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
+}
+
+#if defined(AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
+ * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
+ * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Check if SPI3 has been remaped or not
+ * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
+ * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
+ * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+#endif
+
+#if defined(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
+ * @note ENABLE: PTP_PPS is output on PB5 pin.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG);
+}
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
+ * @note DISABLE: PTP_PPS not output on PB5 pin.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
+{
+ MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
+ * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
+ * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
+}
+
+/**
+ * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
+ * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM10_CH1.
+ * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
+ * @note ENABLE: Remap (TIM10_CH1 on PF6).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM10_CH1.
+ * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
+ * @note DISABLE: No remap (TIM10_CH1 on PB8).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
+}
+
+/**
+ * @brief Check if TIM10_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM11_REMAP)
+/**
+ * @brief Enable the remapping of TIM11_CH1.
+ * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
+ * @note ENABLE: Remap (TIM11_CH1 on PF7).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM11_CH1.
+ * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
+ * @note DISABLE: No remap (TIM11_CH1 on PB9).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
+}
+
+/**
+ * @brief Check if TIM11_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM13_CH1.
+ * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
+ * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM13_CH1.
+ * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
+ * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
+}
+
+/**
+ * @brief Check if TIM13_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM14_CH1.
+ * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
+ * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM14_CH1.
+ * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
+ * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
+}
+
+/**
+ * @brief Check if TIM14_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
+ * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
+}
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
+ * @note CONNECTED: The NADV signal is connected to the output (default).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
+ * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
+}
+/**
+ * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
+ * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
+}
+
+/**
+ * @brief Check if TIM15_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM16_CH1.
+ * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
+ * @note ENABLE: Remap (TIM16_CH1 on PA6).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM16_CH1.
+ * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
+ * @note DISABLE: No remap (TIM16_CH1 on PB8).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
+}
+
+/**
+ * @brief Check if TIM16_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM17_CH1.
+ * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
+ * @note ENABLE: Remap (TIM17_CH1 on PA7).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM17_CH1.
+ * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
+ * @note DISABLE: No remap (TIM17_CH1 on PB9).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
+}
+
+/**
+ * @brief Check if TIM17_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Enable the remapping of CEC.
+ * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
+ * @note ENABLE: Remap (CEC on PB10).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of CEC.
+ * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
+ * @note DISABLE: No remap (CEC on PB8).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
+}
+
+/**
+ * @brief Check if CEC has been remaped or not
+ * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
+ * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
+}
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
+ * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
+}
+
+/**
+ * @brief Check if TIM1DMA has been remaped or not
+ * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
+ * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
+}
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
+ * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
+}
+
+/**
+ * @brief Check if TIM67DACDMA has been remaped or not
+ * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
+ * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
+ * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
+}
+
+/**
+ * @brief Check if TIM12_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ * This bit is set and cleared by software. It controls miscellaneous features.
+ * The DMA2 channel 5 interrupt position in the vector table.
+ * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
+ * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
+ * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
+}
+
+/**
+ * @brief Miscellaneous features remapping.
+ * This bit is set and cleared by software. It controls miscellaneous features.
+ * The DMA2 channel 5 interrupt position in the vector table.
+ * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
+ * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
+ * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
+}
+
+/**
+ * @brief Check if MISC has been remaped or not
+ * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
+ * @brief This section propose definition to Configure EVENTOUT Cortex feature .
+ * @{
+ */
+
+/**
+ * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
+ * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
+ * EVCR PIN LL_GPIO_AF_ConfigEventout
+ * @param LL_GPIO_PortSource This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
+ * @param LL_GPIO_PinSource This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
+ * @retval None
+*/
+__STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
+{
+ MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource));
+}
+
+/**
+ * @brief Enables the Event Output.
+ * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
+{
+ SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
+}
+
+/**
+ * @brief Disables the Event Output.
+ * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
+{
+ CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
+}
+
+/**
+ * @}
+ */
+/** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
+ * @brief This section Configure source input for the EXTI external interrupt .
+ * @{
+ */
+
+/**
+ * @brief Configure source input for the EXTI external interrupt.
+ * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
+ * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
+ * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
+ * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EXTI_PORTA
+ * @arg @ref LL_GPIO_AF_EXTI_PORTB
+ * @arg @ref LL_GPIO_AF_EXTI_PORTC
+ * @arg @ref LL_GPIO_AF_EXTI_PORTD
+ * @arg @ref LL_GPIO_AF_EXTI_PORTE
+ * @arg @ref LL_GPIO_AF_EXTI_PORTF
+ * @arg @ref LL_GPIO_AF_EXTI_PORTG
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EXTI_LINE0
+ * @arg @ref LL_GPIO_AF_EXTI_LINE1
+ * @arg @ref LL_GPIO_AF_EXTI_LINE2
+ * @arg @ref LL_GPIO_AF_EXTI_LINE3
+ * @arg @ref LL_GPIO_AF_EXTI_LINE4
+ * @arg @ref LL_GPIO_AF_EXTI_LINE5
+ * @arg @ref LL_GPIO_AF_EXTI_LINE6
+ * @arg @ref LL_GPIO_AF_EXTI_LINE7
+ * @arg @ref LL_GPIO_AF_EXTI_LINE8
+ * @arg @ref LL_GPIO_AF_EXTI_LINE9
+ * @arg @ref LL_GPIO_AF_EXTI_LINE10
+ * @arg @ref LL_GPIO_AF_EXTI_LINE11
+ * @arg @ref LL_GPIO_AF_EXTI_LINE12
+ * @arg @ref LL_GPIO_AF_EXTI_LINE13
+ * @arg @ref LL_GPIO_AF_EXTI_LINE14
+ * @arg @ref LL_GPIO_AF_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+ MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
+}
+
+/**
+ * @brief Get the configured defined for specific EXTI Line
+ * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
+ * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
+ * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
+ * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EXTI_LINE0
+ * @arg @ref LL_GPIO_AF_EXTI_LINE1
+ * @arg @ref LL_GPIO_AF_EXTI_LINE2
+ * @arg @ref LL_GPIO_AF_EXTI_LINE3
+ * @arg @ref LL_GPIO_AF_EXTI_LINE4
+ * @arg @ref LL_GPIO_AF_EXTI_LINE5
+ * @arg @ref LL_GPIO_AF_EXTI_LINE6
+ * @arg @ref LL_GPIO_AF_EXTI_LINE7
+ * @arg @ref LL_GPIO_AF_EXTI_LINE8
+ * @arg @ref LL_GPIO_AF_EXTI_LINE9
+ * @arg @ref LL_GPIO_AF_EXTI_LINE10
+ * @arg @ref LL_GPIO_AF_EXTI_LINE11
+ * @arg @ref LL_GPIO_AF_EXTI_LINE12
+ * @arg @ref LL_GPIO_AF_EXTI_LINE13
+ * @arg @ref LL_GPIO_AF_EXTI_LINE14
+ * @arg @ref LL_GPIO_AF_EXTI_LINE15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EXTI_PORTA
+ * @arg @ref LL_GPIO_AF_EXTI_PORTB
+ * @arg @ref LL_GPIO_AF_EXTI_PORTC
+ * @arg @ref LL_GPIO_AF_EXTI_PORTD
+ * @arg @ref LL_GPIO_AF_EXTI_PORTE
+ * @arg @ref LL_GPIO_AF_EXTI_PORTF
+ * @arg @ref LL_GPIO_AF_EXTI_PORTG
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
+{
+ return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h
new file mode 100644
index 0000000..cd75914
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h
@@ -0,0 +1,440 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_PWR_H
+#define __STM32F1xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_WriteReg function
+ * @{
+ */
+#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
+#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_ReadReg function
+ * @{
+ */
+#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
+#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
+#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
+#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+ * @{
+ */
+#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
+ * @{
+ */
+#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+ * @{
+ */
+#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
+#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
+#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
+/**
+ * @}
+ */
+/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PWR register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PWR register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Check if the backup domain is enabled
+ * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
+}
+
+/**
+ * @brief Set voltage Regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
+ * @param RegulMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
+}
+
+/**
+ * @brief Get voltage Regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
+}
+
+/**
+ * @brief Set Power Down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_SetPowerMode
+ * @param PDMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
+}
+
+/**
+ * @brief Get Power Down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_GetPowerMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STANDBY
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
+}
+
+/**
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector
+ * @rmtoll CR PLS LL_PWR_SetPVDLevel
+ * @param PVDLevel This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
+}
+
+/**
+ * @brief Get the voltage threshold detection
+ * @rmtoll CR PLS LL_PWR_GetPVDLevel
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
+}
+
+/**
+ * @brief Enable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_EnablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Disable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_DisablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Check if Power Voltage Detector is enabled
+ * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
+}
+
+/**
+ * @brief Enable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Disable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Check if the WakeUp PINx functionality is enabled
+ * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+ return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Wake-up Flag
+ * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
+}
+
+/**
+ * @brief Get Standby Flag
+ * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
+}
+
+/**
+ * @brief Indicate whether VDD voltage is below the selected PVD threshold
+ * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
+}
+
+/**
+ * @brief Clear Standby Flag
+ * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CSBF);
+}
+
+/**
+ * @brief Clear Wake-up Flags
+ * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CWUF);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PWR) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
new file mode 100644
index 0000000..3ca73fe
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
@@ -0,0 +1,2312 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_RCC_H
+#define __STM32F1xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+ * @{
+ */
+
+/**
+ * @brief RCC Clocks Frequency Structure
+ */
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+ * @brief Defines used to adapt values of different oscillators
+ * @note These values could be modified in the user environment according to
+ * HW set-up.
+ * @{
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_WriteReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
+#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */
+#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */
+#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_ReadReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */
+#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */
+#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
+#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */
+#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR2_PREDIV2)
+/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
+ * @{
+ */
+#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
+#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
+#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
+#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
+#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
+#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
+#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
+#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
+#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
+#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
+#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
+#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
+#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
+#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
+#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
+#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_PREDIV2 */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
+ * @{
+ */
+#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+ * @{
+ */
+#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+ * @{
+ */
+#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
+ * @{
+ */
+#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK /*!< SYSCLK selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI /*!< HSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE /*!< HSE selection as MCO source */
+#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!< PLL clock divided by 2*/
+#if defined(RCC_CFGR_MCO_PLL2CLK)
+#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCO_PLL2CLK /*!< PLL2 clock selected as MCO source*/
+#endif /* RCC_CFGR_MCO_PLL2CLK */
+#if defined(RCC_CFGR_MCO_PLL3CLK_DIV2)
+#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/
+#endif /* RCC_CFGR_MCO_PLL3CLK_DIV2 */
+#if defined(RCC_CFGR_MCO_EXT_HSE)
+#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCO_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+#endif /* RCC_CFGR_MCO_EXT_HSE */
+#if defined(RCC_CFGR_MCO_PLL3CLK)
+#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCO_PLL3CLK /*!< PLLI2S clock selected as MCO source */
+#endif /* RCC_CFGR_MCO_PLL3CLK */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ * @{
+ */
+#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
+ * @{
+ */
+#define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */
+#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */
+#define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */
+#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */
+/**
+ * @}
+ */
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
+ * @{
+ */
+#if defined(RCC_CFGR_USBPRE)
+#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */
+#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */
+#endif /*RCC_CFGR_USBPRE*/
+#if defined(RCC_CFGR_OTGFSPRE)
+#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */
+#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */
+#endif /*RCC_CFGR_OTGFSPRE*/
+/**
+ * @}
+ */
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
+ * @{
+ */
+#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */
+#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
+ * @{
+ */
+#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
+ * @{
+ */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
+ * @{
+ */
+#if defined(RCC_CFGR_PLLMULL2)
+#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */
+#endif /*RCC_CFGR_PLLMULL2*/
+#if defined(RCC_CFGR_PLLMULL3)
+#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */
+#endif /*RCC_CFGR_PLLMULL3*/
+#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */
+#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */
+#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */
+#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */
+#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */
+#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */
+#if defined(RCC_CFGR_PLLMULL6_5)
+#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */
+#else
+#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */
+#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */
+#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */
+#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */
+#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */
+#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */
+#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */
+#endif /*RCC_CFGR_PLLMULL6_5*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
+ * @{
+ */
+#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */
+#if defined(RCC_CFGR2_PREDIV1SRC)
+#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+
+#if defined(RCC_CFGR2_PREDIV1)
+#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
+#if defined(RCC_CFGR2_PREDIV1SRC)
+#define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+#else
+#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */
+#endif /*RCC_CFGR2_PREDIV1*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
+ * @{
+ */
+#if defined(RCC_CFGR2_PREDIV1)
+#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */
+#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */
+#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */
+#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */
+#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */
+#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */
+#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */
+#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */
+#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */
+#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */
+#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */
+#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */
+#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */
+#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */
+#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */
+#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */
+#else
+#define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */
+#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */
+#endif /*RCC_CFGR2_PREDIV1*/
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
+ * @{
+ */
+#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
+#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
+#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
+#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
+#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
+#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
+#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
+#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
+#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
+/**
+ * @}
+ */
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
+ * @{
+ */
+#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
+#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
+#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
+#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
+#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
+#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
+#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
+#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
+#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
+/**
+ * @}
+ */
+
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RCC register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RCC register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+ * @{
+ */
+
+#if defined(RCC_CFGR_PLLMULL6_5)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
+ * @param __PLLMUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_6_5
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
+ (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
+ ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\
+ (((__INPUTFREQ__) * 13U) / 2U))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
+ * @param __PLLMUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
+#endif /* RCC_CFGR_PLLMULL6_5 */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLI2S frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
+ * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
+ * @param __PLLI2SMUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2S_MUL_8
+ * @arg @ref LL_RCC_PLLI2S_MUL_9
+ * @arg @ref LL_RCC_PLLI2S_MUL_10
+ * @arg @ref LL_RCC_PLLI2S_MUL_11
+ * @arg @ref LL_RCC_PLLI2S_MUL_12
+ * @arg @ref LL_RCC_PLLI2S_MUL_13
+ * @arg @ref LL_RCC_PLLI2S_MUL_14
+ * @arg @ref LL_RCC_PLLI2S_MUL_16
+ * @arg @ref LL_RCC_PLLI2S_MUL_20
+ * @param __PLLI2SDIV__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLL2 frequency
+ * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
+ * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
+ * @param __PLL2MUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL2_MUL_8
+ * @arg @ref LL_RCC_PLL2_MUL_9
+ * @arg @ref LL_RCC_PLL2_MUL_10
+ * @arg @ref LL_RCC_PLL2_MUL_11
+ * @arg @ref LL_RCC_PLL2_MUL_12
+ * @arg @ref LL_RCC_PLL2_MUL_13
+ * @arg @ref LL_RCC_PLL2_MUL_14
+ * @arg @ref LL_RCC_PLL2_MUL_16
+ * @arg @ref LL_RCC_PLL2_MUL_20
+ * @param __PLL2DIV__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ * @retval PLL2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Helper macro to calculate the HCLK frequency
+ * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
+ * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
+ * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+ * @param __AHBPRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval HCLK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
+ * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
+ * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB1PRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
+ * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
+ * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB2PRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+ * @{
+ */
+
+/**
+ * @brief Enable the Clock Security System.
+ * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Enable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Disable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Enable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Disable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Check if HSE oscillator Ready
+ * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+#if defined(RCC_CFGR2_PREDIV2)
+/**
+ * @brief Get PREDIV2 division factor
+ * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
+}
+#endif /* RCC_CFGR2_PREDIV2 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+ * @{
+ */
+
+/**
+ * @brief Enable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Disable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Check if HSI clock is ready
+ * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+ * @brief Get HSI Calibration value
+ * @note When HSITRIM is written, HSICAL is updated with the sum of
+ * HSITRIM and the factory trim value
+ * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+}
+
+/**
+ * @brief Set HSI Calibration trimming
+ * @note user-programmable trimming value that is added to the HSICAL
+ * @note Default value is 16, which, when added to the HSICAL value,
+ * should trim the HSI to 16 MHz +/- 1 %
+ * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
+ * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+}
+
+/**
+ * @brief Get HSI Calibration trimming
+ * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
+ * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+ * @{
+ */
+
+/**
+ * @brief Enable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Disable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Enable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Disable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Check if LSE oscillator Ready
+ * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+ * @{
+ */
+
+/**
+ * @brief Enable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Disable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Check if LSI is Ready
+ * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_System System
+ * @{
+ */
+
+/**
+ * @brief Configure the system clock source
+ * @rmtoll CFGR SW LL_RCC_SetSysClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+ * @brief Get the system clock source
+ * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Set AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+ * @brief Set APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+ * @brief Set APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+ * @brief Get AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+ * @brief Get APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+ * @brief Get APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+ * @{
+ */
+
+/**
+ * @brief Configure MCOx
+ * @rmtoll CFGR MCO LL_RCC_ConfigMCO
+ * @param MCOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+ * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI
+ * @arg @ref LL_RCC_MCO1SOURCE_HSE
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
+ * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+ * @{
+ */
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/**
+ * @brief Configure I2Sx clock source
+ * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
+ * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
+{
+ MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
+}
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/**
+ * @brief Configure USB clock source
+ * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
+ * CFGR USBPRE LL_RCC_SetUSBClockSource
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+#if defined(RCC_CFGR_USBPRE)
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
+#else /*RCC_CFGR_OTGFSPRE*/
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
+#endif /*RCC_CFGR_USBPRE*/
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
+}
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/**
+ * @brief Get I2Sx clock source
+ * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
+ * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
+ * @param I2Sx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx);
+}
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/**
+ * @brief Get USBx clock source
+ * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
+ * CFGR USBPRE LL_RCC_GetUSBClockSource
+ * @param USBx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+ * @{
+ */
+
+/**
+ * @brief Set RTC Clock Source
+ * @note Once the RTC clock source has been selected, it cannot be changed any more unless
+ * the Backup domain is reset. The BDRST bit can be used to reset them.
+ * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+ * @brief Get RTC Clock Source
+ * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+ * @brief Enable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Disable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Check if RTC has been enabled or not
+ * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+ * @brief Force the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Release the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+ * @{
+ */
+
+/**
+ * @brief Enable PLL
+ * @rmtoll CR PLLON LL_RCC_PLL_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Disable PLL
+ * @note Cannot be disabled if the PLL clock is used as the system clock
+ * @rmtoll CR PLLON LL_RCC_PLL_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Check if PLL Ready
+ * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
+ *
+ * (*) value not defined in all devices
+ * @param PLLMul This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2 (*)
+ * @arg @ref LL_RCC_PLL_MUL_3 (*)
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
+ * @arg @ref LL_RCC_PLL_MUL_10 (*)
+ * @arg @ref LL_RCC_PLL_MUL_11 (*)
+ * @arg @ref LL_RCC_PLL_MUL_12 (*)
+ * @arg @ref LL_RCC_PLL_MUL_13 (*)
+ * @arg @ref LL_RCC_PLL_MUL_14 (*)
+ * @arg @ref LL_RCC_PLL_MUL_15 (*)
+ * @arg @ref LL_RCC_PLL_MUL_16 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
+ (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul);
+#if defined(RCC_CFGR2_PREDIV1)
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC),
+ (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
+#else
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+#endif /*RCC_CFGR2_PREDIV1*/
+}
+
+/**
+ * @brief Configure PLL clock source
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n
+ * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
+#endif /* RCC_CFGR2_PREDIV1SRC */
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n
+ * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
+ uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
+ return (uint32_t)(pllsrc | predivsrc);
+#else
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+}
+
+/**
+ * @brief Get PLL multiplication Factor
+ * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2 (*)
+ * @arg @ref LL_RCC_PLL_MUL_3 (*)
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
+ * @arg @ref LL_RCC_PLL_MUL_10 (*)
+ * @arg @ref LL_RCC_PLL_MUL_11 (*)
+ * @arg @ref LL_RCC_PLL_MUL_12 (*)
+ * @arg @ref LL_RCC_PLL_MUL_13 (*)
+ * @arg @ref LL_RCC_PLL_MUL_14 (*)
+ * @arg @ref LL_RCC_PLL_MUL_15 (*)
+ * @arg @ref LL_RCC_PLL_MUL_16 (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
+}
+
+/**
+ * @brief Get PREDIV1 division factor for the main PLL
+ * @note They can be written only when the PLL is disabled
+ * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n
+ * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PREDIV_DIV_1
+ * @arg @ref LL_RCC_PREDIV_DIV_2
+ * @arg @ref LL_RCC_PREDIV_DIV_3 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_4 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_5 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_6 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_7 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_8 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_9 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_10 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_11 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_12 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_13 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_14 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_15 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_16 (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
+{
+#if defined(RCC_CFGR2_PREDIV1)
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
+#else
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos);
+#endif /*RCC_CFGR2_PREDIV1*/
+}
+
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
+ * @{
+ */
+
+/**
+ * @brief Enable PLLI2S
+ * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+ * @brief Disable PLLI2S
+ * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+ * @brief Check if PLLI2S Ready
+ * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
+}
+
+/**
+ * @brief Configure PLLI2S used for I2S Domain
+ * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n
+ * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S
+ * @param Divider This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ * @param Multiplicator This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2S_MUL_8
+ * @arg @ref LL_RCC_PLLI2S_MUL_9
+ * @arg @ref LL_RCC_PLLI2S_MUL_10
+ * @arg @ref LL_RCC_PLLI2S_MUL_11
+ * @arg @ref LL_RCC_PLLI2S_MUL_12
+ * @arg @ref LL_RCC_PLLI2S_MUL_13
+ * @arg @ref LL_RCC_PLLI2S_MUL_14
+ * @arg @ref LL_RCC_PLLI2S_MUL_16
+ * @arg @ref LL_RCC_PLLI2S_MUL_20
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator);
+}
+
+/**
+ * @brief Get PLLI2S Multiplication Factor
+ * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2S_MUL_8
+ * @arg @ref LL_RCC_PLLI2S_MUL_9
+ * @arg @ref LL_RCC_PLLI2S_MUL_10
+ * @arg @ref LL_RCC_PLLI2S_MUL_11
+ * @arg @ref LL_RCC_PLLI2S_MUL_12
+ * @arg @ref LL_RCC_PLLI2S_MUL_13
+ * @arg @ref LL_RCC_PLLI2S_MUL_14
+ * @arg @ref LL_RCC_PLLI2S_MUL_16
+ * @arg @ref LL_RCC_PLLI2S_MUL_20
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/** @defgroup RCC_LL_EF_PLL2 PLL2
+ * @{
+ */
+
+/**
+ * @brief Enable PLL2
+ * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+ * @brief Disable PLL2
+ * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+ * @brief Check if PLL2 Ready
+ * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
+}
+
+/**
+ * @brief Configure PLL2 used for PLL2 Domain
+ * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n
+ * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2
+ * @param Divider This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ * @param Multiplicator This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL2_MUL_8
+ * @arg @ref LL_RCC_PLL2_MUL_9
+ * @arg @ref LL_RCC_PLL2_MUL_10
+ * @arg @ref LL_RCC_PLL2_MUL_11
+ * @arg @ref LL_RCC_PLL2_MUL_12
+ * @arg @ref LL_RCC_PLL2_MUL_13
+ * @arg @ref LL_RCC_PLL2_MUL_14
+ * @arg @ref LL_RCC_PLL2_MUL_16
+ * @arg @ref LL_RCC_PLL2_MUL_20
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator);
+}
+
+/**
+ * @brief Get PLL2 Multiplication Factor
+ * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL2_MUL_8
+ * @arg @ref LL_RCC_PLL2_MUL_9
+ * @arg @ref LL_RCC_PLL2_MUL_10
+ * @arg @ref LL_RCC_PLL2_MUL_11
+ * @arg @ref LL_RCC_PLL2_MUL_12
+ * @arg @ref LL_RCC_PLL2_MUL_13
+ * @arg @ref LL_RCC_PLL2_MUL_14
+ * @arg @ref LL_RCC_PLL2_MUL_16
+ * @arg @ref LL_RCC_PLL2_MUL_20
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_PLL2_SUPPORT */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear LSI ready interrupt flag
+ * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
+}
+
+/**
+ * @brief Clear LSE ready interrupt flag
+ * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
+}
+
+/**
+ * @brief Clear HSI ready interrupt flag
+ * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
+}
+
+/**
+ * @brief Clear HSE ready interrupt flag
+ * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
+}
+
+/**
+ * @brief Clear PLL ready interrupt flag
+ * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Clear PLLI2S ready interrupt flag
+ * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Clear PLL2 ready interrupt flag
+ * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Clear Clock security system interrupt flag
+ * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_CSSC);
+}
+
+/**
+ * @brief Check if LSI ready interrupt occurred or not
+ * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
+}
+
+/**
+ * @brief Check if LSE ready interrupt occurred or not
+ * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
+}
+
+/**
+ * @brief Check if HSI ready interrupt occurred or not
+ * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
+}
+
+/**
+ * @brief Check if HSE ready interrupt occurred or not
+ * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
+}
+
+/**
+ * @brief Check if PLL ready interrupt occurred or not
+ * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Check if PLLI2S ready interrupt occurred or not
+ * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Check if PLL2 ready interrupt occurred or not
+ * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
+}
+
+/**
+ * @brief Check if RCC flag Independent Watchdog reset is set or not.
+ * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Low Power reset is set or not.
+ * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Pin reset is set or not.
+ * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+ * @brief Check if RCC flag POR/PDR reset is set or not.
+ * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Software reset is set or not.
+ * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Window Watchdog reset is set or not.
+ * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+/**
+ * @brief Set RMVF bit to clear the reset flags.
+ * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Enable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Enable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Enable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Enable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Enable PLLI2S ready interrupt
+ * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Enable PLL2 ready interrupt
+ * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Disable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Disable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Disable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Disable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Disable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Disable PLLI2S ready interrupt
+ * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Disable PLL2 ready interrupt
+ * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Checks if LSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
+}
+
+/**
+ * @brief Checks if LSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
+}
+
+/**
+ * @brief Checks if HSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
+}
+
+/**
+ * @brief Checks if HSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
+}
+
+/**
+ * @brief Checks if PLL ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+ * @{
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+#if defined(RCC_CFGR2_I2S2SRC)
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#endif /* RCC_CFGR2_I2S2SRC */
+#if defined(USB_OTG_FS) || defined(USB)
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* RCC */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h
new file mode 100644
index 0000000..a17687e
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h
@@ -0,0 +1,1938 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_LL_SPI_H
+#define STM32F1xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @defgroup SPI_LL SPI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief SPI Init structures definition
+ */
+typedef struct
+{
+ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+ uint32_t DataWidth; /*!< Specifies the SPI data width.
+ This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+ @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+ This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_SPI_ReadReg function
+ * @{
+ */
+#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
+#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
+#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
+#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
+#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
+#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @{
+ */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ * @{
+ */
+#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @{
+ */
+#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
+#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
+#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ * @{
+ */
+#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
+#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
+#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
+#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @{
+ */
+#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable SPI peripheral
+ * @rmtoll CR1 SPE LL_SPI_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Disable SPI peripheral
+ * @note When disabling the SPI, follow the procedure described in the Reference Manual.
+ * @rmtoll CR1 SPE LL_SPI_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Check if SPI peripheral is enabled
+ * @rmtoll CR1 SPE LL_SPI_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set SPI operation mode to Master or Slave
+ * @note This bit should not be changed when communication is ongoing.
+ * @rmtoll CR1 MSTR LL_SPI_SetMode\n
+ * CR1 SSI LL_SPI_SetMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+ * @brief Get SPI operation mode (Master or Slave)
+ * @rmtoll CR1 MSTR LL_SPI_GetMode\n
+ * CR1 SSI LL_SPI_GetMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+
+/**
+ * @brief Set clock phase
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
+ * @param SPIx SPI Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Get clock phase
+ * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+ * @brief Set clock polarity
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Get clock polarity
+ * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+ * @brief Set baud rate prescaler
+ * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+ * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @param BaudRate This parameter can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+ * @brief Get baud rate prescaler
+ * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+ * @brief Set transfer bit order
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Get transfer bit order
+ * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+ * @brief Set transfer direction mode
+ * @note For Half-Duplex mode, Rx Direction is set by default.
+ * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+ * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_SetTransferDirection
+ * @param SPIx SPI Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+ * @brief Get transfer direction mode
+ * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_GetTransferDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+ * @brief Set frame data width
+ * @rmtoll CR1 DFF LL_SPI_SetDataWidth
+ * @param SPIx SPI Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
+}
+
+/**
+ * @brief Get frame data width
+ * @rmtoll CR1 DFF LL_SPI_GetDataWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ * @{
+ */
+
+/**
+ * @brief Enable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Disable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Check if CRC is enabled
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set CRCNext to transfer CRC on the line
+ * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
+ * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+ * @brief Set polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+ WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+ * @brief Get polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+ * @brief Get Rx CRC
+ * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+ * @brief Get Tx CRC
+ * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ * @{
+ */
+
+/**
+ * @brief Set NSS mode
+ * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
+ * @param SPIx SPI Instance
+ * @param NSS This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+ * @brief Get NSS mode
+ * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+ uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ return (Ssm | Ssoe);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get mode fault error flag
+ * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get busy flag
+ * @note The BSY flag is cleared under any one of the following conditions:
+ * -When the SPI is correctly disabled
+ * -When a fault is detected in Master mode (MODF bit set to 1)
+ * -In Master mode, when it finishes a data transmission and no new data is ready to be
+ * sent
+ * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+ * each data transfer.
+ * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Clear CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+ * @brief Clear mode fault error flag
+ * @note Clearing this flag is done by a read access to the SPIx_SR
+ * register followed by a write access to the SPIx_CR1 register
+ * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg_sr;
+ tmpreg_sr = SPIx->SR;
+ (void) tmpreg_sr;
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @note Clearing this flag is done by a read access to the SPIx_DR
+ * register followed by a read access to the SPIx_SR register
+ * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->DR;
+ (void) tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @note Clearing this flag is done by reading SPIx_SR register
+ * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Enable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Enable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Disable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Disable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Disable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Check if error interrupt is enabled
+ * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx buffer not empty interrupt is enabled
+ * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
+ * @param SPIx SPI Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+ return (uint32_t) &(SPIx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData8
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+ return (uint8_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Read 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Write 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData8
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+#if defined (__GNUC__)
+ __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ *((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+ * @brief Write 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+#if defined (__GNUC__)
+ __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ SPIx->DR = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup I2S_LL I2S
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_LL_EC_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+ Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
+ and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+
+
+ uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+ * @{
+ */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2S_ReadReg function
+ * @{
+ */
+#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
+#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
+#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
+#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+ * @{
+ */
+#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
+#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
+#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
+#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+ * @{
+ */
+#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
+#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
+#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
+#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
+#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
+#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+ * @{
+ */
+#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+ * @{
+ */
+#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+ * @{
+ */
+
+#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Select I2S mode and Enable I2S peripheral
+ * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
+ * I2SCFGR I2SE LL_I2S_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Disable I2S peripheral
+ * @rmtoll I2SCFGR I2SE LL_I2S_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Check if I2S peripheral is enabled
+ * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_SetDataFormat
+ * @param SPIx SPI Instance
+ * @param DataFormat This parameter can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+ * @brief Get I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_GetDataFormat
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+ * @brief Set I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+ * @brief Get I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+ * @brief Set I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+ * @brief Get I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+ * @brief Set I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+ * @brief Get I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+ * @brief Set I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+ * @brief Get I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+ * @brief Set I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
+ * @param SPIx SPI Instance
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+ * @brief Get I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+ * @brief Enable the master clock output (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Disable the master clock output (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Check if the master clock output (Pin MCK) is enabled
+ * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+ * @brief Get busy flag
+ * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Get underrun error flag
+ * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Get channel side flag.
+ * @note 0: Channel Left has to be transmitted or has been received\n
+ * 1: Channel Right has to be transmitted or has been received\n
+ * It has no significance in PCM mode.
+ * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Clear underrun error flag
+ * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Enable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Enable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Disable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Disable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Disable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Check if ERR IT is enabled
+ * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+ * @brief Check if RXNE IT is enabled
+ * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if TXE IT is enabled
+ * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+ * @brief Write 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_LL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h
new file mode 100644
index 0000000..b22f8df
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h
@@ -0,0 +1,574 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_system.h
+ * @author MCD Application Team
+ * @brief Header file of SYSTEM LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL SYSTEM driver contains a set of generic APIs that can be
+ used by user:
+ (+) Some of the FLASH features need to be handled in the SYSTEM file.
+ (+) Access to DBGCMU registers
+ (+) Access to SYSCFG registers
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_SYSTEM_H
+#define __STM32F1xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (FLASH) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @{
+ */
+
+
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @{
+ */
+#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
+#if defined(DBGMCU_CR_DBG_TIM5_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM5_STOP */
+#if defined(DBGMCU_CR_DBG_TIM6_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM6_STOP */
+#if defined(DBGMCU_CR_DBG_TIM7_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM7_STOP */
+#if defined(DBGMCU_CR_DBG_TIM12_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM12_STOP */
+#if defined(DBGMCU_CR_DBG_TIM13_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM13_STOP */
+#if defined(DBGMCU_CR_DBG_TIM14_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM14_STOP */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
+#if defined(DBGMCU_CR_DBG_CAN1_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
+#endif /* DBGMCU_CR_DBG_CAN1_STOP */
+#if defined(DBGMCU_CR_DBG_CAN2_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
+#endif /* DBGMCU_CR_DBG_CAN2_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
+#if defined(DBGMCU_CR_DBG_TIM8_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_CAN1_STOP */
+#if defined(DBGMCU_CR_DBG_TIM9_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM9_STOP */
+#if defined(DBGMCU_CR_DBG_TIM10_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM10_STOP */
+#if defined(DBGMCU_CR_DBG_TIM11_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM11_STOP */
+#if defined(DBGMCU_CR_DBG_TIM15_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM15_STOP */
+#if defined(DBGMCU_CR_DBG_TIM16_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM16_STOP */
+#if defined(DBGMCU_CR_DBG_TIM17_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM17_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @{
+ */
+#if defined(FLASH_ACR_LATENCY)
+#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
+#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
+#else
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @{
+ */
+
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @{
+ */
+
+/**
+ * @brief Return the device identifier
+ * @note For Low Density devices, the device ID is 0x412
+ * @note For Medium Density devices, the device ID is 0x410
+ * @note For High Density devices, the device ID is 0x414
+ * @note For XL Density devices, the device ID is 0x430
+ * @note For Connectivity Line devices, the device ID is 0x418
+ * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+ * @brief Return the device revision identifier
+ * @note This field indicates the revision of the device.
+ For example, it is read as revA -> 0x1000,for Low Density devices
+ For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
+ For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
+ For example, it is read as revA or 1 -> 0x1003,for XL Density devices
+ For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
+ * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Set Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
+ * @param PinAssignment This parameter can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+ * @brief Get Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->CR, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->CR, Periphs);
+}
+
+/**
+ * @brief Freeze APB2 peripherals
+ * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->CR, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB2 peripherals
+ * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->CR, Periphs);
+}
+/**
+ * @}
+ */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @{
+ */
+
+/**
+ * @brief Set FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
+ * @param Latency This parameter can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+ * @brief Get FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+ * @brief Enable Prefetch
+ * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
+}
+
+/**
+ * @brief Disable Prefetch
+ * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
+}
+
+/**
+ * @brief Check if Prefetch buffer is enabled
+ * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
+}
+
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @brief Enable Flash Half Cycle Access
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
+}
+
+/**
+ * @brief Disable Flash Half Cycle Access
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
+}
+
+/**
+ * @brief Check if Flash Half Cycle Access is enabled or not
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (FLASH) || defined (DBGMCU) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h
new file mode 100644
index 0000000..56d1232
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_utils.h
+ * @author MCD Application Team
+ * @brief Header file of UTILS LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL UTILS driver contains a set of generic APIs that can be
+ used by user:
+ (+) Device electronic signature
+ (+) Timing functions
+ (+) PLL configuration functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_UTILS_H
+#define __STM32F1xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UTILS_LL UTILS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+ * @{
+ */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY 0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+ * @{
+ */
+/**
+ * @brief UTILS PLL structure definition
+ */
+typedef struct
+{
+ uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
+ This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+ * @brief UTILS System, AHB and APB buses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAHBPrescaler(). */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB1Prescaler(). */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ * @{
+ */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ * @{
+ */
+#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ * @{
+ */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ * @{
+ */
+
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed in
+ * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+ return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source of the time base.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @note When a RTOS is used, it is recommended to avoid changing the SysTick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param Ticks Number of ticks
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
+}
+
+void LL_Init1msTick(uint32_t HCLKFrequency);
+void LL_mDelay(uint32_t Delay);
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+ * @{
+ */
+
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+#if defined(FLASH_ACR_LATENCY)
+ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
+#endif /* FLASH_ACR_LATENCY */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
deleted file mode 100644
index 616c155..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
+++ /dev/null
@@ -1,606 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal.c
- * @author MCD Application Team
- * @brief HAL module driver.
- * This is the common part of the HAL initialization
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The common HAL driver contains a set of generic and common APIs that can be
- used by the PPP peripheral drivers and the user to start using the HAL.
- [..]
- The HAL contains two APIs' categories:
- (+) Common HAL APIs
- (+) Services HAL APIs
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL HAL
- * @brief HAL module driver.
- * @{
- */
-
-#ifdef HAL_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup HAL_Private_Constants HAL Private Constants
- * @{
- */
-/**
- * @brief STM32F1xx HAL Driver version number V1.1.7
- */
-#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
-#define __STM32F1xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
-#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
-#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
- |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
- |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
- |(__STM32F1xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK 0x00000FFFU
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/** @defgroup HAL_Private_Variables HAL Private Variables
- * @{
- */
-__IO uint32_t uwTick;
-uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
-HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
- * @{
- */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initializes the Flash interface, the NVIC allocation and initial clock
- configuration. It initializes the systick also when timeout is needed
- and the backup domain when enabled.
- (+) de-Initializes common part of the HAL.
- (+) Configure The time base source to have 1ms time base with a dedicated
- Tick interrupt priority.
- (++) SysTick timer is used by default as source of time base, but user
- can eventually implement his proper time base source (a general purpose
- timer for example or other time source), keeping in mind that Time base
- duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
- handled in milliseconds basis.
- (++) Time base configuration function (HAL_InitTick ()) is called automatically
- at the beginning of the program after reset by HAL_Init() or at any time
- when clock is configured, by HAL_RCC_ClockConfig().
- (++) Source of time base is configured to generate interrupts at regular
- time intervals. Care must be taken if HAL_Delay() is called from a
- peripheral ISR process, the Tick interrupt line must have higher priority
- (numerically lower) than the peripheral interrupt. Otherwise the caller
- ISR process will be blocked.
- (++) functions affecting time base configurations are declared as __weak
- to make override possible in case of other implementations in user file.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is used to initialize the HAL Library; it must be the first
- * instruction to be executed in the main program (before to call any other
- * HAL function), it performs the following:
- * Configure the Flash prefetch.
- * Configures the SysTick to generate an interrupt each 1 millisecond,
- * which is clocked by the HSI (at this stage, the clock is not yet
- * configured and thus the system is running from the internal HSI at 16 MHz).
- * Set NVIC Group Priority to 4.
- * Calls the HAL_MspInit() callback function defined in user file
- * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization
- *
- * @note SysTick is used as time base for the HAL_Delay() function, the application
- * need to ensure that the SysTick time base is always set to 1 millisecond
- * to have correct HAL operation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- /* Configure Flash prefetch */
-#if (PREFETCH_ENABLE != 0)
-#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
- defined(STM32F102x6) || defined(STM32F102xB) || \
- defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
- defined(STM32F105xC) || defined(STM32F107xC)
-
- /* Prefetch buffer is not available on value line devices */
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
- HAL_InitTick(TICK_INT_PRIORITY);
-
- /* Init the low level hardware */
- HAL_MspInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief This function de-Initializes common part of the HAL and stops the systick.
- * of time base.
- * @note This function is optional.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
- /* Reset of all peripherals */
- __HAL_RCC_APB1_FORCE_RESET();
- __HAL_RCC_APB1_RELEASE_RESET();
-
- __HAL_RCC_APB2_FORCE_RESET();
- __HAL_RCC_APB2_RELEASE_RESET();
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- __HAL_RCC_AHB_FORCE_RESET();
- __HAL_RCC_AHB_RELEASE_RESET();
-#endif
-
- /* De-Init the low level hardware */
- HAL_MspDeInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the MSP.
- * @retval None
- */
-__weak void HAL_MspInit(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the MSP.
- * @retval None
- */
-__weak void HAL_MspDeInit(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief This function configures the source of the time base.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
- * @note In the default implementation, SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals.
- * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
- * The SysTick interrupt must have higher priority (numerically lower)
- * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
- * The function is declared as __weak to be overwritten in case of other
- * implementation in user file.
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- {
- return HAL_ERROR;
- }
-
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- uwTickPrio = TickPriority;
- }
- else
- {
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
- *
-@verbatim
- ===============================================================================
- ##### HAL Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Provide a tick value in millisecond
- (+) Provide a blocking delay in millisecond
- (+) Suspend the time base source interrupt
- (+) Resume the time base source interrupt
- (+) Get the HAL API driver version
- (+) Get the device identifier
- (+) Get the device revision identifier
- (+) Enable/Disable Debug module during SLEEP mode
- (+) Enable/Disable Debug module during STOP mode
- (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is called to increment a global variable "uwTick"
- * used as application time base.
- * @note In the default implementation, this variable is incremented each 1ms
- * in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- uwTick += uwTickFreq;
-}
-
-/**
- * @brief Provides a tick value in millisecond.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- return uwTick;
-}
-
-/**
- * @brief This function returns a tick priority.
- * @retval tick priority
- */
-uint32_t HAL_GetTickPrio(void)
-{
- return uwTickPrio;
-}
-
-/**
- * @brief Set new tick Freq.
- * @retval status
- */
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
-{
- HAL_StatusTypeDef status = HAL_OK;
- HAL_TickFreqTypeDef prevTickFreq;
-
- assert_param(IS_TICKFREQ(Freq));
-
- if (uwTickFreq != Freq)
- {
- /* Back up uwTickFreq frequency */
- prevTickFreq = uwTickFreq;
-
- /* Update uwTickFreq global variable used by HAL_InitTick() */
- uwTickFreq = Freq;
-
- /* Apply the new tick Freq */
- status = HAL_InitTick(uwTickPrio);
-
- if (status != HAL_OK)
- {
- /* Restore previous tick frequency */
- uwTickFreq = prevTickFreq;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Return tick frequency.
- * @retval tick period in Hz
- */
-HAL_TickFreqTypeDef HAL_GetTickFreq(void)
-{
- return uwTickFreq;
-}
-
-/**
- * @brief This function provides minimum delay (in milliseconds) based
- * on variable incremented.
- * @note In the default implementation , SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals where uwTick
- * is incremented.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-__weak void HAL_Delay(uint32_t Delay)
-{
- uint32_t tickstart = HAL_GetTick();
- uint32_t wait = Delay;
-
- /* Add a freq to guarantee minimum wait */
- if (wait < HAL_MAX_DELAY)
- {
- wait += (uint32_t)(uwTickFreq);
- }
-
- while ((HAL_GetTick() - tickstart) < wait)
- {
- }
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the SysTick interrupt will be disabled and so Tick increment
- * is suspended.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_SuspendTick(void)
-{
- /* Disable SysTick Interrupt */
- CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Resume Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the SysTick interrupt will be enabled and so Tick increment
- * is resumed.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_ResumeTick(void)
-{
- /* Enable SysTick Interrupt */
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Returns the HAL revision
- * @retval version 0xXYZR (8bits for each decimal, R for RC)
- */
-uint32_t HAL_GetHalVersion(void)
-{
- return __STM32F1xx_HAL_VERSION;
-}
-
-/**
- * @brief Returns the device revision identifier.
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval Device revision identifier
- */
-uint32_t HAL_GetREVID(void)
-{
- return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
- * @brief Returns the device identifier.
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval Device identifier
- */
-uint32_t HAL_GetDEVID(void)
-{
- return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Returns first word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw0(void)
-{
- return(READ_REG(*((uint32_t *)UID_BASE)));
-}
-
-/**
- * @brief Returns second word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw1(void)
-{
- return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
-}
-
-/**
- * @brief Returns third word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw2(void)
-{
- return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
-}
-
-/**
- * @brief Enable the Debug Module during SLEEP mode
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * Note: On all STM32F1 devices:
- * If the system tick timer interrupt is enabled during the Stop mode
- * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
- * the system from Stop mode.
- * Workaround: To debug the Stop mode, disable the system tick timer
- * interrupt.
- * Refer to errata sheet of these devices for more details.
- * Note: On all STM32F1 devices:
- * If the system tick timer interrupt is enabled during the Stop mode
- * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
- * the system from Stop mode.
- * Workaround: To debug the Stop mode, disable the system tick timer
- * interrupt.
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
deleted file mode 100644
index a89150a..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
+++ /dev/null
@@ -1,505 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_cortex.c
- * @author MCD Application Team
- * @brief CORTEX HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the CORTEX:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
-
- [..]
- *** How to configure Interrupts using CORTEX HAL driver ***
- ===========================================================
- [..]
- This section provides functions allowing to configure the NVIC interrupts (IRQ).
- The Cortex-M3 exceptions are managed by CMSIS functions.
-
- (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
- function according to the following table.
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
- (#) please refer to programming manual for details in how to configure priority.
-
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
- The pending IRQ priority will be managed only by the sub priority.
-
- -@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest preemption priority
- (+@) Lowest sub priority
- (+@) Lowest hardware priority (IRQ number)
-
- [..]
- *** How to configure Systick using CORTEX HAL driver ***
- ========================================================
- [..]
- Setup SysTick Timer for time base.
-
- (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
- is a CMSIS function that:
- (++) Configures the SysTick Reload register with value passed as function parameter.
- (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
- (++) Resets the SysTick Counter register.
- (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
- (++) Enables the SysTick Interrupt.
- (++) Starts the SysTick Counter.
-
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
- __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
- HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
- inside the stm32f1xx_hal_cortex.h file.
-
- (+) You can change the SysTick IRQ priority by calling the
- HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
- call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
- (+) To adjust the SysTick time base, use the following formula:
-
- Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
- (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
- (++) Reload Value should not exceed 0xFFFFFF
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CORTEX CORTEX
- * @brief CORTEX HAL module driver
- * @{
- */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides the CORTEX HAL driver functions allowing to configure Interrupts
- Systick functionalities
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Sets the priority grouping field (preemption priority and subpriority)
- * using the required unlock sequence.
- * @param PriorityGroup: The priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
- * 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
- * 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
- * @brief Sets the priority of an interrupt.
- * @param IRQn: External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
- * @param PreemptPriority: The preemption priority for the IRQn channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority
- * @param SubPriority: the subpriority level for the IRQ channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t prioritygroup = 0x00U;
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
- * @brief Enables a device specific interrupt in the NVIC interrupt controller.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
-}
-
-/**
- * @brief Disables a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval None
- */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Disable interrupt */
- NVIC_DisableIRQ(IRQn);
-}
-
-/**
- * @brief Initiates a system reset request to reset the MCU.
- * @retval None
- */
-void HAL_NVIC_SystemReset(void)
-{
- /* System Reset */
- NVIC_SystemReset();
-}
-
-/**
- * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- * Counter is in free running mode to generate periodic interrupts.
- * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- return SysTick_Config(TicksNumb);
-}
-/**
- * @}
- */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- * @brief Cortex control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK, MPU) functionalities.
-
-
-@endverbatim
- * @{
- */
-
-#if (__MPU_PRESENT == 1U)
-/**
- * @brief Disables the MPU
- * @retval None
- */
-void HAL_MPU_Disable(void)
-{
- /* Make sure outstanding transfers are done */
- __DMB();
-
- /* Disable fault exceptions */
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Disable the MPU and clear the control register*/
- MPU->CTRL = 0U;
-}
-
-/**
- * @brief Enable the MPU.
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged access to the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
- /* Enable fault exceptions */
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Ensure MPU setting take effects */
- __DSB();
- __ISB();
-}
-
-/**
- * @brief Initializes and configures the Region and the memory to be protected.
- * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
- * the initialization and configuration information.
- * @retval None
- */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
- /* Check the parameters */
- assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
- assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
- /* Set the Region number */
- MPU->RNR = MPU_Init->Number;
-
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00U;
- MPU->RASR = 0x00U;
- }
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
- * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
- */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
- /* Get the PRIGROUP[10:8] field value */
- return NVIC_GetPriorityGrouping();
-}
-
-/**
- * @brief Gets the priority of an interrupt.
- * @param IRQn: External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @param PriorityGroup: the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
- * 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
- * 0 bits for subpriority
- * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
- * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
- * @retval None
- */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
- NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
- * @brief Sets Pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval None
- */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Set interrupt pending */
- NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Gets Pending Interrupt (reads the pending register in the NVIC
- * and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Return 1 if pending else 0 */
- return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval None
- */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Clear pending interrupt */
- NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
- * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Return 1 if active else 0 */
- return NVIC_GetActive(IRQn);
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
- if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
- {
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
- }
- else
- {
- SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
- }
-}
-
-/**
- * @brief This function handles SYSTICK interrupt request.
- * @retval None
- */
-void HAL_SYSTICK_IRQHandler(void)
-{
- HAL_SYSTICK_Callback();
-}
-
-/**
- * @brief SYSTICK callback.
- * @retval None
- */
-__weak void HAL_SYSTICK_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SYSTICK_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
deleted file mode 100644
index c9bc061..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_dma.c
- * @author MCD Application Team
- * @brief DMA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access (DMA) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and errors functions
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable and configure the peripheral to be connected to the DMA Channel
- (except for internal SRAM / FLASH memories: no initialization is
- necessary). Please refer to the Reference manual for connection between peripherals
- and DMA requests.
-
- (#) For a given Channel, program the required configuration through the following parameters:
- Channel request, Transfer Direction, Source and Destination data formats,
- Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
- using HAL_DMA_Init() function.
-
- (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
- detection.
-
- (#) Use HAL_DMA_Abort() function to abort the current transfer
-
- -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
- case a fixed Timeout can be configured by User depending from his application.
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred.
- In this case the DMA interrupt is configured
- (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback and
- XferErrorCallback (i.e. a member of DMA handle structure).
-
- *** DMA HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DMA HAL driver.
-
- (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
- (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
- (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
- (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
- (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
-
- [..]
- (@) You can refer to the DMA HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMA DMA
- * @brief DMA HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @{
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize the DMA Channel source
- and destination addresses, incrementation and data sizes, transfer direction,
- circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
- [..]
- The HAL_DMA_Init() function follows the DMA configuration procedures as described in
- reference manual.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DMA according to the specified
- * parameters in the DMA_InitTypeDef and initialize the associated handle.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
- uint32_t tmp = 0U;
-
- /* Check the DMA handle allocation */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
- assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
- assert_param(IS_DMA_MODE(hdma->Init.Mode));
- assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
-#if defined (DMA2)
- /* calculation of the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
- {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA1;
- }
- else
- {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA2;
- }
-#else
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA1;
-#endif /* DMA2 */
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Get the CR register value */
- tmp = hdma->Instance->CCR;
-
- /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
- DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
- DMA_CCR_DIR));
-
- /* Prepare the DMA Channel configuration */
- tmp |= hdma->Init.Direction |
- hdma->Init.PeriphInc | hdma->Init.MemInc |
- hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
- hdma->Init.Mode | hdma->Init.Priority;
-
- /* Write to DMA Channel CR register */
- hdma->Instance->CCR = tmp;
-
- /* Initialise the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
- /* Allocate lock resource and initialize it */
- hdma->Lock = HAL_UNLOCKED;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the DMA peripheral.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
- /* Check the DMA handle allocation */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* Disable the selected DMA Channelx */
- __HAL_DMA_DISABLE(hdma);
-
- /* Reset DMA Channel control register */
- hdma->Instance->CCR = 0U;
-
- /* Reset DMA Channel Number of Data to Transfer register */
- hdma->Instance->CNDTR = 0U;
-
- /* Reset DMA Channel peripheral address register */
- hdma->Instance->CPAR = 0U;
-
- /* Reset DMA Channel memory address register */
- hdma->Instance->CMAR = 0U;
-
-#if defined (DMA2)
- /* calculation of the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
- {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA1;
- }
- else
- {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA2;
- }
-#else
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA1;
-#endif /* DMA2 */
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
-
- /* Clean all callbacks */
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
-
- /* Reset the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Reset the DMA state */
- hdma->State = HAL_DMA_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @brief Input and Output operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the source, destination address and data length and Start DMA transfer
- (+) Configure the source, destination address and data length and
- Start DMA transfer with interrupt
- (+) Abort DMA transfer
- (+) Poll for transfer complete
- (+) Handle DMA interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the DMA Transfer.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length & clear flags*/
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
- status = HAL_BUSY;
- }
- return status;
-}
-
-/**
- * @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length & clear flags*/
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the transfer complete interrupt */
- /* Enable the transfer Error interrupt */
- if(NULL != hdma->XferHalfCpltCallback)
- {
- /* Enable the Half transfer complete interrupt as well */
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
- }
- else
- {
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
- }
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Remain BUSY */
- status = HAL_BUSY;
- }
- return status;
-}
-
-/**
- * @brief Abort the DMA Transfer.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(hdma->State != HAL_DMA_STATE_BUSY)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- else
-
- {
- /* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
- }
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief Aborts the DMA Transfer in Interrupt mode.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- status = HAL_ERROR;
- }
- else
- {
- /* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* Clear all flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Call User Abort callback */
- if(hdma->XferAbortCallback != NULL)
- {
- hdma->XferAbortCallback(hdma);
- }
- }
- return status;
-}
-
-/**
- * @brief Polling for transfer complete.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CompleteLevel: Specifies the DMA level complete.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
-{
- uint32_t temp;
- uint32_t tickstart = 0U;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- __HAL_UNLOCK(hdma);
- return HAL_ERROR;
- }
-
- /* Polling mode not supported in circular mode */
- if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- /* Get the level transfer complete flag */
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
- {
- /* Transfer Complete flag */
- temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
- }
- else
- {
- /* Half Transfer Complete flag */
- temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
- {
- if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
-
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
-
- /* Change the DMA state */
- hdma->State= HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- }
- }
-
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
- {
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
- /* The selected Channelx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- hdma->State = HAL_DMA_STATE_READY;
- }
- else
- {
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handles DMA interrupt request.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- uint32_t flag_it = hdma->DmaBaseAddress->ISR;
- uint32_t source_it = hdma->Instance->CCR;
-
- /* Half Transfer Complete Interrupt management ******************************/
- if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
- {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the half transfer interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- }
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* DMA peripheral state is not updated in Half Transfer */
- /* but in Transfer Complete case */
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
-
- /* Transfer Complete Interrupt management ***********************************/
- else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
- {
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the transfer complete and error interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
- }
-
- /* Transfer Error Interrupt management **************************************/
- else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Disable ALL DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if (hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- return;
-}
-
-/**
- * @brief Register callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CallbackID: User Callback identifer
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback: pointer to private callbacsk function which has pointer to
- * a DMA_HandleTypeDef structure as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = pCallback;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief UnRegister callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CallbackID: User Callback identifer
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ALL_CB_ID:
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA state
- (+) Get error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the DMA hande state.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL state
- */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
- /* Return DMA handle state */
- return hdma->State;
-}
-
-/**
- * @brief Return the DMA error code.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval DMA Error Code
- */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
- return hdma->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Private_Functions
- * @{
- */
-
-/**
- * @brief Sets the DMA Transfer parameter.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
-
- /* Configure DMA Channel data length */
- hdma->Instance->CNDTR = DataLength;
-
- /* Memory to Peripheral */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
- /* Configure DMA Channel destination address */
- hdma->Instance->CPAR = DstAddress;
-
- /* Configure DMA Channel source address */
- hdma->Instance->CMAR = SrcAddress;
- }
- /* Peripheral to Memory */
- else
- {
- /* Configure DMA Channel source address */
- hdma->Instance->CPAR = SrcAddress;
-
- /* Configure DMA Channel destination address */
- hdma->Instance->CMAR = DstAddress;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c
deleted file mode 100644
index 44daaff..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c
+++ /dev/null
@@ -1,559 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_exti.c
- * @author MCD Application Team
- * @brief EXTI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- @verbatim
- ==============================================================================
- ##### EXTI Peripheral features #####
- ==============================================================================
- [..]
- (+) Each Exti line can be configured within this driver.
-
- (+) Exti line can be configured in 3 different modes
- (++) Interrupt
- (++) Event
- (++) Both of them
-
- (+) Configurable Exti lines can be configured with 3 different triggers
- (++) Rising
- (++) Falling
- (++) Both of them
-
- (+) When set in interrupt mode, configurable Exti lines have two different
- interrupts pending registers which allow to distinguish which transition
- occurs:
- (++) Rising edge pending interrupt
- (++) Falling
-
- (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
- be selected through multiplexer.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
- (++) Choose the interrupt line number by setting "Line" member from
- EXTI_ConfigTypeDef structure.
- (++) Configure the interrupt and/or event mode using "Mode" member from
- EXTI_ConfigTypeDef structure.
- (++) For configurable lines, configure rising and/or falling trigger
- "Trigger" member from EXTI_ConfigTypeDef structure.
- (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
- member from GPIO_InitTypeDef structure.
-
- (#) Get current Exti configuration of a dedicated line using
- HAL_EXTI_GetConfigLine().
- (++) Provide exiting handle as parameter.
- (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
-
- (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
- (++) Provide exiting handle as parameter.
-
- (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
- (++) Provide exiting handle as first parameter.
- (++) Provide which callback will be registered using one value from
- EXTI_CallbackIDTypeDef.
- (++) Provide callback function pointer.
-
- (#) Get interrupt pending bit using HAL_EXTI_GetPending().
-
- (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
-
- (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-/** MISRA C:2012 deviation rule has been granted for following rule:
- * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
- * of bounds [0,3] in following API :
- * HAL_EXTI_SetConfigLine
- * HAL_EXTI_GetConfigLine
- * HAL_EXTI_ClearConfigLine
- */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup EXTI_Exported_Functions
- * @{
- */
-
-/** @addtogroup EXTI_Exported_Functions_Group1
- * @brief Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @param pExtiConfig Pointer on EXTI configuration to be set.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
-
- /* Check null pointer */
- if ((hexti == NULL) || (pExtiConfig == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(pExtiConfig->Line));
- assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
-
- /* Assign line number to handle */
- hexti->Line = pExtiConfig->Line;
-
- /* Compute line mask */
- linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
- maskline = (1uL << linepos);
-
- /* Configure triggers for configurable lines */
- if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
- {
- assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
-
- /* Configure rising trigger */
- /* Mask or set line */
- if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
- {
- EXTI->RTSR |= maskline;
- }
- else
- {
- EXTI->RTSR &= ~maskline;
- }
-
- /* Configure falling trigger */
- /* Mask or set line */
- if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
- {
- EXTI->FTSR |= maskline;
- }
- else
- {
- EXTI->FTSR &= ~maskline;
- }
-
-
- /* Configure gpio port selection in case of gpio exti line */
- if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
- {
- assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = AFIO->EXTICR[linepos >> 2u];
- regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- AFIO->EXTICR[linepos >> 2u] = regval;
- }
- }
-
- /* Configure interrupt mode : read current mode */
- /* Mask or set line */
- if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
- {
- EXTI->IMR |= maskline;
- }
- else
- {
- EXTI->IMR &= ~maskline;
- }
-
- /* Configure event mode : read current mode */
- /* Mask or set line */
- if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
- {
- EXTI->EMR |= maskline;
- }
- else
- {
- EXTI->EMR &= ~maskline;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Get configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @param pExtiConfig Pointer on structure to store Exti configuration.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
-
- /* Check null pointer */
- if ((hexti == NULL) || (pExtiConfig == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameter */
- assert_param(IS_EXTI_LINE(hexti->Line));
-
- /* Store handle line number to configuration structure */
- pExtiConfig->Line = hexti->Line;
-
- /* Compute line mask */
- linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
- maskline = (1uL << linepos);
-
- /* 1] Get core mode : interrupt */
-
- /* Check if selected line is enable */
- if ((EXTI->IMR & maskline) != 0x00u)
- {
- pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
- }
- else
- {
- pExtiConfig->Mode = EXTI_MODE_NONE;
- }
-
- /* Get event mode */
- /* Check if selected line is enable */
- if ((EXTI->EMR & maskline) != 0x00u)
- {
- pExtiConfig->Mode |= EXTI_MODE_EVENT;
- }
-
- /* 2] Get trigger for configurable lines : rising */
- if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
- {
- /* Check if configuration of selected line is enable */
- if ((EXTI->RTSR & maskline) != 0x00u)
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
- }
- else
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- }
-
- /* Get falling configuration */
- /* Check if configuration of selected line is enable */
- if ((EXTI->FTSR & maskline) != 0x00u)
- {
- pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
- }
-
- /* Get Gpio port selection for gpio lines */
- if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
- {
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = AFIO->EXTICR[linepos >> 2u];
- pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
- }
- else
- {
- pExtiConfig->GPIOSel = 0x00u;
- }
- }
- else
- {
- /* No Trigger selected */
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- pExtiConfig->GPIOSel = 0x00u;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Clear whole configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
-{
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
-
- /* Check null pointer */
- if (hexti == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameter */
- assert_param(IS_EXTI_LINE(hexti->Line));
-
- /* compute line mask */
- linepos = (hexti->Line & EXTI_PIN_MASK);
- maskline = (1uL << linepos);
-
- /* 1] Clear interrupt mode */
- EXTI->IMR = (EXTI->IMR & ~maskline);
-
- /* 2] Clear event mode */
- EXTI->EMR = (EXTI->EMR & ~maskline);
-
- /* 3] Clear triggers in case of configurable lines */
- if ((hexti->Line & EXTI_CONFIG) != 0x00u)
- {
- EXTI->RTSR = (EXTI->RTSR & ~maskline);
- EXTI->FTSR = (EXTI->FTSR & ~maskline);
-
- /* Get Gpio port selection for gpio lines */
- if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
- {
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = AFIO->EXTICR[linepos >> 2u];
- regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- AFIO->EXTICR[linepos >> 2u] = regval;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Register callback for a dedicated Exti line.
- * @param hexti Exti handle.
- * @param CallbackID User callback identifier.
- * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
- * @param pPendingCbfn function pointer to be stored as callback.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- switch (CallbackID)
- {
- case HAL_EXTI_COMMON_CB_ID:
- hexti->PendingCallback = pPendingCbfn;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Store line number as handle private field.
- * @param hexti Exti handle.
- * @param ExtiLine Exti line number.
- * This parameter can be from 0 to @ref EXTI_LINE_NB.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(ExtiLine));
-
- /* Check null pointer */
- if (hexti == NULL)
- {
- return HAL_ERROR;
- }
- else
- {
- /* Store line number as handle private field */
- hexti->Line = ExtiLine;
-
- return HAL_OK;
- }
-}
-
-/**
- * @}
- */
-
-/** @addtogroup EXTI_Exported_Functions_Group2
- * @brief EXTI IO functions.
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Handle EXTI interrupt request.
- * @param hexti Exti handle.
- * @retval none.
- */
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
-{
- uint32_t regval;
- uint32_t maskline;
-
- /* Compute line mask */
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- /* Get pending bit */
- regval = (EXTI->PR & maskline);
- if (regval != 0x00u)
- {
- /* Clear pending bit */
- EXTI->PR = maskline;
-
- /* Call callback */
- if (hexti->PendingCallback != NULL)
- {
- hexti->PendingCallback();
- }
- }
-}
-
-/**
- * @brief Get interrupt pending bit of a dedicated line.
- * @param hexti Exti handle.
- * @param Edge Specify which pending edge as to be checked.
- * This parameter can be one of the following values:
- * @arg @ref EXTI_TRIGGER_RISING_FALLING
- * This parameter is kept for compatibility with other series.
- * @retval 1 if interrupt is pending else 0.
- */
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
- uint32_t regval;
- uint32_t maskline;
- uint32_t linepos;
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
- assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
- /* Compute line mask */
- linepos = (hexti->Line & EXTI_PIN_MASK);
- maskline = (1uL << linepos);
-
- /* return 1 if bit is set else 0 */
- regval = ((EXTI->PR & maskline) >> linepos);
- return regval;
-}
-
-/**
- * @brief Clear interrupt pending bit of a dedicated line.
- * @param hexti Exti handle.
- * @param Edge Specify which pending edge as to be clear.
- * This parameter can be one of the following values:
- * @arg @ref EXTI_TRIGGER_RISING_FALLING
- * This parameter is kept for compatibility with other series.
- * @retval None.
- */
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
- uint32_t maskline;
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
- assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
- /* Compute line mask */
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- /* Clear Pending bit */
- EXTI->PR = maskline;
-}
-
-/**
- * @brief Generate a software interrupt for a dedicated line.
- * @param hexti Exti handle.
- * @retval None.
- */
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
-{
- uint32_t maskline;
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-
- /* Compute line mask */
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- /* Generate Software interrupt */
- EXTI->SWIER = maskline;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_EXTI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c
deleted file mode 100644
index 50abf92..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c
+++ /dev/null
@@ -1,967 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_flash.c
- * @author MCD Application Team
- * @brief FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the internal FLASH memory:
- * + Program operations functions
- * + Memory Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### FLASH peripheral features #####
- ==============================================================================
- [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
- to the Flash memory. It implements the erase and program Flash memory operations
- and the read and write protection mechanisms.
-
- [..] The Flash memory interface accelerates code execution with a system of instruction
- prefetch.
-
- [..] The FLASH main features are:
- (+) Flash memory read operations
- (+) Flash memory program/erase operations
- (+) Read / write protections
- (+) Prefetch on I-Code
- (+) Option Bytes programming
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver provides functions and macros to configure and program the FLASH
- memory of all STM32F1xx devices.
-
- (#) FLASH Memory I/O Programming functions: this group includes all needed
- functions to erase and program the main memory:
- (++) Lock and Unlock the FLASH interface
- (++) Erase function: Erase page, erase all pages
- (++) Program functions: half word, word and doubleword
- (#) FLASH Option Bytes Programming functions: this group includes all needed
- functions to manage the Option Bytes:
- (++) Lock and Unlock the Option Bytes
- (++) Set/Reset the write protection
- (++) Set the Read protection Level
- (++) Program the user Option Bytes
- (++) Launch the Option Bytes loader
- (++) Erase Option Bytes
- (++) Program the data Option Bytes
- (++) Get the Write protection.
- (++) Get the user option bytes.
-
- (#) Interrupts and flags management functions : this group
- includes all needed functions to:
- (++) Handle FLASH interrupts
- (++) Wait for last FLASH operation according to its status
- (++) Get error flag status
-
- [..] In addition to these function, this driver includes a set of macros allowing
- to handle the following operations:
-
- (+) Set/Get the latency
- (+) Enable/Disable the prefetch buffer
- (+) Enable/Disable the half cycle access
- (+) Enable/Disable the FLASH interrupts
- (+) Monitor the FLASH flags status
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @defgroup FLASH FLASH
- * @brief FLASH HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macro ---------------------------- ---------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-/* Variables used for Erase pages under interruption*/
-FLASH_ProcessTypeDef pFlash;
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
-static void FLASH_SetErrorCode(void);
-extern void FLASH_PageErase(uint32_t PageAddress);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
- * @{
- */
-
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- * @brief Programming operation functions
- *
-@verbatim
-@endverbatim
- * @{
- */
-
-/**
- * @brief Program halfword, word or double word at a specified address
- * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @note FLASH should be previously erased before new programmation (only exception to this
- * is when 0x0000 is programmed)
- *
- * @param TypeProgram: Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: Specifies the address to be programmed.
- * @param Data: Specifies the data to be programmed
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint8_t index = 0;
- uint8_t nbiterations = 0;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-#if defined(FLASH_BANK2_END)
- if(Address <= FLASH_BANK1_END)
- {
-#endif /* FLASH_BANK2_END */
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-#if defined(FLASH_BANK2_END)
- }
- else
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_BANK2_END */
-
- if(status == HAL_OK)
- {
- if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
- {
- /* Program halfword (16-bit) at a specified address. */
- nbiterations = 1U;
- }
- else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
- {
- /* Program word (32-bit = 2*16-bit) at a specified address. */
- nbiterations = 2U;
- }
- else
- {
- /* Program double word (64-bit = 4*16-bit) at a specified address. */
- nbiterations = 4U;
- }
-
- for (index = 0U; index < nbiterations; index++)
- {
- FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
-
-#if defined(FLASH_BANK2_END)
- if(Address <= FLASH_BANK1_END)
- {
-#endif /* FLASH_BANK2_END */
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
-#if defined(FLASH_BANK2_END)
- }
- else
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
- }
-#endif /* FLASH_BANK2_END */
- /* In case of error, stop programation procedure */
- if (status != HAL_OK)
- {
- break;
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Program halfword, word or double word at a specified address with interrupt enabled.
- * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param TypeProgram: Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: Specifies the address to be programmed.
- * @param Data: Specifies the data to be programmed
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-#if defined(FLASH_BANK2_END)
- /* If procedure already ongoing, reject the next one */
- if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- return HAL_ERROR;
- }
-
- if(Address <= FLASH_BANK1_END)
- {
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);
-
- }else
- {
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
- }
-#else
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-#endif /* FLASH_BANK2_END */
-
- pFlash.Address = Address;
- pFlash.Data = Data;
-
- if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
- /* Program halfword (16-bit) at a specified address. */
- pFlash.DataRemaining = 1U;
- }
- else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
- /* Program word (32-bit : 2*16-bit) at a specified address. */
- pFlash.DataRemaining = 2U;
- }
- else
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
- /* Program double word (64-bit : 4*16-bit) at a specified address. */
- pFlash.DataRemaining = 4U;
- }
-
- /* Program halfword (16-bit) at a specified address. */
- FLASH_Program_HalfWord(Address, (uint16_t)Data);
-
- return status;
-}
-
-/**
- * @brief This function handles FLASH interrupt request.
- * @retval None
- */
-void HAL_FLASH_IRQHandler(void)
-{
- uint32_t addresstmp = 0U;
-
- /* Check FLASH operation error flags */
-#if defined(FLASH_BANK2_END)
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
- (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
-#else
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
-#endif /* FLASH_BANK2_END */
- {
- /* Return the faulty address */
- addresstmp = pFlash.Address;
- /* Reset address */
- pFlash.Address = 0xFFFFFFFFU;
-
- /* Save the Error code */
- FLASH_SetErrorCode();
-
- /* FLASH error interrupt user callback */
- HAL_FLASH_OperationErrorCallback(addresstmp);
-
- /* Stop the procedure ongoing */
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-
- /* Check FLASH End of Operation flag */
-#if defined(FLASH_BANK2_END)
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
-#else
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-#endif /* FLASH_BANK2_END */
-
- /* Process can continue only if no error detected */
- if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
- {
- /* Nb of pages to erased can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still pages to erase */
- if(pFlash.DataRemaining != 0U)
- {
- addresstmp = pFlash.Address;
- /*Indicate user which sector has been erased */
- HAL_FLASH_EndOfOperationCallback(addresstmp);
-
- /*Increment sector number*/
- addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
- pFlash.Address = addresstmp;
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
-
- FLASH_PageErase(addresstmp);
- }
- else
- {
- /* No more pages to Erase, user callback can be called. */
- /* Reset Sector and stop Erase pages procedure */
- pFlash.Address = addresstmp = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(addresstmp);
- }
- }
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
- {
- /* Operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
-
-#if defined(FLASH_BANK2_END)
- /* Stop Mass Erase procedure if no pending mass erase on other bank */
- if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER))
- {
-#endif /* FLASH_BANK2_END */
- /* MassErase ended. Return the selected bank */
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0U);
-
- /* Stop Mass Erase procedure*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-#if defined(FLASH_BANK2_END)
- }
-#endif /* FLASH_BANK2_END */
- else
- {
- /* Nb of 16-bit data to program can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0U)
- {
- /* Increment address to 16-bit */
- pFlash.Address += 2U;
- addresstmp = pFlash.Address;
-
- /* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16U);
-
- /* Operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
-
- /*Program halfword (16-bit) at a specified address.*/
- FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
- }
- else
- {
- /* Program ended. Return the selected address */
- /* FLASH EOP interrupt user callback */
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
- }
- else
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
- }
-
- /* Reset Address and stop Program procedure */
- pFlash.Address = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
- }
- }
-
-#if defined(FLASH_BANK2_END)
- /* Check FLASH End of Operation flag */
- if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
-
- /* Process can continue only if no error detected */
- if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
- {
- /* Nb of pages to erased can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still pages to erase*/
- if(pFlash.DataRemaining != 0U)
- {
- /* Indicate user which page address has been erased*/
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-
- /* Increment page address to next page */
- pFlash.Address += FLASH_PAGE_SIZE;
- addresstmp = pFlash.Address;
-
- /* Operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
-
- FLASH_PageErase(addresstmp);
- }
- else
- {
- /*No more pages to Erase*/
-
- /*Reset Address and stop Erase pages procedure*/
- pFlash.Address = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
- }
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
- {
- /* Operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
-
- if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER))
- {
- /* MassErase ended. Return the selected bank*/
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0U);
-
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
- else
- {
- /* Nb of 16-bit data to program can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0U)
- {
- /* Increment address to 16-bit */
- pFlash.Address += 2U;
- addresstmp = pFlash.Address;
-
- /* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16U);
-
- /* Operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
-
- /*Program halfword (16-bit) at a specified address.*/
- FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
- }
- else
- {
- /*Program ended. Return the selected address*/
- /* FLASH EOP interrupt user callback */
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U);
- }
- else
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U);
- }
-
- /* Reset Address and stop Program procedure*/
- pFlash.Address = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
- }
- }
-#endif
-
- if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
- {
-#if defined(FLASH_BANK2_END)
- /* Operation is completed, disable the PG, PER and MER Bits for both bank */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
- CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
-
- /* Disable End of FLASH Operation and Error source interrupts for both banks */
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
-#else
- /* Operation is completed, disable the PG, PER and MER Bits */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
-
- /* Disable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-#endif /* FLASH_BANK2_END */
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- }
-}
-
-/**
- * @brief FLASH end of operation interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
- * - Mass Erase: No return value expected
- * - Pages Erase: Address of the page which has been erased
- * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
- * - Program: Address which was selected for data program
- * @retval none
- */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief FLASH operation error interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
- * - Mass Erase: No return value expected
- * - Pages Erase: Address of the page which returned an error
- * - Program: Address which was selected for data program
- * @retval none
- */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_OperationErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- memory operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlock the FLASH control register access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
- {
- /* Authorize the FLASH Registers access */
- WRITE_REG(FLASH->KEYR, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR, FLASH_KEY2);
-
- /* Verify Flash is unlocked */
- if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
- {
- status = HAL_ERROR;
- }
- }
-#if defined(FLASH_BANK2_END)
- if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET)
- {
- /* Authorize the FLASH BANK2 Registers access */
- WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
-
- /* Verify Flash BANK2 is unlocked */
- if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET)
- {
- status = HAL_ERROR;
- }
- }
-#endif /* FLASH_BANK2_END */
-
- return status;
-}
-
-/**
- * @brief Locks the FLASH control register access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- SET_BIT(FLASH->CR, FLASH_CR_LOCK);
-
-#if defined(FLASH_BANK2_END)
- /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
- SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
-
-#endif /* FLASH_BANK2_END */
- return HAL_OK;
-}
-
-/**
- * @brief Unlock the FLASH Option Control Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
- if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
- {
- /* Authorizes the Option Byte register programming */
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Lock the FLASH Option Control Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
- /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
-
- return HAL_OK;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @note This function will reset automatically the MCU.
- * @retval None
- */
-void HAL_FLASH_OB_Launch(void)
-{
- /* Initiates a system reset request to launch the option byte loading */
- HAL_NVIC_SystemReset();
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
- * @brief Peripheral errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Errors functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time errors of the FLASH peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Get the specific FLASH error flag.
- * @retval FLASH_ErrorCode The returned value can be:
- * @ref FLASH_Error_Codes
- */
-uint32_t HAL_FLASH_GetError(void)
-{
- return pFlash.ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
- * @brief Program a half-word (16-bit) at a specified address.
- * @param Address specify the address to be programmed.
- * @param Data specify the data to be programmed.
- * @retval None
- */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
-{
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-#if defined(FLASH_BANK2_END)
- if(Address <= FLASH_BANK1_END)
- {
-#endif /* FLASH_BANK2_END */
- /* Proceed to program the new data */
- SET_BIT(FLASH->CR, FLASH_CR_PG);
-#if defined(FLASH_BANK2_END)
- }
- else
- {
- /* Proceed to program the new data */
- SET_BIT(FLASH->CR2, FLASH_CR2_PG);
- }
-#endif /* FLASH_BANK2_END */
-
- /* Write data in the address */
- *(__IO uint16_t*)Address = Data;
-}
-
-/**
- * @brief Wait for a FLASH operation to complete.
- * @param Timeout maximum flash operation timeout
- * @retval HAL Status
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
-
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
- __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
- __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
- {
- /*Save the error code*/
- FLASH_SetErrorCode();
- return HAL_ERROR;
- }
-
- /* There is no error flag set */
- return HAL_OK;
-}
-
-#if defined(FLASH_BANK2_END)
-/**
- * @brief Wait for a FLASH BANK2 operation to complete.
- * @param Timeout maximum flash operation timeout
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
-{
- /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
- flag will be set */
-
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2))
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
- }
-
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
- {
- /*Save the error code*/
- FLASH_SetErrorCode();
- return HAL_ERROR;
- }
-
- /* If there is an error flag set */
- return HAL_OK;
-
-}
-#endif /* FLASH_BANK2_END */
-
-/**
- * @brief Set the specific FLASH error flag.
- * @retval None
- */
-static void FLASH_SetErrorCode(void)
-{
- uint32_t flags = 0U;
-
-#if defined(FLASH_BANK2_END)
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
-#else
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
-#endif /* FLASH_BANK2_END */
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-#if defined(FLASH_BANK2_END)
- flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
-#else
- flags |= FLASH_FLAG_WRPERR;
-#endif /* FLASH_BANK2_END */
- }
-#if defined(FLASH_BANK2_END)
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
-#else
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
-#endif /* FLASH_BANK2_END */
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
-#if defined(FLASH_BANK2_END)
- flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
-#else
- flags |= FLASH_FLAG_PGERR;
-#endif /* FLASH_BANK2_END */
- }
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
- }
-
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG(flags);
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
deleted file mode 100644
index ebd6f8b..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
+++ /dev/null
@@ -1,1127 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_flash_ex.c
- * @author MCD Application Team
- * @brief Extended FLASH HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the FLASH peripheral:
- * + Extended Initialization/de-initialization functions
- * + Extended I/O operation functions
- * + Extended Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### Flash peripheral extended features #####
- ==============================================================================
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the FLASH memory
- of all STM32F1xxx devices. It includes
-
- (++) Set/Reset the write protection
- (++) Program the user Option Bytes
- (++) Get the Read protection Level
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @addtogroup FLASH
- * @{
- */
-/** @addtogroup FLASH_Private_Variables
- * @{
- */
-/* Variables used for Erase pages under interruption*/
-extern FLASH_ProcessTypeDef pFlash;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx FLASHEx
- * @brief FLASH HAL Extension module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
- * @{
- */
-#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos
-#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos
-#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-/* Erase operations */
-static void FLASH_MassErase(uint32_t Banks);
-void FLASH_PageErase(uint32_t PageAddress);
-
-/* Option bytes control */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
-static uint32_t FLASH_OB_GetWRP(void);
-static uint32_t FLASH_OB_GetRDP(void);
-static uint8_t FLASH_OB_GetUser(void);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
- * @{
- */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
- * @brief FLASH Memory Erasing functions
- *
-@verbatim
- ==============================================================================
- ##### FLASH Erasing Programming functions #####
- ==============================================================================
-
- [..] The FLASH Memory Erasing functions, includes the following functions:
- (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
- (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
- is called with parameter 0xFFFFFFFF
-
- [..] Any operation of erase should follow these steps:
- (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
- program memory access.
- (#) Call the desired function to erase page.
- (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
- (recommended to protect the FLASH memory against possible unwanted operation).
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages
- * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
- * must be called before.
- * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @param[out] PageError pointer to variable that
- * contains the configuration information on faulty page in case of error
- * (0xFFFFFFFF means that all the pages have been correctly erased)
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t address = 0U;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
-#if defined(FLASH_BANK2_END)
- if (pEraseInit->Banks == FLASH_BANK_BOTH)
- {
- /* Mass Erase requested for Bank1 and Bank2 */
- /* Wait for last operation to be completed */
- if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
- (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
- {
- /*Mass erase to be done*/
- FLASH_MassErase(FLASH_BANK_BOTH);
-
- /* Wait for last operation to be completed */
- if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
- (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
- {
- status = HAL_OK;
- }
-
- /* If the erase operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
- }
- }
- else if (pEraseInit->Banks == FLASH_BANK_2)
- {
- /* Mass Erase requested for Bank2 */
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Mass erase to be done*/
- FLASH_MassErase(FLASH_BANK_2);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
- }
- }
- else
-#endif /* FLASH_BANK2_END */
- {
- /* Mass Erase requested for Bank1 */
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Mass erase to be done*/
- FLASH_MassErase(FLASH_BANK_1);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
- }
- }
- }
- else
- {
- /* Page Erase is requested */
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
-
-#if defined(FLASH_BANK2_END)
- /* Page Erase requested on address located on bank2 */
- if(pEraseInit->PageAddress > FLASH_BANK1_END)
- {
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFFU;
-
- /* Erase by page by page to be done*/
- for(address = pEraseInit->PageAddress;
- address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
- address += FLASH_PAGE_SIZE)
- {
- FLASH_PageErase(address);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
-
- if (status != HAL_OK)
- {
- /* In case of error, stop erase procedure and return the faulty address */
- *PageError = address;
- break;
- }
- }
- }
- }
- else
-#endif /* FLASH_BANK2_END */
- {
- /* Page Erase requested on address located on bank1 */
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFFU;
-
- /* Erase page by page to be done*/
- for(address = pEraseInit->PageAddress;
- address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
- address += FLASH_PAGE_SIZE)
- {
- FLASH_PageErase(address);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
-
- if (status != HAL_OK)
- {
- /* In case of error, stop erase procedure and return the faulty address */
- *PageError = address;
- break;
- }
- }
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
- * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
- * must be called before.
- * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* If procedure already ongoing, reject the next one */
- if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-
-#if defined(FLASH_BANK2_END)
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
-
-#endif
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /*Mass erase to be done*/
- pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
- FLASH_MassErase(pEraseInit->Banks);
- }
- else
- {
- /* Erase by page to be done*/
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
-
- pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
- pFlash.DataRemaining = pEraseInit->NbPages;
- pFlash.Address = pEraseInit->PageAddress;
-
- /*Erase 1st page and wait for IT*/
- FLASH_PageErase(pEraseInit->PageAddress);
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ==============================================================================
- ##### Option Bytes Programming functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- option bytes operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Erases the FLASH option bytes.
- * @note This functions erases all option bytes except the Read protection (RDP).
- * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
-{
- uint8_t rdptmp = OB_RDP_LEVEL_0;
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Get the actual read protection Option Byte value */
- rdptmp = FLASH_OB_GetRDP();
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* If the previous operation is completed, proceed to erase the option bytes */
- SET_BIT(FLASH->CR, FLASH_CR_OPTER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the OPTER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
-
- if(status == HAL_OK)
- {
- /* Restore the last read protection Option Byte value */
- status = FLASH_OB_RDP_LevelConfig(rdptmp);
- }
- }
-
- /* Return the erase status */
- return status;
-}
-
-/**
- * @brief Program option bytes
- * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- *
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
- /* Write protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
- {
- assert_param(IS_WRPSTATE(pOBInit->WRPState));
- if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
- {
- /* Enable of Write protection on the selected page */
- status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
- }
- else
- {
- /* Disable of Write protection on the selected page */
- status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
- }
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* Read protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
- {
- status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* USER configuration */
- if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
- {
- status = FLASH_OB_UserConfig(pOBInit->USERConfig);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* DATA configuration*/
- if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
- {
- status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Get the Option byte configuration
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval None
- */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
-
- /*Get WRP*/
- pOBInit->WRPPage = FLASH_OB_GetWRP();
-
- /*Get RDP Level*/
- pOBInit->RDPLevel = FLASH_OB_GetRDP();
-
- /*Get USER*/
- pOBInit->USERConfig = FLASH_OB_GetUser();
-}
-
-/**
- * @brief Get the Option byte user data
- * @param DATAAdress Address of the option byte DATA
- * This parameter can be one of the following values:
- * @arg @ref OB_DATA_ADDRESS_DATA0
- * @arg @ref OB_DATA_ADDRESS_DATA1
- * @retval Value programmed in USER data
- */
-uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
-{
- uint32_t value = 0;
-
- if (DATAAdress == OB_DATA_ADDRESS_DATA0)
- {
- /* Get value programmed in OB USER Data0 */
- value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
- }
- else
- {
- /* Get value programmed in OB USER Data1 */
- value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
- }
-
- return value;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Private_Functions
- * @{
- */
-
-/**
- * @brief Full erase of FLASH memory Bank
- * @param Banks Banks to be erased
- * This parameter can be one of the following values:
- * @arg @ref FLASH_BANK_1 Bank1 to be erased
- @if STM32F101xG
- * @arg @ref FLASH_BANK_2 Bank2 to be erased
- * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
- @endif
- @if STM32F103xG
- * @arg @ref FLASH_BANK_2 Bank2 to be erased
- * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
- @endif
- *
- * @retval None
- */
-static void FLASH_MassErase(uint32_t Banks)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Banks));
-
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-#if defined(FLASH_BANK2_END)
- if(Banks == FLASH_BANK_BOTH)
- {
- /* bank1 & bank2 will be erased*/
- SET_BIT(FLASH->CR, FLASH_CR_MER);
- SET_BIT(FLASH->CR2, FLASH_CR2_MER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
- }
- else if(Banks == FLASH_BANK_2)
- {
- /*Only bank2 will be erased*/
- SET_BIT(FLASH->CR2, FLASH_CR2_MER);
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
- }
- else
- {
-#endif /* FLASH_BANK2_END */
-#if !defined(FLASH_BANK2_END)
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Banks);
-#endif /* FLASH_BANK2_END */
- /* Only bank1 will be erased*/
- SET_BIT(FLASH->CR, FLASH_CR_MER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-#if defined(FLASH_BANK2_END)
- }
-#endif /* FLASH_BANK2_END */
-}
-
-/**
- * @brief Enable the write protection of the desired pages
- * @note An option byte erase is done automatically in this function.
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash page i if
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- *
- * @param WriteProtectPage specifies the page(s) to be write protected.
- * The value of this parameter depend on device used within the same series
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint16_t WRP0_Data = 0xFFFF;
-#if defined(FLASH_WRP1_WRP1)
- uint16_t WRP1_Data = 0xFFFF;
-#endif /* FLASH_WRP1_WRP1 */
-#if defined(FLASH_WRP2_WRP2)
- uint16_t WRP2_Data = 0xFFFF;
-#endif /* FLASH_WRP2_WRP2 */
-#if defined(FLASH_WRP3_WRP3)
- uint16_t WRP3_Data = 0xFFFF;
-#endif /* FLASH_WRP3_WRP3 */
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(WriteProtectPage));
-
- /* Get current write protected pages and the new pages to be protected ******/
- WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
-
-#if defined(OB_WRP_PAGES0TO15MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
-#elif defined(OB_WRP_PAGES0TO31MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
-#endif /* OB_WRP_PAGES0TO31MASK */
-
-#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
-#elif defined(OB_WRP_PAGES32TO63MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
-#endif /* OB_WRP_PAGES32TO63MASK */
-
-#if defined(OB_WRP_PAGES64TO95MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
-#endif /* OB_WRP_PAGES64TO95MASK */
-#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
-#endif /* OB_WRP_PAGES32TO47MASK */
-
-#if defined(OB_WRP_PAGES96TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO511MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
-#endif /* OB_WRP_PAGES96TO127MASK */
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* To be able to write again option byte, need to perform a option byte erase */
- status = HAL_FLASHEx_OBErase();
- if (status == HAL_OK)
- {
- /* Enable write protection */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(FLASH_WRP0_WRP0)
- if(WRP0_Data != 0xFFU)
- {
- OB->WRP0 &= WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP0_WRP0 */
-
-#if defined(FLASH_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFFU))
- {
- OB->WRP1 &= WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP1_WRP1 */
-
-#if defined(FLASH_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFFU))
- {
- OB->WRP2 &= WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP2_WRP2 */
-
-#if defined(FLASH_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFFU))
- {
- OB->WRP3 &= WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP3_WRP3 */
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Disable the write protection of the desired pages
- * @note An option byte erase is done automatically in this function.
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash page i if
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- *
- * @param WriteProtectPage specifies the page(s) to be write unprotected.
- * The value of this parameter depend on device used within the same series
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint16_t WRP0_Data = 0xFFFF;
-#if defined(FLASH_WRP1_WRP1)
- uint16_t WRP1_Data = 0xFFFF;
-#endif /* FLASH_WRP1_WRP1 */
-#if defined(FLASH_WRP2_WRP2)
- uint16_t WRP2_Data = 0xFFFF;
-#endif /* FLASH_WRP2_WRP2 */
-#if defined(FLASH_WRP3_WRP3)
- uint16_t WRP3_Data = 0xFFFF;
-#endif /* FLASH_WRP3_WRP3 */
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(WriteProtectPage));
-
- /* Get current write protected pages and the new pages to be unprotected ******/
- WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
-
-#if defined(OB_WRP_PAGES0TO15MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
-#elif defined(OB_WRP_PAGES0TO31MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
-#endif /* OB_WRP_PAGES0TO31MASK */
-
-#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
-#elif defined(OB_WRP_PAGES32TO63MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
-#endif /* OB_WRP_PAGES32TO63MASK */
-
-#if defined(OB_WRP_PAGES64TO95MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
-#endif /* OB_WRP_PAGES64TO95MASK */
-#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
-#endif /* OB_WRP_PAGES32TO47MASK */
-
-#if defined(OB_WRP_PAGES96TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO511MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
-#endif /* OB_WRP_PAGES96TO127MASK */
-
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* To be able to write again option byte, need to perform a option byte erase */
- status = HAL_FLASHEx_OBErase();
- if (status == HAL_OK)
- {
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(FLASH_WRP0_WRP0)
- if(WRP0_Data != 0xFFU)
- {
- OB->WRP0 |= WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP0_WRP0 */
-
-#if defined(FLASH_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFFU))
- {
- OB->WRP1 |= WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP1_WRP1 */
-
-#if defined(FLASH_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFFU))
- {
- OB->WRP2 |= WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP2_WRP2 */
-
-#if defined(FLASH_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFFU))
- {
- OB->WRP3 |= WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP3_WRP3 */
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
- return status;
-}
-
-/**
- * @brief Set the read protection level.
- * @param ReadProtectLevel specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg @ref OB_RDP_LEVEL_0 No protection
- * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* If the previous operation is completed, proceed to erase the option bytes */
- SET_BIT(FLASH->CR, FLASH_CR_OPTER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the OPTER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
-
- if(status == HAL_OK)
- {
- /* Enable the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
- WRITE_REG(OB->RDP, ReadProtectLevel);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Program the FLASH User Option Byte.
- * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
- * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2),
- * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
- * And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
- assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
- assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
-#if defined(FLASH_BANK2_END)
- assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
-#endif /* FLASH_BANK2_END */
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Enable the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(FLASH_BANK2_END)
- OB->USER = (UserConfig | 0xF0U);
-#else
- OB->USER = (UserConfig | 0x88U);
-#endif /* FLASH_BANK2_END */
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
-
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified Option Byte Data address.
- * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
- * @param Address specifies the address to be programmed.
- * This parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data specifies the data to be programmed.
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Enables the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/**
- * @brief Return the FLASH Write Protection Option Bytes value.
- * @retval The FLASH Write Protection Option Bytes value
- */
-static uint32_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (uint32_t)(READ_REG(FLASH->WRPR));
-}
-
-/**
- * @brief Returns the FLASH Read Protection level.
- * @retval FLASH RDP level
- * This parameter can be one of the following values:
- * @arg @ref OB_RDP_LEVEL_0 No protection
- * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
- */
-static uint32_t FLASH_OB_GetRDP(void)
-{
- uint32_t readstatus = OB_RDP_LEVEL_0;
- uint32_t tmp_reg = 0U;
-
- /* Read RDP level bits */
- tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
-
- if (tmp_reg == FLASH_OBR_RDPRT)
- {
- readstatus = OB_RDP_LEVEL_1;
- }
- else
- {
- readstatus = OB_RDP_LEVEL_0;
- }
-
- return readstatus;
-}
-
-/**
- * @brief Return the FLASH User Option Byte value.
- * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2),
- * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
- * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .
- */
-static uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
- * @brief Erase the specified FLASH memory page
- * @param PageAddress FLASH page to erase
- * The value of this parameter depend on device used within the same series
- *
- * @retval None
- */
-void FLASH_PageErase(uint32_t PageAddress)
-{
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-#if defined(FLASH_BANK2_END)
- if(PageAddress > FLASH_BANK1_END)
- {
- /* Proceed to erase the page */
- SET_BIT(FLASH->CR2, FLASH_CR2_PER);
- WRITE_REG(FLASH->AR2, PageAddress);
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
- }
- else
- {
-#endif /* FLASH_BANK2_END */
- /* Proceed to erase the page */
- SET_BIT(FLASH->CR, FLASH_CR_PER);
- WRITE_REG(FLASH->AR, PageAddress);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-#if defined(FLASH_BANK2_END)
- }
-#endif /* FLASH_BANK2_END */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
deleted file mode 100644
index cd3563a..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
+++ /dev/null
@@ -1,587 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_gpio.c
- * @author MCD Application Team
- * @brief GPIO HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (GPIO) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- @verbatim
- ==============================================================================
- ##### GPIO Peripheral features #####
- ==============================================================================
- [..]
- Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
- port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
- in several modes:
- (+) Input mode
- (+) Analog mode
- (+) Output mode
- (+) Alternate function mode
- (+) External interrupt/event lines
-
- [..]
- During and just after reset, the alternate functions and external interrupt
- lines are not active and the I/O ports are configured in input floating mode.
-
- [..]
- All GPIO pins have weak internal pull-up and pull-down resistors, which can be
- activated or not.
-
- [..]
- In Output or Alternate mode, each IO can be configured on open-drain or push-pull
- type and the IO speed can be selected depending on the VDD value.
-
- [..]
- All ports have external interrupt/event capability. To use external interrupt
- lines, the port must be configured in input mode. All available GPIO pins are
- connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
- [..]
- The external interrupt/event controller consists of up to 20 edge detectors in connectivity
- line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
- Each input line can be independently configured to select the type (event or interrupt) and
- the corresponding trigger event (rising or falling or both). Each line can also masked
- independently. A pending register maintains the status line of the interrupt requests
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
-
- (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
- (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
- (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
- structure.
- (++) In case of Output or alternate function mode selection: the speed is
- configured through "Speed" member from GPIO_InitTypeDef structure
- (++) Analog mode is required when a pin is to be used as ADC channel
- or DAC output.
- (++) In case of external interrupt/event selection the "Mode" member from
- GPIO_InitTypeDef structure select the type (interrupt or event) and
- the corresponding trigger event (rising or falling or both).
-
- (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
- mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
- HAL_NVIC_EnableIRQ().
-
- (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
- (#) To set/reset the level of a pin configured in output mode use
- HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
- (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
- (#) During and just after reset, the alternate functions are not
- active and the GPIO pins are configured in input floating mode (except JTAG
- pins).
-
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
- (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
- priority over the GPIO function.
-
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
- The HSE has priority over the GPIO function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIO GPIO
- * @brief GPIO HAL module driver
- * @{
- */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-#define GPIO_MODE 0x00000003u
-#define EXTI_MODE 0x10000000u
-#define GPIO_MODE_IT 0x00010000u
-#define GPIO_MODE_EVT 0x00020000u
-#define RISING_EDGE 0x00100000u
-#define FALLING_EDGE 0x00200000u
-#define GPIO_OUTPUT_TYPE 0x00000010u
-
-#define GPIO_NUMBER 16u
-
-/* Definitions for bit manipulation of CRL and CRH register */
-#define GPIO_CR_MODE_INPUT 0x00000000u /*!< 00: Input mode (reset state) */
-#define GPIO_CR_CNF_ANALOG 0x00000000u /*!< 00: Analog mode */
-#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004u /*!< 01: Floating input (reset state) */
-#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008u /*!< 10: Input with pull-up / pull-down */
-#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000u /*!< 00: General purpose output push-pull */
-#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004u /*!< 01: General purpose output Open-drain */
-#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008u /*!< 10: Alternate function output Push-pull */
-#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000Cu /*!< 11: Alternate function output Open-drain */
-
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize and de-initialize the GPIOs
- to be ready for use.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- uint32_t position = 0x00u;
- uint32_t ioposition;
- uint32_t iocurrent;
- uint32_t temp;
- uint32_t config = 0x00u;
- __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
- uint32_t registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
- /* Configure the port pins */
- while (((GPIO_Init->Pin) >> position) != 0x00u)
- {
- /* Get the IO position */
- ioposition = (0x01uL << position);
-
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
-
- if (iocurrent == ioposition)
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
-
- /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
- switch (GPIO_Init->Mode)
- {
- /* If we are configuring the pin in OUTPUT push-pull mode */
- case GPIO_MODE_OUTPUT_PP:
- /* Check the GPIO speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
- break;
-
- /* If we are configuring the pin in OUTPUT open-drain mode */
- case GPIO_MODE_OUTPUT_OD:
- /* Check the GPIO speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
- break;
-
- /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
- case GPIO_MODE_AF_PP:
- /* Check the GPIO speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
- break;
-
- /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
- case GPIO_MODE_AF_OD:
- /* Check the GPIO speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
- break;
-
- /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
- case GPIO_MODE_INPUT:
- case GPIO_MODE_IT_RISING:
- case GPIO_MODE_IT_FALLING:
- case GPIO_MODE_IT_RISING_FALLING:
- case GPIO_MODE_EVT_RISING:
- case GPIO_MODE_EVT_FALLING:
- case GPIO_MODE_EVT_RISING_FALLING:
- /* Check the GPIO pull parameter */
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
- if (GPIO_Init->Pull == GPIO_NOPULL)
- {
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
- }
- else if (GPIO_Init->Pull == GPIO_PULLUP)
- {
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
-
- /* Set the corresponding ODR bit */
- GPIOx->BSRR = ioposition;
- }
- else /* GPIO_PULLDOWN */
- {
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
-
- /* Reset the corresponding ODR bit */
- GPIOx->BRR = ioposition;
- }
- break;
-
- /* If we are configuring the pin in INPUT analog mode */
- case GPIO_MODE_ANALOG:
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
- break;
-
- /* Parameters are checked with assert_param */
- default:
- break;
- }
-
- /* Check if the current bit belongs to first half or last half of the pin count number
- in order to address CRH or CRL register*/
- configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
- registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
-
- /* Apply the new configuration of the pin to the register */
- MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- {
- /* Enable AFIO Clock */
- __HAL_RCC_AFIO_CLK_ENABLE();
- temp = AFIO->EXTICR[position >> 2u];
- CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
- SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
- AFIO->EXTICR[position >> 2u] = temp;
-
-
- /* Configure the interrupt mask */
- if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- {
- SET_BIT(EXTI->IMR, iocurrent);
- }
- else
- {
- CLEAR_BIT(EXTI->IMR, iocurrent);
- }
-
- /* Configure the event mask */
- if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- {
- SET_BIT(EXTI->EMR, iocurrent);
- }
- else
- {
- CLEAR_BIT(EXTI->EMR, iocurrent);
- }
-
- /* Enable or disable the rising trigger */
- if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- {
- SET_BIT(EXTI->RTSR, iocurrent);
- }
- else
- {
- CLEAR_BIT(EXTI->RTSR, iocurrent);
- }
-
- /* Enable or disable the falling trigger */
- if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- {
- SET_BIT(EXTI->FTSR, iocurrent);
- }
- else
- {
- CLEAR_BIT(EXTI->FTSR, iocurrent);
- }
- }
- }
-
- position++;
- }
-}
-
-/**
- * @brief De-initializes the GPIOx peripheral registers to their default reset values.
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @retval None
- */
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
-{
- uint32_t position = 0x00u;
- uint32_t iocurrent;
- uint32_t tmp;
- __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
- uint32_t registeroffset;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Configure the port pins */
- while ((GPIO_Pin >> position) != 0u)
- {
- /* Get current io position */
- iocurrent = (GPIO_Pin) & (1uL << position);
-
- if (iocurrent)
- {
- /*------------------------- EXTI Mode Configuration --------------------*/
- /* Clear the External Interrupt or Event for the current IO */
-
- tmp = AFIO->EXTICR[position >> 2u];
- tmp &= 0x0FuL << (4u * (position & 0x03u));
- if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
- {
- tmp = 0x0FuL << (4u * (position & 0x03u));
- CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp);
-
- /* Clear EXTI line configuration */
- CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
- CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
-
- /* Clear Rising Falling edge configuration */
- CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
- CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
- }
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Check if the current bit belongs to first half or last half of the pin count number
- in order to address CRH or CRL register */
- configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
- registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
-
- /* CRL/CRH default value is floating input(0x04) shifted to correct position */
- MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset);
-
- /* ODR default value is 0 */
- CLEAR_BIT(GPIOx->ODR, iocurrent);
- }
-
- position++;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the GPIOs.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_PIN_x where x can be (0..15).
- * @retval The input port pin value.
- */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- GPIO_PinState bitstatus;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
- {
- bitstatus = GPIO_PIN_SET;
- }
- else
- {
- bitstatus = GPIO_PIN_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- *
- * @note This function uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- *
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @param PinState: specifies the value to be written to the selected bit.
- * This parameter can be one of the GPIO_PinState enum values:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if (PinState != GPIO_PIN_RESET)
- {
- GPIOx->BSRR = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
- }
-}
-
-/**
- * @brief Toggles the specified GPIO pin
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Pin: Specifies the pins to be toggled.
- * @retval None
- */
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- uint32_t odr;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* get current Ouput Data Register value */
- odr = GPIOx->ODR;
-
- /* Set selected pins that were at low level, and reset ones that were high */
- GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
-}
-
-/**
-* @brief Locks GPIO Pins configuration registers.
-* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
-* has been applied on a port bit, it is no longer possible to modify the value of the port bit until
-* the next reset.
-* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
-* @param GPIO_Pin: specifies the port bit to be locked.
-* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-* @retval None
-*/
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Apply lock key write sequence */
- SET_BIT(tmp, GPIO_Pin);
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Read LCKK register. This read is mandatory to complete key lock sequence */
- tmp = GPIOx->LCKR;
-
- /* read again in order to confirm lock is active */
- if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
- {
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief This function handles EXTI interrupt request.
- * @param GPIO_Pin: Specifies the pins connected EXTI line
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- /* EXTI line interrupt detected */
- if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- }
-}
-
-/**
- * @brief EXTI line detection callbacks.
- * @param GPIO_Pin: Specifies the pins connected EXTI line
- * @retval None
- */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(GPIO_Pin);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_GPIO_EXTI_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c
deleted file mode 100644
index c2d810c..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_gpio_ex.c
- * @author MCD Application Team
- * @brief GPIO Extension HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
- * + Extended features functions
- *
- @verbatim
- ==============================================================================
- ##### GPIO Peripheral extension features #####
- ==============================================================================
- [..] GPIO module on STM32F1 family, manage also the AFIO register:
- (+) Possibility to use the EVENTOUT Cortex feature
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to use EVENTOUT Cortex feature
- (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
- (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
- (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIOEx GPIOEx
- * @brief GPIO HAL module driver
- * @{
- */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
- * @{
- */
-
-/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ==============================================================================
- ##### Extended features functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
- (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
- (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
- * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
- * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
- * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
- * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
- * @retval None
- */
-void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
-{
- /* Verify the parameters */
- assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
- assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
-
- /* Apply the new configuration */
- MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));
-}
-
-/**
- * @brief Enables the Event Output.
- * @retval None
- */
-void HAL_GPIOEx_EnableEventout(void)
-{
- SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
-
-/**
- * @brief Disables the Event Output.
- * @retval None
- */
-void HAL_GPIOEx_DisableEventout(void)
-{
- CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c
deleted file mode 100644
index c757976..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c
+++ /dev/null
@@ -1,621 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_pwr.c
- * @author MCD Application Team
- * @brief PWR HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWR PWR
- * @brief PWR HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Constants PWR Private Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
- * @{
- */
-#define PVD_MODE_IT 0x00010000U
-#define PVD_MODE_EVT 0x00020000U
-#define PVD_RISING_EDGE 0x00000001U
-#define PVD_FALLING_EDGE 0x00000002U
-/**
- * @}
- */
-
-
-/** @defgroup PWR_register_alias_address PWR Register alias address
- * @{
- */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET 0x00U
-#define PWR_CSR_OFFSET 0x04U
-#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
-#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
-/**
- * @}
- */
-
-/** @defgroup PWR_CR_register_alias PWR CR Register alias address
- * @{
- */
-/* --- CR Register ---*/
-/* Alias word address of LPSDSR bit */
-#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
-#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
-
-/* Alias word address of DBP bit */
-#define DBP_BIT_NUMBER PWR_CR_DBP_Pos
-#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
-#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
- * @{
- */
-
-/* --- CSR Register ---*/
-/* Alias word address of EWUP1 bit */
-#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup PWR_Private_Functions PWR Private Functions
- * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
- * @{
- */
-static void PWR_OverloadWfe(void);
-
-/* Private functions ---------------------------------------------------------*/
-__NOINLINE
-static void PWR_OverloadWfe(void)
-{
- __asm volatile( "wfe" );
- __asm volatile( "nop" );
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- After reset, the backup domain (RTC registers, RTC backup data
- registers) is protected against possible unwanted
- write accesses.
- To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- __HAL_RCC_PWR_CLK_ENABLE() macro.
- (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @retval None
- */
-void HAL_PWR_DeInit(void)
-{
- __HAL_RCC_PWR_FORCE_RESET();
- __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
- * @brief Enables access to the backup domain (RTC registers, RTC
- * backup data registers ).
- * @note If the HSE divided by 128 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @retval None
- */
-void HAL_PWR_EnableBkUpAccess(void)
-{
- /* Enable access to RTC and backup registers */
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables access to the backup domain (RTC registers, RTC
- * backup data registers).
- * @note If the HSE divided by 128 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @retval None
- */
-void HAL_PWR_DisableBkUpAccess(void)
-{
- /* Disable access to RTC and backup registers */
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
-
- *** PVD configuration ***
- =========================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled. This is done through
- __HAL_PVD_EXTI_ENABLE_IT() macro.
- (+) The PVD is stopped in Standby mode.
-
- *** WakeUp pin configuration ***
- ================================
- [..]
- (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
- forced in input pull-down configuration and is active on rising edges.
- (+) There is one WakeUp pin:
- WakeUp Pin 1 on PA.00.
-
- [..]
-
- *** Low Power modes configuration ***
- =====================================
- [..]
- The device features 3 low-power modes:
- (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
- NVIC, SysTick, etc. are kept running
- (+) Stop mode: All clocks are stopped
- (+) Standby mode: 1.8V domain powered off
-
-
- *** Sleep mode ***
- ==================
- [..]
- (+) Entry:
- The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
- functions with
- (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-
- (+) Exit:
- (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
- (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
- (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
- (+++) Any EXTI Line (Internal or External) configured in Event mode
-
- *** Stop mode ***
- =================
- [..]
- The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
- clock gating. The voltage regulator can be configured either in normal or low-power mode.
- In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
- oscillators are disabled. SRAM and register contents are preserved.
- In Stop mode, all I/O pins keep the same state as in Run mode.
-
- (+) Entry:
- The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
- function with:
- (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
- (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
- (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
- (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
- (+) Exit:
- (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
- (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
-
- *** Standby mode ***
- ====================
- [..]
- The Standby mode allows to achieve the lowest power consumption. It is based on the
- Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
- consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
- switched off. SRAM and register contents are lost except for registers in the Backup domain
- and Standby circuitry
-
- (+) Entry:
- (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
- NRSTpin, IWDG Reset
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
-
- (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
- without depending on an external interrupt (Auto-wakeup mode).
-
- (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
-
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
- configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
-
- *** PWR Workarounds linked to Silicon Limitation ***
- ====================================================
- [..]
- Below the list of all silicon limitations known on STM32F1xx prouct.
-
- (#)Workarounds Implemented inside PWR HAL Driver
- (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
- * information for the PVD.
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
- assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
- /* Set PLS[7:5] bits according to PVDLevel value */
- MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */
- __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVD_EXTI_DISABLE_IT();
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
- }
-}
-
-/**
- * @brief Enables the Power Voltage Detector(PVD).
- * @retval None
- */
-void HAL_PWR_EnablePVD(void)
-{
- /* Enable the power voltage detector */
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables the Power Voltage Detector(PVD).
- * @retval None
- */
-void HAL_PWR_DisablePVD(void)
-{
- /* Disable the power voltage detector */
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
-}
-
-/**
- * @brief Enables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
- * This parameter can be one of the following values:
- * @arg PWR_WAKEUP_PIN1
- * @retval None
- */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
-{
- /* Check the parameter */
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- /* Enable the EWUPx pin */
- *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
- * This parameter can be one of the following values:
- * @arg PWR_WAKEUP_PIN1
- * @retval None
- */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
- /* Check the parameter */
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- /* Disable the EWUPx pin */
- *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
-}
-
-/**
- * @brief Enters Sleep mode.
- * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
- * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
- * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
- * When WFI entry is used, tick interrupt have to be disabled if not desired as
- * the interrupt wake up source.
- * This parameter can be one of the following values:
- * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
- * @retval None
- */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
- /* Check the parameters */
- /* No check on Regulator because parameter not used in SLEEP mode */
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Regulator);
-
- assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select SLEEP mode entry -------------------------------------------------*/
- if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-}
-
-/**
- * @brief Enters Stop mode.
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by using an interrupt or a wakeup event,
- * HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- * @param Regulator: Specifies the regulator state in Stop mode.
- * This parameter can be one of the following values:
- * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
- * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
- * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
- * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
- * @retval None
- */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
- CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
-
- /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
- MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select Stop mode entry --------------------------------------------------*/
- if(STOPEntry == PWR_STOPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- PWR_OverloadWfe(); /* WFE redefine locally */
- PWR_OverloadWfe(); /* WFE redefine locally */
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Enters Standby mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available)
- * - TAMPER pin if configured for tamper or calibration out.
- * - WKUP pin (PA0) if enabled.
- * @retval None
- */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
- /* Select Standby mode */
- SET_BIT(PWR->CR, PWR_CR_PDDS);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-
-/**
- * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
- * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * Setting this bit is useful when the processor is expected to run only on
- * interruptions handling.
- * @retval None
- */
-void HAL_PWR_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
- * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
- * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * @retval None
- */
-void HAL_PWR_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
- * @brief Enables CORTEX M3 SEVONPEND bit.
- * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_EnableSEVOnPend(void)
-{
- /* Set SEVONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-/**
- * @brief Disables CORTEX M3 SEVONPEND bit.
- * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_DisableSEVOnPend(void)
-{
- /* Clear SEVONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-
-/**
- * @brief This function handles the PWR PVD interrupt request.
- * @note This API should be called under the PVD_IRQHandler().
- * @retval None
- */
-void HAL_PWR_PVD_IRQHandler(void)
-{
- /* Check PWR exti flag */
- if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
- {
- /* PWR PVD interrupt user callback */
- HAL_PWR_PVDCallback();
-
- /* Clear PWR Exti pending bit */
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
- }
-}
-
-/**
- * @brief PWR PVD interrupt callback
- * @retval None
- */
-__weak void HAL_PWR_PVDCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWR_PVDCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
deleted file mode 100644
index 95b5568..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
+++ /dev/null
@@ -1,1403 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_rcc.c
- * @author MCD Application Team
- * @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Reset and Clock Control (RCC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### RCC specific features #####
- ==============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
- and all peripherals are off except internal SRAM, Flash and JTAG.
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
- all peripherals mapped on these buses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in input floating state, except the JTAG pins which
- are assigned to be used for debug purpose.
- [..] Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB buses prescalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals whose clocks are not
- derived from the System clock (I2S, RTC, ADC, USB OTG FS)
-
- ##### RCC Limitations #####
- ==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective peripheral
- enabling should be taken into account in order to manage the peripheral read/write
- from/to registers.
- (+) This delay depends on the peripheral mapping.
- (++) AHB & APB peripherals, 1 dummy read is necessary
-
- [..]
- Workarounds:
- (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
- inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCC RCC
-* @brief RCC HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
- * @{
- */
-
-#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT GPIOA
-#define MCO1_PIN GPIO_PIN_8
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
- * @{
- */
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-static void RCC_Delay(uint32_t mdelay);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the internal/external oscillators
- (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
- and APB2).
-
- [..] Internal/external clock and PLL configuration
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
- (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- (#) PLL (clocked by HSI or HSE), featuring different output clocks:
- (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
-
- (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
- and if a HSE clock failure occurs(HSE used directly or through PLL as System
- clock source), the System clocks automatically switched to HSI and an interrupt
- is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
- (Non-Maskable Interrupt) exception vector.
-
- (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
- HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
-
- [..] System, AHB and APB buses clocks configuration
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these buses. You can use
- "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
- divided by 128.
- (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
- to work correctly. This clock is derived of the main PLL through PLL Multiplier.
- (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
- (+@) IWDG clock which is always the LSI clock.
-
- (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
- For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
- @endverbatim
- * @{
- */
-
-/*
- Additional consideration on the SYSCLK based on Latency settings:
- +-----------------------------------------------+
- | Latency | SYSCLK clock frequency (MHz) |
- |---------------|-------------------------------|
- |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
- |---------------|-------------------------------|
- |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
- |---------------|-------------------------------|
- |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
- +-----------------------------------------------+
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE, PLL, PLL2 and PLL3 are OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS and MCO1 OFF
- * - All interrupts disabled
- * - All flags are cleared
- * @note This function does not modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval HAL_StatusTypeDef
- */
-HAL_StatusTypeDef HAL_RCC_DeInit(void)
-{
- uint32_t tickstart;
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Set HSION bit */
- SET_BIT(RCC->CR, RCC_CR_HSION);
-
- /* Wait till HSI is ready */
- while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Set HSITRIM bits to the reset value */
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Reset CFGR register */
- CLEAR_REG(RCC->CFGR);
-
- /* Wait till clock switch is ready */
- while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HSI_VALUE;
-
- /* Adapt Systick interrupt period */
- if (HAL_InitTick(uwTickPrio) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Second step is to clear PLLON bit */
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-
- /* Wait till PLL is disabled */
- while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Ensure to reset PLLSRC and PLLMUL bits */
- CLEAR_REG(RCC->CFGR);
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Reset HSEON & CSSON bits */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);
-
- /* Wait till HSE is disabled */
- while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset HSEBYP bit */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
-#if defined(RCC_PLL2_SUPPORT)
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Clear PLL2ON bit */
- CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
-
- /* Wait till PLL2 is disabled */
- while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-#endif /* RCC_PLL2_SUPPORT */
-
-#if defined(RCC_PLLI2S_SUPPORT)
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Clear PLL3ON bit */
- CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
-
- /* Wait till PLL3 is disabled */
- while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_CFGR2_PREDIV1)
- /* Reset CFGR2 register */
- CLEAR_REG(RCC->CFGR2);
-#endif /* RCC_CFGR2_PREDIV1 */
-
- /* Reset all CSR flags */
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-
- /* Disable all interrupts */
- CLEAR_REG(RCC->CIR);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the RCC Oscillators according to the specified parameters in the
- * RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC Oscillators.
- * @note The PLL is not disabled when used as system clock.
- * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this macro. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- uint32_t tickstart;
- uint32_t pll_config;
-
- /* Check Null pointer */
- if (RCC_OscInitStruct == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
- /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
- if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
- {
- if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-
- /* Check the HSE State */
- if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
- {
- /* When HSI is used as system clock it will not disabled */
- if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- }
- else
- {
- /* Check the HSI State */
- if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- /* To have a fully stabilized clock in the specified range, a software delay of 1ms
- should be added.*/
- RCC_Delay(1);
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- {
- FlagStatus pwrclkchanged = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if (__HAL_RCC_PWR_IS_CLK_DISABLED())
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- /* Check the LSE State */
- if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Require to disable power clock if necessary */
- if (pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
-#if defined(RCC_CR_PLL2ON)
- /*-------------------------------- PLL2 Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
- if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
- {
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system
- clock (i.e. it is used as PLL clock entry that is used as system clock). */
- if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
- ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
- {
- return HAL_ERROR;
- }
- else
- {
- if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
- assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
-
- /* Prediv2 can be written only when the PLLI2S is disabled. */
- /* Return an error only if new value is different from the programmed value */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
- (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
- {
- return HAL_ERROR;
- }
-
- /* Disable the main PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the HSE prediv2 factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
-
- /* Configure the main PLL2 multiplication factors. */
- __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
-
- /* Enable the main PLL2. */
- __HAL_RCC_PLL2_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Set PREDIV1 source to HSE */
- CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
-
- /* Disable the main PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
-
-#endif /* RCC_CR_PLL2ON */
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- {
- /* Check if the PLL is used as system clock or not */
- if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the HSE prediv factor --------------------------------*/
- /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
- if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
- {
- /* Check the parameter */
- assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
-#if defined(RCC_CFGR2_PREDIV1SRC)
- assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
-
- /* Set PREDIV1 source */
- SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
-#endif /* RCC_CFGR2_PREDIV1SRC */
-
- /* Set PREDIV1 Value */
- __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
- }
-
- /* Configure the main PLL clock source and multiplication factors. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLMUL);
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- /* Check if there is a request to disable the PLL used as System clock source */
- if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
- {
- return HAL_ERROR;
- }
- else
- {
- /* Do not return HAL_ERROR if request repeats the current configuration */
- pll_config = RCC->CFGR;
- if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
- {
- return HAL_ERROR;
- }
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
- * parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC peripheral.
- * @param FLatency FLASH Latency
- * The value of this parameter depend on device used within the same series
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
- *
- * @note The HSI is used (enabled by hardware) as system clock source after
- * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- *
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after start-up delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
- * currently used as system clock source.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- uint32_t tickstart;
-
- /* Check Null pointer */
- if (RCC_ClkInitStruct == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
- assert_param(IS_FLASH_LATENCY(FLatency));
-
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) of the device. */
-
-#if defined(FLASH_ACR_LATENCY)
- /* Increasing the number of wait states because of higher CPU frequency */
- if (FLatency > __HAL_FLASH_GET_LATENCY())
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if (__HAL_FLASH_GET_LATENCY() != FLatency)
- {
- return HAL_ERROR;
- }
-}
-
-#endif /* FLASH_ACR_LATENCY */
-/*-------------------------- HCLK Configuration --------------------------*/
-if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- /* Set the highest APBx dividers in order to ensure that we do not go through
- a non-spec phase whatever we decrease or increase HCLK. */
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- }
-
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- }
-
- /* Set the new HCLK clock divider */
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
-#if defined(FLASH_ACR_LATENCY)
- /* Decreasing the number of wait states because of lower CPU frequency */
- if (FLatency < __HAL_FLASH_GET_LATENCY())
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if (__HAL_FLASH_GET_LATENCY() != FLatency)
- {
- return HAL_ERROR;
- }
-}
-#endif /* FLASH_ACR_LATENCY */
-
-/*-------------------------- PCLK1 Configuration ---------------------------*/
-if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick(uwTickPrio);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
- *
- @verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
-
- @endverbatim
- * @{
- */
-
-/**
- * @brief Selects the clock source to output on MCO pin.
- * @note MCO pin should be configured in alternate function mode.
- * @param RCC_MCOx specifies the output direction for the clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
- * @param RCC_MCOSource specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- @if STM32F105xC
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
- @endif
- @if STM32F107xC
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
- @endif
- * @param RCC_MCODiv specifies the MCO DIV.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
- * @retval None
- */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
- GPIO_InitTypeDef gpio = {0U};
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO(RCC_MCOx));
- assert_param(IS_RCC_MCODIV(RCC_MCODiv));
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(RCC_MCOx);
- UNUSED(RCC_MCODiv);
-
- /* Configure the MCO1 pin in alternate function mode */
- gpio.Mode = GPIO_MODE_AF_PP;
- gpio.Speed = GPIO_SPEED_FREQ_HIGH;
- gpio.Pull = GPIO_NOPULL;
- gpio.Pin = MCO1_PIN;
-
- /* MCO1 Clock Enable */
- MCO1_CLK_ENABLE();
-
- HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
-
- /* Configure the MCO clock source */
- __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
-}
-
-/**
- * @brief Enables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
- * @retval None
- */
-void HAL_RCC_EnableCSS(void)
-{
- *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables the Clock Security System.
- * @retval None
- */
-void HAL_RCC_DisableCSS(void)
-{
- *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
-}
-
-/**
- * @brief Returns the SYSCLK frequency
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
- * divided by PREDIV factor(**)
- * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
- * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
- * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- *
- * @note Each time SYSCLK changes, this function must be called to update the
- * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-#if defined(RCC_CFGR2_PREDIV1SRC)
- const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-#else
- const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
-#if defined(RCC_CFGR2_PREDIV1)
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-#else
- const uint8_t aPredivFactorTable[2] = {1, 2};
-#endif /*RCC_CFGR2_PREDIV1*/
-
-#endif
- uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
- uint32_t sysclockfreq = 0U;
-#if defined(RCC_CFGR2_PREDIV1SRC)
- uint32_t prediv2 = 0U, pll2mul = 0U;
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-
- tmpreg = RCC->CFGR;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (tmpreg & RCC_CFGR_SWS)
- {
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
- {
- sysclockfreq = HSE_VALUE;
- break;
- }
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
- {
- pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
- if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
- {
-#if defined(RCC_CFGR2_PREDIV1)
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
-#else
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
-#endif /*RCC_CFGR2_PREDIV1*/
-#if defined(RCC_CFGR2_PREDIV1SRC)
-
- if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
- {
- /* PLL2 selected as Prediv1 source */
- /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
- pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
- pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));
- }
- else
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
- }
-
- /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
- /* In this case need to divide pllclk by 2 */
- if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
- {
- pllclk = pllclk / 2;
- }
-#else
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
-#endif /*RCC_CFGR2_PREDIV1SRC*/
- }
- else
- {
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
- }
- sysclockfreq = pllclk;
- break;
- }
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- default: /* HSI used as system clock */
- {
- sysclockfreq = HSI_VALUE;
- break;
- }
- }
- return sysclockfreq;
-}
-
-/**
- * @brief Returns the HCLK frequency
- * @note Each time HCLK changes, this function must be called to update the
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated within this function
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- return SystemCoreClock;
-}
-
-/**
- * @brief Returns the PCLK1 frequency
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
-}
-
-/**
- * @brief Returns the PCLK2 frequency
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
-}
-
-/**
- * @brief Configures the RCC_OscInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * will be configured.
- * @retval None
- */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- /* Check the parameters */
- assert_param(RCC_OscInitStruct != NULL);
-
- /* Set all possible values for the Oscillator type parameter ---------------*/
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
- | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
-#if defined(RCC_CFGR2_PREDIV1SRC)
- /* Get the Prediv1 source --------------------------------------------------*/
- RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
-#endif /* RCC_CFGR2_PREDIV1SRC */
-
- /* Get the HSE configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
- else
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
- RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
-
- /* Get the HSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;
- }
- else
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
-
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-
- /* Get the LSE configuration -----------------------------------------------*/
- if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
-
- /* Get the LSI configuration -----------------------------------------------*/
- if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;
- }
- else
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
-
-
- /* Get the PLL configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
- }
- RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
- RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
-#if defined(RCC_CR_PLL2ON)
- /* Get the PLL2 configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
- {
- RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
- }
- RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
- RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
-#endif /* RCC_CR_PLL2ON */
-}
-
-/**
- * @brief Get the RCC_ClkInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
- * contains the current clock configuration.
- * @param pFLatency Pointer on the Flash Latency.
- * @retval None
- */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
- /* Check the parameters */
- assert_param(RCC_ClkInitStruct != NULL);
- assert_param(pFLatency != NULL);
-
- /* Set all possible values for the Clock type parameter --------------------*/
- RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
- RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
-
-#if defined(FLASH_ACR_LATENCY)
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
-#else
- /* For VALUE lines devices, only LATENCY_0 can be set*/
- *pFLatency = (uint32_t)FLASH_LATENCY_0;
-#endif
-}
-
-/**
- * @brief This function handles the RCC CSS interrupt request.
- * @note This API should be called under the NMI_Handler().
- * @retval None
- */
-void HAL_RCC_NMI_IRQHandler(void)
-{
- /* Check RCC CSSF flag */
- if (__HAL_RCC_GET_IT(RCC_IT_CSS))
- {
- /* RCC Clock Security System interrupt user callback */
- HAL_RCC_CSSCallback();
-
- /* Clear RCC CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
- }
-}
-
-/**
- * @brief This function provides delay (in milliseconds) based on CPU cycles method.
- * @param mdelay: specifies the delay time length, in milliseconds.
- * @retval None
- */
-static void RCC_Delay(uint32_t mdelay)
-{
- __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
- do
- {
- __NOP();
- }
- while (Delay --);
-}
-
-/**
- * @brief RCC Clock Security System interrupt callback
- * @retval none
- */
-__weak void HAL_RCC_CSSCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RCC_CSSCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
deleted file mode 100644
index 4719727..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,863 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_rcc_ex.c
- * @author MCD Application Team
- * @brief Extended RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities RCC extension peripheral:
- * + Extended Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/** @defgroup RCCEx RCCEx
- * @brief RCC Extension HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
- * @{
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
- [..]
- (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
- select the RTC clock source; in this case the Backup domain will be reset in
- order to modify the RTC Clock source, as consequence RTC registers (including
- the backup registers) are set to their reset values.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
- * RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * contains the configuration information for the Extended Peripherals clocks(RTC clock).
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
- * the backup registers) are set to their reset values.
- *
- * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
- * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
- * manually disable it.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- uint32_t tickstart = 0U, temp_reg = 0U;
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t pllactive = 0U;
-#endif /* STM32F105xC || STM32F107xC */
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*------------------------------- RTC/LCD Configuration ------------------------*/
- if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
- {
- /* check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- FlagStatus pwrclkchanged = RESET;
-
- /* As soon as function is called to change RTC clock source, activation of the
- power domain is done. */
- /* Requires to enable write access to Backup Domain of necessary */
- if (__HAL_RCC_PWR_IS_CLK_DISABLED())
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
- temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
- if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of BDCR register */
- RCC->BDCR = temp_reg;
-
- /* Wait for LSERDY if LSE was enabled */
- if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-
- /* Require to disable power clock if necessary */
- if (pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
- /*------------------------------ ADC clock Configuration ------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
- {
- /* Check the parameters */
- assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
-
- /* Configure the ADC clock source */
- __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
- }
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- /*------------------------------ I2S2 Configuration ------------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
-
- /* Configure the I2S2 clock source */
- __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
- }
-
- /*------------------------------ I2S3 Configuration ------------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
-
- /* Configure the I2S3 clock source */
- __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
- }
-
- /*------------------------------ PLL I2S Configuration ----------------------*/
- /* Check that PLLI2S need to be enabled */
- if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
- {
- /* Update flag to indicate that PLL I2S should be active */
- pllactive = 1;
- }
-
- /* Check if PLL I2S need to be enabled */
- if (pllactive == 1)
- {
- /* Enable PLL I2S only if not active */
- if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
- assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
-
- /* Prediv2 can be written only when the PLL2 is disabled. */
- /* Return an error only if new value is different from the programmed value */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
- (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
- {
- return HAL_ERROR;
- }
-
- /* Configure the HSE prediv2 factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
-
- /* Configure the main PLLI2S multiplication factors. */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
-
- /* Enable the main PLLI2S. */
- __HAL_RCC_PLLI2S_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
- if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
- {
- return HAL_ERROR;
- }
- }
- }
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- /*------------------------------ USB clock Configuration ------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
-
- /* Configure the USB clock source */
- __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
- }
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the PeriphClkInit according to the internal
- * RCC configuration registers.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
- * @retval None
- */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- uint32_t srcclk = 0U;
-
- /* Set all possible values for the extended clock type parameter------------*/
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
-
- /* Get the RTC configuration -----------------------------------------------*/
- srcclk = __HAL_RCC_GET_RTC_SOURCE();
- /* Source clock is LSE or LSI*/
- PeriphClkInit->RTCClockSelection = srcclk;
-
- /* Get the ADC clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
- PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- /* Get the I2S2 clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
- PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
-
- /* Get the I2S3 clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
- PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
- /* Get the I2S2 clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
- PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
-
- /* Get the I2S3 clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
- PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- /* Get the USB clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
- PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-}
-
-/**
- * @brief Returns the peripheral clock frequency
- * @note Returns 0 if peripheral clock is unknown
- * @param PeriphClk Peripheral clock identifier
- * This parameter can be one of the following values:
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
- @if STM32F103xE
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- @endif
- @if STM32F103xG
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- @endif
- @if STM32F105xC
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- @endif
- @if STM32F107xC
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- @endif
- @if STM32F102xx
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- @endif
- @if STM32F103xx
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- @endif
- * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
- */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-#if defined(STM32F105xC) || defined(STM32F107xC)
- const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-
- uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
- uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
-#endif /* STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
- defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
- const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
- const uint8_t aPredivFactorTable[2] = {1, 2};
-
- uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
- uint32_t temp_reg = 0U, frequency = 0U;
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
- switch (PeriphClk)
- {
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- case RCC_PERIPHCLK_USB:
- {
- /* Get RCC configuration ------------------------------------------------------*/
- temp_reg = RCC->CFGR;
-
- /* Check if PLL is enabled */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON))
- {
- pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
- if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
- {
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
-#else
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
- {
- /* PLL2 selected as Prediv1 source */
- /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
- pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
- pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
- }
- else
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
- }
-
- /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
- /* In this case need to divide pllclk by 2 */
- if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
- {
- pllclk = pllclk / 2;
- }
-#else
- if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
- }
-#endif /* STM32F105xC || STM32F107xC */
- }
- else
- {
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
- }
-
- /* Calcul of the USB frequency*/
-#if defined(STM32F105xC) || defined(STM32F107xC)
- /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
- if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
- {
- /* Prescaler of 2 selected for USB */
- frequency = pllclk;
- }
- else
- {
- /* Prescaler of 3 selected for USB */
- frequency = (2 * pllclk) / 3;
- }
-#else
- /* USBCLK = PLLCLK / USB prescaler */
- if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
- {
- /* No prescaler selected for USB */
- frequency = pllclk;
- }
- else
- {
- /* Prescaler of 1.5 selected for USB */
- frequency = (pllclk * 2) / 3;
- }
-#endif
- }
- break;
- }
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
- case RCC_PERIPHCLK_I2S2:
- {
-#if defined(STM32F103xE) || defined(STM32F103xG)
- /* SYSCLK used as source clock for I2S2 */
- frequency = HAL_RCC_GetSysClockFreq();
-#else
- if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
- {
- /* SYSCLK used as source clock for I2S2 */
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else
- {
- /* Check if PLLI2S is enabled */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
- {
- /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
- pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
- frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
- }
- }
-#endif /* STM32F103xE || STM32F103xG */
- break;
- }
- case RCC_PERIPHCLK_I2S3:
- {
-#if defined(STM32F103xE) || defined(STM32F103xG)
- /* SYSCLK used as source clock for I2S3 */
- frequency = HAL_RCC_GetSysClockFreq();
-#else
- if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
- {
- /* SYSCLK used as source clock for I2S3 */
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else
- {
- /* Check if PLLI2S is enabled */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
- {
- /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
- pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
- frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
- }
- }
-#endif /* STM32F103xE || STM32F103xG */
- break;
- }
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
- case RCC_PERIPHCLK_RTC:
- {
- /* Get RCC BDCR configuration ------------------------------------------------------*/
- temp_reg = RCC->BDCR;
-
- /* Check if LSE is ready if RTC clock selection is LSE */
- if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- /* Check if LSI is ready if RTC clock selection is LSI */
- else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
- {
- frequency = LSI_VALUE;
- }
- else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
- {
- frequency = HSE_VALUE / 128U;
- }
- /* Clock not enabled for RTC*/
- else
- {
- /* nothing to do: frequency already initialized to 0U */
- }
- break;
- }
- case RCC_PERIPHCLK_ADC:
- {
- frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
- break;
- }
- default:
- {
- break;
- }
- }
- return (frequency);
-}
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
- * @brief PLLI2S Management functions
- *
-@verbatim
- ===============================================================================
- ##### Extended PLLI2S Management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PLLI2S
- activation or deactivation
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable PLLI2S
- * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
- * contains the configuration information for the PLLI2S
- * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
-{
- uint32_t tickstart = 0U;
-
- /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
- if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
- assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
-
- /* Prediv2 can be written only when the PLL2 is disabled. */
- /* Return an error only if new value is different from the programmed value */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
- (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
- {
- return HAL_ERROR;
- }
-
- /* Disable the main PLLI2S. */
- __HAL_RCC_PLLI2S_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the HSE prediv2 factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
-
-
- /* Configure the main PLLI2S multiplication factors. */
- __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
-
- /* Enable the main PLLI2S. */
- __HAL_RCC_PLLI2S_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable PLLI2S
- * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
-{
- uint32_t tickstart = 0U;
-
- /* Disable PLL I2S as not requested by I2S2 or I2S3*/
- if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
- {
- /* Disable the main PLLI2S. */
- __HAL_RCC_PLLI2S_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
- * @brief PLL2 Management functions
- *
-@verbatim
- ===============================================================================
- ##### Extended PLL2 Management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PLL2
- activation or deactivation
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable PLL2
- * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
- * contains the configuration information for the PLL2
- * @note The PLL2 configuration not modified if used indirectly as system clock.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
-{
- uint32_t tickstart = 0U;
-
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system
- clock (i.e. it is used as PLL clock entry that is used as system clock). */
- if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
- ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
- {
- return HAL_ERROR;
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
- assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
-
- /* Prediv2 can be written only when the PLLI2S is disabled. */
- /* Return an error only if new value is different from the programmed value */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
- (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
- {
- return HAL_ERROR;
- }
-
- /* Disable the main PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the HSE prediv2 factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
-
- /* Configure the main PLL2 multiplication factors. */
- __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
-
- /* Enable the main PLL2. */
- __HAL_RCC_PLL2_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is ready */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable PLL2
- * @note PLL2 is not disabled if used indirectly as system clock.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
-{
- uint32_t tickstart = 0U;
-
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system
- clock (i.e. it is used as PLL clock entry that is used as system clock). */
- if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
- ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
- {
- return HAL_ERROR;
- }
- else
- {
- /* Disable the main PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
- while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c
deleted file mode 100644
index bb02cac..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c
+++ /dev/null
@@ -1,3960 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_spi.c
- * @author MCD Application Team
- * @brief SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Serial Peripheral Interface (SPI) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SPI HAL driver can be used as follows:
-
- (#) Declare a SPI_HandleTypeDef handle structure, for example:
- SPI_HandleTypeDef hspi;
-
- (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
- (##) Enable the SPIx interface clock
- (##) SPI pins configuration
- (+++) Enable the clock for the SPI GPIOs
- (+++) Configure these SPI pins as alternate function push-pull
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the SPIx interrupt priority
- (+++) Enable the NVIC SPI IRQ handle
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
- (+++) Enable the DMAx clock
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx Stream/Channel
- (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
-
- (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
- management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
- (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SPI_MspInit() API.
- [..]
- Circular mode restriction:
- (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
- (##) Master 2Lines RxOnly
- (##) Master 1Line Rx
- (#) The CRC feature is not managed when the DMA circular mode is enabled
- (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
- the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
- [..]
- Master Receive mode restriction:
- (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
- bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
- does not initiate a new transfer the following procedure has to be respected:
- (##) HAL_SPI_DeInit()
- (##) HAL_SPI_Init()
- [..]
- Callback registration:
-
- (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
- allows the user to configure dynamically the driver callbacks.
- Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
-
- Function HAL_SPI_RegisterCallback() allows to register following callbacks:
- (++) TxCpltCallback : SPI Tx Completed callback
- (++) RxCpltCallback : SPI Rx Completed callback
- (++) TxRxCpltCallback : SPI TxRx Completed callback
- (++) TxHalfCpltCallback : SPI Tx Half Completed callback
- (++) RxHalfCpltCallback : SPI Rx Half Completed callback
- (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
- (++) ErrorCallback : SPI Error callback
- (++) AbortCpltCallback : SPI Abort callback
- (++) MspInitCallback : SPI Msp Init callback
- (++) MspDeInitCallback : SPI Msp DeInit callback
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
-
-
- (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
- weak function.
- HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
- This function allows to reset following callbacks:
- (++) TxCpltCallback : SPI Tx Completed callback
- (++) RxCpltCallback : SPI Rx Completed callback
- (++) TxRxCpltCallback : SPI TxRx Completed callback
- (++) TxHalfCpltCallback : SPI Tx Half Completed callback
- (++) RxHalfCpltCallback : SPI Rx Half Completed callback
- (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
- (++) ErrorCallback : SPI Error callback
- (++) AbortCpltCallback : SPI Abort callback
- (++) MspInitCallback : SPI Msp Init callback
- (++) MspDeInitCallback : SPI Msp DeInit callback
-
- [..]
- By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
- all callbacks are set to the corresponding weak functions:
- examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
- Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
- these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
- [..]
- Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
- Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
- Then, the user first registers the MspInit/MspDeInit user callbacks
- using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
- or HAL_SPI_Init() function.
-
- [..]
- When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
-
- [..]
- Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
- the following table resume the max SPI frequency reached with data size 8bits/16bits,
- according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
-
- @endverbatim
-
- Additional table :
-
- DataSize = SPI_DATASIZE_8BIT:
- +----------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Transfer mode |---------------------|----------------------|----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==============================================================================================|
- | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
- | R |----------------|----------|----------|-----------|----------|-----------|----------|
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
- +----------------------------------------------------------------------------------------------+
-
- DataSize = SPI_DATASIZE_16BIT:
- +----------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Transfer mode |---------------------|----------------------|----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==============================================================================================|
- | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA |
- | R |----------------|----------|----------|-----------|----------|-----------|----------|
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
- +----------------------------------------------------------------------------------------------+
- @note The max SPI frequency depend on SPI data size (8bits, 16bits),
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
- @note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
- (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
-
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SPI SPI
- * @brief SPI HAL module driver
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-#if (USE_SPI_CRC != 0U) && defined(SPI_CRC_ERROR_WORKAROUND_FEATURE)
-/* CRC WORKAOUND FEATURE: Variable used to determine if device is impacted by implementation
- * of workaround related to wrong CRC errors detection on SPI2. Conditions in which this workaround
- * has to be applied, are:
- * - STM32F101CDE/STM32F103CDE
- * - Revision ID : Z
- * - SPI2
- * - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
- * the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
- * + If the value is 0, the complete data transfer is successful.
- * + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
- * If CRCERR is found reset, the complete data transfer is considered successful.
- *
- * Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
- * CRC errors wrongly detected
- */
-/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode
- * Revision ID information is only available in Debug mode, so Workaround could not be implemented
- * to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
- * So, in case of Revison Z F101 or F103 devices, below define should be assigned to 1.
- */
-#define USE_SPI_CRC_ERROR_WORKAROUND 0U
-#endif
-/** @defgroup SPI_Private_Constants SPI Private Constants
- * @{
- */
-#define SPI_DEFAULT_TIMEOUT 100U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
- * @{
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
- uint32_t Timeout, uint32_t Tickstart);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#if (USE_SPI_CRC != 0U)
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif /* USE_SPI_CRC */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SPIx peripheral:
-
- (+) User must implement HAL_SPI_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_SPI_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Direction
- (++) Data Size
- (++) Clock Polarity and Phase
- (++) NSS Management
- (++) BaudRate Prescaler
- (++) FirstBit
- (++) TIMode
- (++) CRC Calculation
- (++) CRC Polynomial if CRC enabled
-
- (+) Call the function HAL_SPI_DeInit() to restore the default configuration
- of the selected SPIx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the SPI according to the specified parameters
- * in the SPI_InitTypeDef and initialize the associated handle.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
- /* Check the SPI handle allocation */
- if (hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
- assert_param(IS_SPI_MODE(hspi->Init.Mode));
- assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
- assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_NSS(hspi->Init.NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
- /* TI mode is not supported on this device.
- TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */
- assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
- if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
- {
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
- }
- else
- {
- /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
- hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
- }
- }
- else
- {
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-
- /* Force polarity and phase to TI protocaol requirements */
- hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
- hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
- }
-#if (USE_SPI_CRC != 0U)
- assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
- }
-#else
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
- if (hspi->State == HAL_SPI_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hspi->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- /* Init the SPI Callback settings */
- hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
- hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
- hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
- hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
- hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
- hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
- hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
- hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
-
- if (hspi->MspInitCallback == NULL)
- {
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
- }
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- hspi->MspInitCallback(hspi);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_SPI_MspInit(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the selected SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
- /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
- Communication speed, First bit and CRC calculation state */
- WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
- (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
- (hspi->Init.DataSize & SPI_CR1_DFF) |
- (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
- (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
- (hspi->Init.NSS & SPI_CR1_SSM) |
- (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
- (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
- (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
-
- /* Configure : NSS management */
- WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
-
-#if (USE_SPI_CRC != 0U)
- /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
- /* Configure : CRC Polynomial */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
- }
-#endif /* USE_SPI_CRC */
-
-#if defined(SPI_I2SCFGR_I2SMOD)
- /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
- CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief De-Initialize the SPI peripheral.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
- /* Check the SPI handle allocation */
- if (hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check SPI Instance parameter */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the SPI Peripheral Clock */
- __HAL_SPI_DISABLE(hspi);
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- if (hspi->MspDeInitCallback == NULL)
- {
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
- }
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- hspi->MspDeInitCallback(hspi);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_SPI_MspDeInit(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SPI MSP.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspInit should be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize the SPI MSP.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit should be implemented in the user file
- */
-}
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
- * @brief Register a User SPI Callback
- * To be used instead of the weak predefined callback
- * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI.
- * @param CallbackID ID of the callback to be registered
- * @param pCallback pointer to the Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
- pSPI_CallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL)
- {
- /* Update the error code */
- hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(hspi);
-
- if (HAL_SPI_STATE_READY == hspi->State)
- {
- switch (CallbackID)
- {
- case HAL_SPI_TX_COMPLETE_CB_ID :
- hspi->TxCpltCallback = pCallback;
- break;
-
- case HAL_SPI_RX_COMPLETE_CB_ID :
- hspi->RxCpltCallback = pCallback;
- break;
-
- case HAL_SPI_TX_RX_COMPLETE_CB_ID :
- hspi->TxRxCpltCallback = pCallback;
- break;
-
- case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
- hspi->TxHalfCpltCallback = pCallback;
- break;
-
- case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
- hspi->RxHalfCpltCallback = pCallback;
- break;
-
- case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
- hspi->TxRxHalfCpltCallback = pCallback;
- break;
-
- case HAL_SPI_ERROR_CB_ID :
- hspi->ErrorCallback = pCallback;
- break;
-
- case HAL_SPI_ABORT_CB_ID :
- hspi->AbortCpltCallback = pCallback;
- break;
-
- case HAL_SPI_MSPINIT_CB_ID :
- hspi->MspInitCallback = pCallback;
- break;
-
- case HAL_SPI_MSPDEINIT_CB_ID :
- hspi->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (HAL_SPI_STATE_RESET == hspi->State)
- {
- switch (CallbackID)
- {
- case HAL_SPI_MSPINIT_CB_ID :
- hspi->MspInitCallback = pCallback;
- break;
-
- case HAL_SPI_MSPDEINIT_CB_ID :
- hspi->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
- return status;
-}
-
-/**
- * @brief Unregister an SPI Callback
- * SPI callback is redirected to the weak predefined callback
- * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI.
- * @param CallbackID ID of the callback to be unregistered
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- if (HAL_SPI_STATE_READY == hspi->State)
- {
- switch (CallbackID)
- {
- case HAL_SPI_TX_COMPLETE_CB_ID :
- hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
- break;
-
- case HAL_SPI_RX_COMPLETE_CB_ID :
- hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
- break;
-
- case HAL_SPI_TX_RX_COMPLETE_CB_ID :
- hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
- break;
-
- case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
- hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
- break;
-
- case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
- hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
- break;
-
- case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
- hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
- break;
-
- case HAL_SPI_ERROR_CB_ID :
- hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
-
- case HAL_SPI_ABORT_CB_ID :
- hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- break;
-
- case HAL_SPI_MSPINIT_CB_ID :
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_SPI_MSPDEINIT_CB_ID :
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default :
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (HAL_SPI_STATE_RESET == hspi->State)
- {
- switch (CallbackID)
- {
- case HAL_SPI_MSPINIT_CB_ID :
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_SPI_MSPDEINIT_CB_ID :
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default :
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
- return status;
-}
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SPI
- data transfers.
-
- [..] The SPI supports master and slave mode :
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
- exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
- uint16_t initial_TxXferCount;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
- initial_TxXferCount = Size;
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit data in 16 Bit mode */
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
- {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- /* Transmit data in 16 Bit mode */
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
- /* Transmit data in 8 Bit mode */
- else
- {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
- {
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint8_t);
- hspi->TxXferCount--;
- }
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint8_t);
- hspi->TxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error:
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be received
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- /* this is done to handle the CRCNEXT before the latest data */
- hspi->RxXferCount--;
- }
-#endif /* USE_SPI_CRC */
-
- /* Configure communication direction: 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_RX(hspi);
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Receive data in 8 Bit mode */
- if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
- {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U)
- {
- /* Check the RXNE flag */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
- {
- /* read the received data */
- (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
- else
- {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U)
- {
- /* Check the RXNE flag */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
- {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Handle the CRC Transmission */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* freeze the CRC before the latest data */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-
- /* Check if CRCNEXT is well reseted by hardware */
- if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
- {
- /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
- CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
- /* Read the latest data */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- /* the latest data has not been received */
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Receive last data in 16 Bit mode */
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
- }
- /* Receive last data in 8 Bit mode */
- else
- {
- (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
- }
-
- /* Wait the CRC data */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Read CRC to Flush DR and RXNE flag */
- READ_REG(hspi->Instance->DR);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error :
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @param Size amount of data to be sent and received
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout)
-{
- uint16_t initial_TxXferCount;
- uint32_t tmp_mode;
- HAL_SPI_StateTypeDef tmp_state;
- uint32_t tickstart;
-
- /* Variable used to alternate Rx and Tx during transfer */
- uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Init temporary variables */
- tmp_state = hspi->State;
- tmp_mode = hspi->Init.Mode;
- initial_TxXferCount = Size;
-
- if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferCount = Size;
- hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferCount = Size;
- hspi->TxXferSize = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit and Receive data in 16 Bit mode */
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
- {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* Check TXE flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
- {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- /* Next Data is a reception (Rx). Tx not allowed */
- txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* Check RXNE flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
- {
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
- }
- if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- /* Transmit and Receive data in 8 Bit mode */
- else
- {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
- {
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint8_t);
- hspi->TxXferCount--;
- }
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* Check TXE flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
- {
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
- /* Next Data is a reception (Rx). Tx not allowed */
- txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* Wait until RXNE flag is reset */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
- {
- (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr++;
- hspi->RxXferCount--;
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
- }
- if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Read CRC from DR to close CRC calculation process */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until TXE flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- /* Read CRC */
- READ_REG(hspi->Instance->DR);
- }
-
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
-
- errorcode = HAL_ERROR;
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
- {
- errorcode = HAL_ERROR;
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- goto error;
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
-error :
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->RxISR = NULL;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->TxISR = SPI_TxISR_16BIT;
- }
- else
- {
- hspi->TxISR = SPI_TxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->TxISR = NULL;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->RxISR = SPI_RxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_RxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_RX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @param Size amount of data to be sent and received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t tmp_mode;
- HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- /* Init temporary variables */
- tmp_state = hspi->State;
- tmp_mode = hspi->Init.Mode;
-
- if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check tx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the SPI TxDMA Half transfer complete callback */
- hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
- /* Set the SPI TxDMA transfer complete callback */
- hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
- hspi->TxXferCount))
- {
- /* Update SPI error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- hspi->State = HAL_SPI_STATE_READY;
- goto error;
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA.
- * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @note When the CRC feature is enabled the pData Length must be Size + 1.
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check rx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
-
- /* Check tx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
- __HAL_SPI_DISABLE(hspi);
- SPI_1LINE_RX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the SPI RxDMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
- /* Set the SPI Rx DMA transfer complete callback */
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
- hspi->RxXferCount))
- {
- /* Update SPI error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- hspi->State = HAL_SPI_STATE_READY;
- goto error;
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size)
-{
- uint32_t tmp_mode;
- HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check rx & tx dma handles */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- /* Init temporary variables */
- tmp_state = hspi->State;
- tmp_mode = hspi->Init.Mode;
-
- if (!((tmp_state == HAL_SPI_STATE_READY) ||
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
- if (hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- /* Set the SPI Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
- }
- else
- {
- /* Set the SPI Tx/Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
- }
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
- hspi->RxXferCount))
- {
- /* Update SPI error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- hspi->State = HAL_SPI_STATE_READY;
- goto error;
- }
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
- is performed in DMA reception complete callback */
- hspi->hdmatx->XferHalfCpltCallback = NULL;
- hspi->hdmatx->XferCpltCallback = NULL;
- hspi->hdmatx->XferErrorCallback = NULL;
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
- hspi->TxXferCount))
- {
- /* Update SPI error code */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- hspi->State = HAL_SPI_STATE_READY;
- goto error;
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (blocking mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
- * started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SPI Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
-{
- HAL_StatusTypeDef errorcode;
- __IO uint32_t count;
- __IO uint32_t resetcount;
-
- /* Initialized local variable */
- errorcode = HAL_OK;
- resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- count = resetcount;
-
- /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
- {
- hspi->TxISR = SPI_AbortTx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
- {
- hspi->RxISR = SPI_AbortRx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- /* Disable the SPI DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
- {
- /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
- if (hspi->hdmatx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
-
- /* Wait until TXE flag is set */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
- }
- }
-
- /* Disable the SPI DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
- {
- /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
- if (hspi->hdmarx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
- }
- }
- /* Reset Tx and Rx transfer counters */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check error during Abort procedure */
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
- {
- /* return HAL_Error in case of error during Abort procedure */
- errorcode = HAL_ERROR;
- }
- else
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
-
- /* Restore hspi->state to ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (Interrupt mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
- * started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SPI Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
-{
- HAL_StatusTypeDef errorcode;
- uint32_t abortcplt ;
- __IO uint32_t count;
- __IO uint32_t resetcount;
-
- /* Initialized local variable */
- errorcode = HAL_OK;
- abortcplt = 1U;
- resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- count = resetcount;
-
- /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
- {
- hspi->TxISR = SPI_AbortTx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
- {
- hspi->RxISR = SPI_AbortRx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if (hspi->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
- {
- hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
- }
- else
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if (hspi->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
- {
- hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
- }
- else
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the SPI DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
- {
- /* Abort the SPI DMA Tx Stream/Channel */
- if (hspi->hdmatx != NULL)
- {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
- /* Disable the SPI DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
- {
- /* Abort the SPI DMA Rx Stream/Channel */
- if (hspi->hdmarx != NULL)
- {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- if (abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check error during Abort procedure */
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
- {
- /* return HAL_Error in case of error during Abort procedure */
- errorcode = HAL_ERROR;
- }
- else
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->AbortCpltCallback(hspi);
-#else
- HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-
- return errorcode;
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Enable the SPI DMA Tx & Rx requests */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
- */
-
- /* Abort the SPI DMA tx Stream/Channel */
- if (hspi->hdmatx != NULL)
- {
- if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
- }
- }
- /* Abort the SPI DMA rx Stream/Channel */
- if (hspi->hdmarx != NULL)
- {
- if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
- }
- }
-
- /* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->State = HAL_SPI_STATE_READY;
- return errorcode;
-}
-
-/**
- * @brief Handle SPI interrupt request.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval None
- */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
- uint32_t itsource = hspi->Instance->CR2;
- uint32_t itflag = hspi->Instance->SR;
-
- /* SPI in mode Receiver ----------------------------------------------------*/
- if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
- (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
- {
- hspi->RxISR(hspi);
- return;
- }
-
- /* SPI in mode Transmitter -------------------------------------------------*/
- if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
- {
- hspi->TxISR(hspi);
- return;
- }
-
- /* SPI in Error Treatment --------------------------------------------------*/
- if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
- && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
- {
- /* SPI Overrun error interrupt occurred ----------------------------------*/
- if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
- {
- if (hspi->State != HAL_SPI_STATE_BUSY_TX)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- return;
- }
- }
-
- /* SPI Mode Fault error interrupt occurred -------------------------------*/
- if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
- __HAL_SPI_CLEAR_MODFFLAG(hspi);
- }
-
- /* SPI Frame error interrupt occurred ------------------------------------*/
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- /* Disable all interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-
- hspi->State = HAL_SPI_STATE_READY;
- /* Disable the SPI DMA requests if enabled */
- if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
- {
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
-
- /* Abort the SPI DMA Rx channel */
- if (hspi->hdmarx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
- hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
- if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- }
- }
- /* Abort the SPI DMA Tx channel */
- if (hspi->hdmatx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
- if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- }
- }
- }
- else
- {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- }
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Half Transfer callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
- */
-}
-
-/**
- * @brief SPI error callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback should be implemented in the user file
- */
- /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
- and user can use HAL_SPI_GetError() API to check the latest error occurred
- */
-}
-
-/**
- * @brief SPI Abort Complete callback.
- * @param hspi SPI handle.
- * @retval None
- */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SPI control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SPI.
- (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
- (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SPI handle state.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI state
- */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
- /* Return SPI handle state */
- return hspi->State;
-}
-
-/**
- * @brief Return the SPI error code.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI error code in bitmap format
- */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
- /* Return SPI ErrorCode */
- return hspi->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SPI_Private_Functions
- * @brief Private functions
- * @{
- */
-
-/**
- * @brief DMA SPI transmit process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- uint32_t tickstart;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received data is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->TxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- return;
- }
- }
- /* Call user Tx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxCpltCallback(hspi);
-#else
- HAL_SPI_TxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- uint32_t tickstart;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
- /* CRC handling */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until RXNE flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC */
- READ_REG(hspi->Instance->DR);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if we are in Master RX 2 line mode */
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- }
- else
- {
- /* Normal case */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
- }
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- hspi->RxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- return;
- }
- }
- /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->RxCpltCallback(hspi);
-#else
- HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI transmit receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- uint32_t tickstart;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
- /* CRC handling */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait the CRC data */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC to Flush DR and RXNE flag */
- READ_REG(hspi->Instance->DR);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Disable Rx/Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0U;
- hspi->RxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- return;
- }
- }
- /* Call user TxRx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxRxCpltCallback(hspi);
-#else
- HAL_SPI_TxRxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI half transmit process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Call user Tx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxHalfCpltCallback(hspi);
-#else
- HAL_SPI_TxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI half receive process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Call user Rx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->RxHalfCpltCallback(hspi);
-#else
- HAL_SPI_RxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI half transmit receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Call user TxRx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxRxHalfCpltCallback(hspi);
-#else
- HAL_SPI_TxRxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI communication error callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Stop the disable DMA transfer on SPI side */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- hspi->State = HAL_SPI_STATE_READY;
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- __IO uint32_t count;
-
- hspi->hdmatx->XferAbortCallback = NULL;
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Wait until TXE flag is set */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
- /* Check if an Abort process is still ongoing */
- if (hspi->hdmarx != NULL)
- {
- if (hspi->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check no error during Abort procedure */
- if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->AbortCpltCallback(hspi);
-#else
- HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief DMA SPI Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Check Busy flag */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- }
-
- /* Check if an Abort process is still ongoing */
- if (hspi->hdmatx != NULL)
- {
- if (hspi->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check no error during Abort procedure */
- if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->AbortCpltCallback(hspi);
-#else
- HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 8bit mode */
- *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
- hspi->pRxBuffPtr++;
- hspi->RxXferCount--;
-
- /* Check end of the reception */
- if (hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_2linesRxISR_8BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- if (hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- /* Read 8bit CRC to flush Data Register */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
-
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- if (hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
-
- /* Check the end of the transmission */
- if (hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Set CRC Next Bit to send CRC */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
- if (hspi->RxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-/**
- * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 16 Bit mode */
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
- if (hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_2linesRxISR_16BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- if (hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- /* Read 16bit CRC to flush Data Register */
- READ_REG(hspi->Instance->DR);
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- SPI_CloseRxTx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- /* Enable CRC Transmission */
- if (hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Set CRC Next Bit to send CRC */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
- if (hspi->RxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 8-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- /* Read 8bit CRC to flush Data Register */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
-
- SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Manage the receive 8-bit in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
- hspi->pRxBuffPtr++;
- hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
- /* Check if CRCNEXT is well reseted by hardware */
- if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
- {
- /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
- CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-
-#endif /* USE_SPI_CRC */
-
- if (hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_RxISR_8BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseRx_ISR(hspi);
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 16-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- /* Read 16bit CRC to flush Data Register */
- READ_REG(hspi->Instance->DR);
-
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Manage the 16-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
- /* Check if CRCNEXT is well reseted by hardware */
- if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
- {
- /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
- CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-
-#endif /* USE_SPI_CRC */
-
- if (hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_RxISR_16BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseRx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle the data 8-bit transmit in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
- hspi->pTxBuffPtr++;
- hspi->TxXferCount--;
-
- if (hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Enable CRC Transmission */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseTx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- if (hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Enable CRC Transmission */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseTx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle SPI Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag SPI flag to check
- * @param State flag state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
- uint32_t Timeout, uint32_t Tickstart)
-{
- __IO uint32_t count;
- uint32_t tmp_timeout;
- uint32_t tmp_tickstart;
-
- /* Adjust Timeout value in case of end of transfer */
- tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
- tmp_tickstart = HAL_GetTick();
-
- /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
- count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
-
- while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
- {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
- if(count == 0U)
- {
- tmp_timeout = 0U;
- }
- count--;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle the check of the RX transaction complete.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))
- {
- /* Wait the RXNE reset */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
- }
- else
- {
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle the check of the RXTX or TX transaction complete.
- * @param hspi SPI handle
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle the end of the RXTX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
-{
- uint32_t tickstart;
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Init tickstart for timeout management */
- tickstart = HAL_GetTick();
-
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
- /* Wait until TXE flag is set */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- break;
- }
- count--;
- } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- hspi->State = HAL_SPI_STATE_READY;
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
-
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
- else
- {
-#endif /* USE_SPI_CRC */
- if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- if (hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_READY;
- /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->RxCpltCallback(hspi);
-#else
- HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- else
- {
- hspi->State = HAL_SPI_STATE_READY;
- /* Call user TxRx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxRxCpltCallback(hspi);
-#else
- HAL_SPI_TxRxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- }
- else
- {
- hspi->State = HAL_SPI_STATE_READY;
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-#if (USE_SPI_CRC != 0U)
- }
-#endif /* USE_SPI_CRC */
-}
-
-/**
- * @brief Handle the end of the RX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
-{
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
-
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
- else
- {
-#endif /* USE_SPI_CRC */
- if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->RxCpltCallback(hspi);
-#else
- HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- else
- {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-#if (USE_SPI_CRC != 0U)
- }
-#endif /* USE_SPI_CRC */
-}
-
-/**
- * @brief Handle the end of the TX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
-{
- uint32_t tickstart;
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Wait until TXE flag is set */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- break;
- }
- count--;
- } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
- /* Disable TXE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->ErrorCallback(hspi);
-#else
- HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
- else
- {
- /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- hspi->TxCpltCallback(hspi);
-#else
- HAL_SPI_TxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief Handle abort a Rx transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
-{
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Wait until TXE flag is set */
- do
- {
- if (count == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- count--;
- } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
- /* Read CRC to flush Data Register */
- READ_REG(hspi->Instance->DR);
-
- hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
- * @brief Handle abort a Tx or Rx/Tx transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
-{
- /* Disable TXEIE interrupt */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
- * according to SPI instance, Device type, and revision ID.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
- */
-uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
-{
-#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U)
- /* Check how to handle this CRC error (workaround to be applied or not) */
- /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
- if (hspi->Instance == SPI2)
- {
- if (hspi->Instance->RXCRCR == 0U)
- {
- return (SPI_INVALID_CRC_ERROR);
- }
- }
-#endif
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- return (SPI_VALID_CRC_ERROR);
-}
-#endif /* USE_SPI_CRC */
-/**
- * @}
- */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
deleted file mode 100644
index f4e2e78..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
+++ /dev/null
@@ -1,7421 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_tim.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer (TIM) peripheral:
- * + TIM Time Base Initialization
- * + TIM Time Base Start
- * + TIM Time Base Start Interruption
- * + TIM Time Base Start DMA
- * + TIM Output Compare/PWM Initialization
- * + TIM Output Compare/PWM Channel Configuration
- * + TIM Output Compare/PWM Start
- * + TIM Output Compare/PWM Start Interruption
- * + TIM Output Compare/PWM Start DMA
- * + TIM Input Capture Initialization
- * + TIM Input Capture Channel Configuration
- * + TIM Input Capture Start
- * + TIM Input Capture Start Interruption
- * + TIM Input Capture Start DMA
- * + TIM One Pulse Initialization
- * + TIM One Pulse Channel Configuration
- * + TIM One Pulse Start
- * + TIM Encoder Interface Initialization
- * + TIM Encoder Interface Start
- * + TIM Encoder Interface Start Interruption
- * + TIM Encoder Interface Start DMA
- * + Commutation Event configuration with Interruption and DMA
- * + TIM OCRef clear configuration
- * + TIM External Clock configuration
- @verbatim
- ==============================================================================
- ##### TIMER Generic features #####
- ==============================================================================
- [..] The Timer features include:
- (#) 16-bit up, down, up/down auto-reload counter.
- (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
- counter clock frequency either by any factor between 1 and 65536.
- (#) Up to 4 independent channels for:
- (++) Input Capture
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and to interconnect
- several timers together.
- (#) Supports incremental encoder for positioning purposes
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending on the selected feature:
- (++) Time Base : HAL_TIM_Base_MspInit()
- (++) Input Capture : HAL_TIM_IC_MspInit()
- (++) Output Compare : HAL_TIM_OC_MspInit()
- (++) PWM generation : HAL_TIM_PWM_MspInit()
- (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- Initialization function of this driver:
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
- Output Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
- PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
- external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
- in One Pulse Mode.
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
- (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
- (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
- (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
- (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
- (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
- (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
- (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
- (#) The DMA Burst is managed with the two following functions:
- HAL_TIM_DMABurst_WriteStart()
- HAL_TIM_DMABurst_ReadStart()
-
- *** Callback registration ***
- =============================================
-
- [..]
- The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
-
- [..]
- Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
- @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
- the Callback ID and a pointer to the user callback function.
-
- [..]
- Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
- weak function.
- @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
-
- [..]
- These functions allow to register/unregister following callbacks:
- (+) Base_MspInitCallback : TIM Base Msp Init Callback.
- (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
- (+) IC_MspInitCallback : TIM IC Msp Init Callback.
- (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
- (+) OC_MspInitCallback : TIM OC Msp Init Callback.
- (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
- (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
- (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
- (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
- (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
- (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
- (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
- (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
- (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
- (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
- (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
- (+) TriggerCallback : TIM Trigger Callback.
- (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
- (+) IC_CaptureCallback : TIM Input Capture Callback.
- (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
- (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
- (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
- (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
- (+) ErrorCallback : TIM Error Callback.
- (+) CommutationCallback : TIM Commutation Callback.
- (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
- (+) BreakCallback : TIM Break Callback.
-
- [..]
-By default, after the Init and when the state is HAL_TIM_STATE_RESET
-all interrupt callbacks are set to the corresponding weak functions:
- examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
-
- [..]
- Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
- functionalities in the Init / DeInit only when these callbacks are null
- (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
- keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
-
- [..]
- Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
- Exception done MspInit / MspDeInit that can be registered / unregistered
- in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
- thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
-
- [..]
- When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIM TIM
- * @brief TIM HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig);
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- *
-@verbatim
- ==============================================================================
- ##### Time Base functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM base.
- (+) De-initialize the TIM base.
- (+) Start the Time Base.
- (+) Stop the Time Base.
- (+) Start the Time Base and enable interrupt.
- (+) Stop the Time Base and disable interrupt.
- (+) Start the Time Base and enable DMA transfer.
- (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and initialize the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->Base_MspInitCallback == NULL)
- {
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Base_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Base peripheral
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->Base_MspDeInitCallback == NULL)
- {
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->Base_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Base MSP.
- * @param htim TIM Base handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Base MSP.
- * @param htim TIM Base handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspDeInit could be implemented in the user file
- */
-}
-
-
-/**
- * @brief Starts the TIM Base generation.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Check the TIM state */
- if (htim->State != HAL_TIM_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Check the TIM state */
- if (htim->State != HAL_TIM_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in DMA mode.
- * @param htim TIM Base handle
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- if (htim->State == HAL_TIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (htim->State == HAL_TIM_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Update DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in DMA mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Output Compare.
- (+) De-initialize the TIM Output Compare.
- (+) Start the TIM Output Compare.
- (+) Stop the TIM Output Compare.
- (+) Start the TIM Output Compare and enable interrupt.
- (+) Stop the TIM Output Compare and disable interrupt.
- (+) Start the TIM Output Compare and enable DMA transfer.
- (+) Stop the TIM Output Compare and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
- * @param htim TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->OC_MspInitCallback == NULL)
- {
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->OC_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the Output Compare */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->OC_MspDeInitCallback == NULL)
- {
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->OC_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Output Compare MSP.
- * @param htim TIM Output Compare handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Output Compare MSP.
- * @param htim TIM Output Compare handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- break;
- }
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- break;
- }
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- *
-@verbatim
- ==============================================================================
- ##### TIM PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM PWM.
- (+) De-initialize the TIM PWM.
- (+) Start the TIM PWM.
- (+) Stop the TIM PWM.
- (+) Start the TIM PWM and enable interrupt.
- (+) Stop the TIM PWM and disable interrupt.
- (+) Start the TIM PWM and enable DMA transfer.
- (+) Stop the TIM PWM and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM PWM Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->PWM_MspInitCallback == NULL)
- {
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->PWM_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->PWM_MspDeInitCallback == NULL)
- {
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->PWM_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the PWM signal generation.
- * @param htim TIM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Capture/Compare 3 request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Input Capture functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Input Capture.
- (+) De-initialize the TIM Input Capture.
- (+) Start the TIM Input Capture.
- (+) Stop the TIM Input Capture.
- (+) Start the TIM Input Capture and enable interrupt.
- (+) Stop the TIM Input Capture and disable interrupt.
- (+) Start the TIM Input Capture and enable DMA transfer.
- (+) Stop the TIM Input Capture and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Input Capture Time base according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
- * @param htim TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->IC_MspInitCallback == NULL)
- {
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->IC_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the input capture */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->IC_MspDeInitCallback == NULL)
- {
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->IC_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Input Capture MSP.
- * @param htim TIM Input Capture handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Input Capture MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- break;
- }
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in DMA mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Set the TIM channel state */
- if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- break;
- }
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in DMA mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### TIM One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM One Pulse.
- (+) De-initialize the TIM One Pulse.
- (+) Start the TIM One Pulse.
- (+) Stop the TIM One Pulse.
- (+) Start the TIM One Pulse and enable interrupt.
- (+) Stop the TIM One Pulse and disable interrupt.
- (+) Start the TIM One Pulse and enable DMA transfer.
- (+) Stop the TIM One Pulse and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM One Pulse Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
- * @note When the timer instance is initialized in One Pulse mode, timer
- * channels 1 and channel 2 are reserved and cannot be used for other
- * purpose.
- * @param htim TIM One Pulse handle
- * @param OnePulseMode Select the One pulse mode.
- * This parameter can be one of the following values:
- * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_OPM_MODE(OnePulseMode));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->OnePulse_MspInitCallback == NULL)
- {
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->OnePulse_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OnePulse_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the One Pulse Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Reset the OPM Bit */
- htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- htim->Instance->CR1 |= OnePulseMode;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM One Pulse
- * @param htim TIM One Pulse handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->OnePulse_MspDeInitCallback == NULL)
- {
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->OnePulse_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_OnePulse_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM One Pulse MSP.
- * @param htim TIM One Pulse handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM One Pulse MSP.
- * @param htim TIM One Pulse handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Encoder functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Encoder.
- (+) De-initialize the TIM Encoder.
- (+) Start the TIM Encoder.
- (+) Stop the TIM Encoder.
- (+) Start the TIM Encoder and enable interrupt.
- (+) Stop the TIM Encoder and disable interrupt.
- (+) Start the TIM Encoder and enable DMA transfer.
- (+) Stop the TIM Encoder and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
- * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
- * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
- * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
- * @note When the timer instance is initialized in Encoder mode, timer
- * channels 1 and channel 2 are reserved and cannot be used for other
- * purpose.
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
-{
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->Encoder_MspInitCallback == NULL)
- {
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Encoder_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Reset the SMS and ECE bits */
- htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
-
- /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitializes the TIM Encoder interface
- * @param htim TIM Encoder Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->Encoder_MspDeInitCallback == NULL)
- {
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->Encoder_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Encoder_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Encoder Interface MSP.
- * @param htim TIM Encoder Interface handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim TIM Encoder Interface handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Encoder Interface.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1)
- {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
-
- /* Enable the encoder interface channels */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1)
- {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
-
- /* Enable the encoder interface channels */
- /* Enable the capture compare Interrupts 1 and/or 2 */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if (Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 and 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @param pData1 The destination Buffer address for IC1.
- * @param pData2 The destination Buffer address for IC2.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
- uint32_t *pData2, uint16_t Length)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1)
- {
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((pData1 == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((pData2 == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
- else
- {
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
-
- case TIM_CHANNEL_ALL:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- default:
- break;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if (Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 and 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief TIM IRQ handler management
- *
-@verbatim
- ==============================================================================
- ##### IRQ handler management #####
- ==============================================================================
- [..]
- This section provides Timer IRQ handler function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- /* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- }
- /* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
-#else
- HAL_TIMEx_BreakCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief TIM Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the DMA Burst Mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM Output Compare Channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM Output Compare handle
- * @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 1 in Output Compare */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 2 in Output Compare */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 3 in Output Compare */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- default:
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Input Capture Channels according to the specified
- * parameters in the TIM_IC_InitTypeDef.
- * @param htim TIM IC handle
- * @param sConfig TIM Input Capture configuration structure
- * @param Channel TIM Channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- if (Channel == TIM_CHANNEL_1)
- {
- /* TI1 Configuration */
- TIM_TI1_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->ICPrescaler;
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- /* TI2 Configuration */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
- }
- else if (Channel == TIM_CHANNEL_3)
- {
- /* TI3 Configuration */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- TIM_TI3_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC3PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- htim->Instance->CCMR2 |= sConfig->ICPrescaler;
- }
- else
- {
- /* TI4 Configuration */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- TIM_TI4_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC4PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
- }
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM PWM handle
- * @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be configured
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- break;
- }
-
- default:
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM One Pulse Channels according to the specified
- * parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim TIM One Pulse handle
- * @param sConfig TIM One Pulse configuration structure
- * @param OutputChannel TIM output channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel TIM input Channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @note To output a waveform with a minimum delay user can enable the fast
- * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
- * output is forced in response to the edge detection on TIx input,
- * without taking in account the comparison.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
- uint32_t OutputChannel, uint32_t InputChannel)
-{
- TIM_OC_InitTypeDef temp1;
-
- /* Check the parameters */
- assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
- assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
- if (OutputChannel != InputChannel)
- {
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Extract the Output compare configuration from sConfig structure */
- temp1.OCMode = sConfig->OCMode;
- temp1.Pulse = sConfig->Pulse;
- temp1.OCPolarity = sConfig->OCPolarity;
- temp1.OCNPolarity = sConfig->OCNPolarity;
- temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
-
- switch (OutputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_OC1_SetConfig(htim->Instance, &temp1);
- break;
- }
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_OC2_SetConfig(htim->Instance, &temp1);
- break;
- }
- default:
- break;
- }
-
- switch (InputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
- }
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
- }
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @note This function should be used only when BurstLength is equal to DMA data transfer length.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
-{
- return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
-}
-
-/**
- * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @param DataLength Data length. This parameter can be one value
- * between 1 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
- uint32_t BurstLength, uint32_t DataLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
- if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
- {
- if ((BurstBuffer == NULL) && (BurstLength > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
- }
- }
- else
- {
- /* nothing to do */
- }
- switch (BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC4:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_COM:
- {
- /* Set the DMA commutation callbacks */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA trigger callbacks */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- default:
- break;
- }
-
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM DMA Burst mode
- * @param htim TIM handle
- * @param BurstRequestSrc TIM DMA Request sources to disable
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch (BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
- break;
- }
- case TIM_DMA_CC1:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
- case TIM_DMA_CC2:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
- case TIM_DMA_CC3:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
- case TIM_DMA_CC4:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
- case TIM_DMA_COM:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- break;
- }
- case TIM_DMA_TRIGGER:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
- break;
- }
- default:
- break;
- }
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @note This function should be used only when BurstLength is equal to DMA data transfer length.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
-{
- return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @param DataLength Data length. This parameter can be one value
- * between 1 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
- uint32_t BurstLength, uint32_t DataLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
- if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
- {
- if ((BurstBuffer == NULL) && (BurstLength > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
- }
- }
- else
- {
- /* nothing to do */
- }
- switch (BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC1:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC2:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC3:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC4:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_COM:
- {
- /* Set the DMA commutation callbacks */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA trigger callbacks */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- default:
- break;
- }
-
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA burst reading
- * @param htim TIM handle
- * @param BurstRequestSrc TIM DMA Request sources to disable.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch (BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
- break;
- }
- case TIM_DMA_CC1:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
- case TIM_DMA_CC2:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
- case TIM_DMA_CC3:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
- case TIM_DMA_CC4:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
- case TIM_DMA_COM:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- break;
- }
- case TIM_DMA_TRIGGER:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
- break;
- }
- default:
- break;
- }
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Generate a software event
- * @param htim TIM handle
- * @param EventSource specifies the event source.
- * This parameter can be one of the following values:
- * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
- * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EVENTSOURCE_COM: Timer COM event source
- * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
- * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
- * @note Basic timers can only generate an update event.
- * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
- * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
- * supporting a break input.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the event sources */
- htim->Instance->EGR = EventSource;
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configures the OCRef clear feature
- * @param htim TIM handle
- * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
- TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (sClearInputConfig->ClearInputSource)
- {
- case TIM_CLEARINPUTSOURCE_NONE:
- {
- /* Clear the OCREF clear selection bit and the the ETR Bits */
- CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
- break;
- }
-
- case TIM_CLEARINPUTSOURCE_ETR:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
- if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
- {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
- break;
- }
-
- default:
- break;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 1 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 1 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
- }
- break;
- }
- case TIM_CHANNEL_2:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 2 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 2 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- break;
- }
- case TIM_CHANNEL_3:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 3 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 3 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- break;
- }
- case TIM_CHANNEL_4:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 4 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 4 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- break;
- }
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the clock source to be used
- * @param htim TIM handle
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
- uint32_t tmpsmcr;
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- htim->Instance->SMCR = tmpsmcr;
-
- switch (sClockSourceConfig->ClockSource)
- {
- case TIM_CLOCKSOURCE_INTERNAL:
- {
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- break;
- }
-
- case TIM_CLOCKSOURCE_ETRMODE1:
- {
- /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
-
- /* Select the External clock mode1 and the ETRF trigger */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- break;
- }
-
- case TIM_CLOCKSOURCE_ETRMODE2:
- {
- /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Enable the External clock mode2 */
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- break;
- }
-
- case TIM_CLOCKSOURCE_TI1:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- break;
- }
-
- case TIM_CLOCKSOURCE_TI2:
- {
- /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI2 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- break;
- }
-
- case TIM_CLOCKSOURCE_TI1ED:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- break;
- }
-
- case TIM_CLOCKSOURCE_ITR0:
- case TIM_CLOCKSOURCE_ITR1:
- case TIM_CLOCKSOURCE_ITR2:
- case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
-
- default:
- break;
- }
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Selects the signal connected to the TI1 input: direct from CH1_input
- * or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim TIM handle.
- * @param TI1_Selection Indicate whether or not channel 1 is connected to the
- * output of a XOR gate.
- * This parameter can be one of the following values:
- * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
- * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
- * pins are connected to the TI1 input (XOR combination)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
- uint32_t tmpcr2;
-
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Reset the TI1 selection */
- tmpcr2 &= ~TIM_CR2_TI1S;
-
- /* Set the TI1 selection */
- tmpcr2 |= TI1_Selection;
-
- /* Write to TIMxCR2 */
- htim->Instance->CR2 = tmpcr2;
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode
- * @param htim TIM handle.
- * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the Slave mode
- * (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
- {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- /* Disable Trigger Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode in interrupt mode
- * @param htim TIM handle.
- * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the Slave mode
- * (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
- {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- /* Enable Trigger Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read the captured value from Capture Compare unit
- * @param htim TIM handle.
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval Captured value
- */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpreg = 0U;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
-
- break;
- }
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
-
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
-
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
-
- break;
- }
-
- default:
- break;
- }
-
- return tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Callbacks functions #####
- ==============================================================================
- [..]
- This section provides TIM callback functions:
- (+) TIM Period elapsed callback
- (+) TIM Output Compare callback
- (+) TIM Input capture callback
- (+) TIM Trigger callback
- (+) TIM Error callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Period elapsed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Period elapsed half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Output Compare callback in non-blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Input Capture callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Input Capture half complete callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWM Pulse finished callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWM Pulse finished half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timer error callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_ErrorCallback could be implemented in the user file
- */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief Register a User TIM callback to be used instead of the weak predefined callback
- * @param htim tim handle
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
- * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
- * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
- * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
- * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
- * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
- * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
- * @param pCallback pointer to the callback function
- * @retval status
- */
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
- pTIM_CallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL)
- {
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(htim);
-
- if (htim->State == HAL_TIM_STATE_READY)
- {
- switch (CallbackID)
- {
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- htim->PeriodElapsedCallback = pCallback;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
- htim->PeriodElapsedHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_TRIGGER_CB_ID :
- htim->TriggerCallback = pCallback;
- break;
-
- case HAL_TIM_TRIGGER_HALF_CB_ID :
- htim->TriggerHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_CB_ID :
- htim->IC_CaptureCallback = pCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
- htim->IC_CaptureHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- htim->OC_DelayElapsedCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- htim->PWM_PulseFinishedCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
- htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_ERROR_CB_ID :
- htim->ErrorCallback = pCallback;
- break;
-
- case HAL_TIM_COMMUTATION_CB_ID :
- htim->CommutationCallback = pCallback;
- break;
-
- case HAL_TIM_COMMUTATION_HALF_CB_ID :
- htim->CommutationHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_BREAK_CB_ID :
- htim->BreakCallback = pCallback;
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (htim->State == HAL_TIM_STATE_RESET)
- {
- switch (CallbackID)
- {
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Unregister a TIM callback
- * TIM callback is redirected to the weak predefined callback
- * @param htim tim handle
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
- * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
- * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
- * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
- * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
- * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
- * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
- * @retval status
- */
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(htim);
-
- if (htim->State == HAL_TIM_STATE_READY)
- {
- switch (CallbackID)
- {
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
- break;
-
- case HAL_TIM_TRIGGER_CB_ID :
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
- break;
-
- case HAL_TIM_TRIGGER_HALF_CB_ID :
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
- break;
-
- case HAL_TIM_IC_CAPTURE_CB_ID :
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
- break;
-
- case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
- break;
-
- case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
- break;
-
- case HAL_TIM_ERROR_CB_ID :
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
- break;
-
- case HAL_TIM_COMMUTATION_CB_ID :
- htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
- break;
-
- case HAL_TIM_COMMUTATION_HALF_CB_ID :
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
- break;
-
- case HAL_TIM_BREAK_CB_ID :
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (htim->State == HAL_TIM_STATE_RESET)
- {
- switch (CallbackID)
- {
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return status;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief TIM Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Base handle state.
- * @param htim TIM Base handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM OC handle state.
- * @param htim TIM Output Compare handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM PWM handle state.
- * @param htim TIM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Input Capture handle state.
- * @param htim TIM IC handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM One Pulse Mode handle state.
- * @param htim TIM OPM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode handle state.
- * @param htim TIM Encoder Interface handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode handle state.
- * @param htim TIM handle
- * @retval Active channel
- */
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
-{
- return htim->Channel;
-}
-
-/**
- * @brief Return actual state of the TIM channel.
- * @param htim TIM handle
- * @param Channel TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_CHANNEL_5: TIM Channel 5
- * @arg TIM_CHANNEL_6: TIM Channel 6
- * @retval TIM Channel state
- */
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_TIM_ChannelStateTypeDef channel_state;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
- return channel_state;
-}
-
-/**
- * @brief Return actual state of a DMA burst operation.
- * @param htim TIM handle
- * @retval DMA burst state
- */
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
- return htim->DMABurstState;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-
-/**
- * @brief TIM DMA error callback
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->ErrorCallback(htim);
-#else
- HAL_TIM_ErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Delay Pulse half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedHalfCpltCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Capture complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Capture half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureHalfCpltCallback(htim);
-#else
- HAL_TIM_IC_CaptureHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
- {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Period Elapse half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedHalfCpltCallback(htim);
-#else
- HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Trigger callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
- {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Trigger half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerHalfCpltCallback(htim);
-#else
- HAL_TIM_TriggerHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief Time Base configuration
- * @param TIMx TIM peripheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- uint32_t tmpcr1;
- tmpcr1 = TIMx->CR1;
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- tmpcr1 |= Structure->CounterMode;
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = Structure->Prescaler;
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter (only for advanced timer) value immediately */
- TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
- * @brief Timer Output Compare 1 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- tmpcr2 &= ~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 2 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
-
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- tmpcr2 &= ~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 3 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- tmpcr2 &= ~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 4 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- tmpccmrx &= ~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
-
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Slave Timer configuration function
- * @param htim TIM handle
- * @param sSlaveConfig Slave timer configuration
- * @retval None
- */
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the Trigger Selection Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source */
- tmpsmcr |= sSlaveConfig->InputTrigger;
-
- /* Reset the slave mode Bits */
- tmpsmcr &= ~TIM_SMCR_SMS;
- /* Set the slave mode */
- tmpsmcr |= sSlaveConfig->SlaveMode;
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Configure the trigger prescaler, filter, and polarity */
- switch (sSlaveConfig->InputTrigger)
- {
- case TIM_TS_ETRF:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- /* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_TI1F_ED:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
- {
- return HAL_ERROR;
- }
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = htim->Instance->CCER;
- htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
- break;
- }
-
- case TIM_TS_TI1FP1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI1 Filter and Polarity */
- TIM_TI1_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_TI2FP2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI2 Filter and Polarity */
- TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_ITR0:
- case TIM_TS_ITR1:
- case TIM_TS_ITR2:
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
-
- default:
- break;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
- }
- else
- {
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
- }
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI1.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4U);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= TIM_ICPolarity;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
- * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI2.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12U);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2;
- uint32_t tmpccer;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC3S;
- tmpccmr2 |= TIM_ICSelection;
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= ~(TIM_CCER_CC3P);
- tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- * @retval None
- */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2;
- uint32_t tmpccer;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= ~(TIM_CCER_CC4P);
- tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx to select the TIM peripheral
- * @param InputTriggerSource The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
- uint32_t tmpsmcr;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx to select the TIM peripheral
- * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
- * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
- * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
- * @param ExtTRGFilter External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- uint32_t tmpsmcr;
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- uint32_t tmp;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief Reset interrupt callbacks to the legacy weak callbacks.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-void TIM_ResetCallback(TIM_HandleTypeDef *htim)
-{
- /* Reset the TIM callback to the legacy weak callbacks */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
- htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
deleted file mode 100644
index 3b2983a..0000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
+++ /dev/null
@@ -1,2296 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_tim_ex.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer Extended peripheral:
- * + Time Hall Sensor Interface Initialization
- * + Time Hall Sensor Interface Start
- * + Time Complementary signal break and dead time configuration
- * + Time Master and Slave synchronization configuration
- * + Timer remapping capabilities configuration
- @verbatim
- ==============================================================================
- ##### TIMER Extended features #####
- ==============================================================================
- [..]
- The Timer Extended features include:
- (#) Complementary outputs with programmable dead-time for :
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and to
- interconnect several timers together.
- (#) Break input to put the timer output signals in reset state or in a known state.
- (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
- positioning purposes
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending on the selected feature:
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
- Timer Hall Sensor Interface and the commutation event with the corresponding
- Interrupt and DMA request if needed (Note that One Timer is used to interface
- with the Hall sensor Interface and another Timer should be used to use
- the commutation event).
-
- (#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
- (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIMEx TIMEx
- * @brief TIM Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
-static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Hall Sensor functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure TIM HAL Sensor.
- (+) De-initialize TIM HAL Sensor.
- (+) Start the Hall Sensor Interface.
- (+) Stop the Hall Sensor Interface.
- (+) Start the Hall Sensor Interface and enable interrupts.
- (+) Stop the Hall Sensor Interface and disable interrupts.
- (+) Start the Hall Sensor Interface and enable DMA transfers.
- (+) Stop the Hall Sensor Interface and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
- * @note When the timer instance is initialized in Hall Sensor Interface mode,
- * timer channels 1 and channel 2 are reserved and cannot be used for
- * other purpose.
- * @param htim TIM Hall Sensor Interface handle
- * @param sConfig TIM Hall Sensor configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
-{
- TIM_OC_InitTypeDef OC_Config;
-
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->HallSensor_MspInitCallback == NULL)
- {
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->HallSensor_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
- TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
- /* Enable the Hall sensor interface (XOR function of the three inputs) */
- htim->Instance->CR2 |= TIM_CR2_TI1S;
-
- /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
- /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
- /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
- OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
- OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
- OC_Config.OCMode = TIM_OCMODE_PWM2;
- OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
- OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
- OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
- OC_Config.Pulse = sConfig->Commutation_Delay;
-
- TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
- /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
- register to 101 */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
- htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Hall Sensor interface
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->HallSensor_MspDeInitCallback == NULL)
- {
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->HallSensor_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIMEx_HallSensor_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Hall Sensor MSP.
- * @param htim TIM Hall Sensor Interface handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim TIM Hall Sensor Interface handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall sensor Interface.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the capture compare Interrupts 1 event */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts event */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM Hall Sensor Interface handle
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel state */
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Set the DMA Input Capture 1 Callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel for Capture 1*/
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the capture compare 1 Interrupt */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-
- /* Disable the capture compare Interrupts 1 event */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary Output Compare/PWM.
- (+) Stop the Complementary Output Compare/PWM.
- (+) Start the Complementary Output Compare/PWM and enable interrupts.
- (+) Stop the Complementary Output Compare/PWM and disable interrupts.
- (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
- (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim TIM OC handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
-
- default:
- break;
- }
-
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpccer;
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary PWM.
- (+) Stop the Complementary PWM.
- (+) Start the Complementary PWM and enable interrupts.
- (+) Stop the Complementary PWM and disable interrupts.
- (+) Start the Complementary PWM and enable DMA transfers.
- (+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the PWM signal generation on the complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation on the complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- default:
- break;
- }
-
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpccer;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode on the
- * complementary output
- * @param htim TIM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- default:
- break;
- }
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
- * output
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- default:
- break;
- }
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM One Pulse signal generation on the complementary
- * output.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
- HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Check the TIM channels state */
- if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the complementary One Pulse output channel and the Input Capture channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation on the complementary
- * output.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the complementary One Pulse output channel and the Input Capture channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
- HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Check the TIM channels state */
- if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- /* Enable the complementary One Pulse output channel and the Input Capture channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the complementary One Pulse output channel and the Input Capture channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure the commutation event in case of use of the Hall sensor interface.
- (+) Configure Output channels for OC and PWM mode.
-
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master synchronization.
- (+) Configure timer remapping capabilities.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the TIM commutation event sequence.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Disable Commutation Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
-
- /* Disable Commutation DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with interrupt.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Disable Commutation DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
-
- /* Enable the Commutation Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with DMA.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation DMA Request */
- /* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-
- /* Disable Commutation Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
-
- /* Enable the Commutation DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in master mode.
- * @param htim TIM handle.
- * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
- * contains the selected trigger output (TRGO) and the Master/Slave
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig)
-{
- uint32_t tmpcr2;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Change the handler state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
-
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param htim TIM handle
- * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @note Interrupts can be generated when an active level is detected on the
- * break input, the break 2 input or the system break input. Break
- * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
-{
- /* Keep this variable initialized to 0 as it is used to configure BDTR register */
- uint32_t tmpbdtr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
- assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
- assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
- assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
- assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
- assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
-
-
- /* Set TIMx_BDTR */
- htim->Instance->BDTR = tmpbdtr;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIMx Remapping input capabilities.
- * @param htim TIM handle.
- * @param Remap specifies the TIM remapping source.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- UNUSED(Remap);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Callbacks functions #####
- ==============================================================================
- [..]
- This section provides Extended TIM callback functions:
- (+) Timer Commutation callback
- (+) Timer Break callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Hall commutation changed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutCallback could be implemented in the user file
- */
-}
-/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Break detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Hall Sensor interface handle state.
- * @param htim TIM Hall Sensor handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return actual state of the TIM complementary channel.
- * @param htim TIM handle
- * @param ChannelN TIM Complementary channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @retval TIM Complementary channel state
- */
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
-{
- HAL_TIM_ChannelStateTypeDef channel_state;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
-
- channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
-
- return channel_state;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
- * @{
- */
-
-/**
- * @brief TIM DMA Commutation callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Commutation half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationHalfCpltCallback(htim);
-#else
- HAL_TIMEx_CommutHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-
-/**
- * @brief TIM DMA Delay Pulse complete callback (complementary channel).
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA error callback (complementary channel)
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->ErrorCallback(htim);
-#else
- HAL_TIM_ErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
- * @retval None
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
-{
- uint32_t tmp;
-
- tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
-}
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c
new file mode 100644
index 0000000..2b237fc
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c
@@ -0,0 +1,314 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_dma.c
+ * @author MCD Application Team
+ * @brief DMA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_dma.h"
+#include "stm32f1xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#if defined (DMA2)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+ (((INSTANCE) == DMA2) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#endif
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the DMA registers to their default reset values.
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are de-initialized
+ * - ERROR: DMA registers are not de-initialized
+ */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
+ ErrorStatus status = SUCCESS;
+
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Disable the selected DMAx_Channely */
+ CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+ /* Reset DMAx_Channely control register */
+ LL_DMA_WriteReg(tmp, CCR, 0U);
+
+ /* Reset DMAx_Channely remaining bytes register */
+ LL_DMA_WriteReg(tmp, CNDTR, 0U);
+
+ /* Reset DMAx_Channely peripheral address register */
+ LL_DMA_WriteReg(tmp, CPAR, 0U);
+
+ /* Reset DMAx_Channely memory address register */
+ LL_DMA_WriteReg(tmp, CMAR, 0U);
+
+ if (Channel == LL_DMA_CHANNEL_1)
+ {
+ /* Reset interrupt pending bits for DMAx Channel1 */
+ LL_DMA_ClearFlag_GI1(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_2)
+ {
+ /* Reset interrupt pending bits for DMAx Channel2 */
+ LL_DMA_ClearFlag_GI2(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_3)
+ {
+ /* Reset interrupt pending bits for DMAx Channel3 */
+ LL_DMA_ClearFlag_GI3(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_4)
+ {
+ /* Reset interrupt pending bits for DMAx Channel4 */
+ LL_DMA_ClearFlag_GI4(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_5)
+ {
+ /* Reset interrupt pending bits for DMAx Channel5 */
+ LL_DMA_ClearFlag_GI5(DMAx);
+ }
+
+ else if (Channel == LL_DMA_CHANNEL_6)
+ {
+ /* Reset interrupt pending bits for DMAx Channel6 */
+ LL_DMA_ClearFlag_GI6(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_7)
+ {
+ /* Reset interrupt pending bits for DMAx Channel7 */
+ LL_DMA_ClearFlag_GI7(DMAx);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+ * @arg @ref __LL_DMA_GET_INSTANCE
+ * @arg @ref __LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Check the DMA parameters from DMA_InitStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+ assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+ assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+ assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+ assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+ assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+ assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+ /*---------------------------- DMAx CCR Configuration ------------------------
+ * Configure DMAx_Channely: data transfer direction, data transfer mode,
+ * peripheral and memory increment mode,
+ * data size alignment and priority level with parameters :
+ * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+ * - Mode: DMA_CCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
+ * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+ * - Priority: DMA_CCR_PL[1:0] bits
+ */
+ LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
+ DMA_InitStruct->Mode | \
+ DMA_InitStruct->PeriphOrM2MSrcIncMode | \
+ DMA_InitStruct->MemoryOrM2MDstIncMode | \
+ DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+ DMA_InitStruct->MemoryOrM2MDstDataSize | \
+ DMA_InitStruct->Priority);
+
+ /*-------------------------- DMAx CMAR Configuration -------------------------
+ * Configure the memory or destination base address with parameter :
+ * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+ */
+ LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+ /*-------------------------- DMAx CPAR Configuration -------------------------
+ * Configure the peripheral or source base address with parameter :
+ * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+ */
+ LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+ /*--------------------------- DMAx CNDTR Configuration -----------------------
+ * Configure the peripheral base address with parameter :
+ * - NbData: DMA_CNDTR_NDT[15:0] bits
+ */
+ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
+ * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval None
+ */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Set DMA_InitStruct fields to default values */
+ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
+ DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
+ DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
+ DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ DMA_InitStruct->NbData = 0x00000000U;
+ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c
new file mode 100644
index 0000000..1692ab1
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c
@@ -0,0 +1,215 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_exti.c
+ * @author MCD Application Team
+ * @brief EXTI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_exti.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the EXTI registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are de-initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_DeInit(void)
+{
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR, 0x00000000U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER, 0x00000000U);
+ /* Pending register clear */
+ LL_EXTI_WriteReg(PR, 0x000FFFFFU);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+ assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+ /* ENABLE LineCommand */
+ if (EXTI_InitStruct->LineCommand != DISABLE)
+ {
+ assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+ /* Configure EXTI Lines in range from 0 to 31 */
+ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+ }
+ /* DISABLE LineCommand */
+ else
+ {
+ /* De-configure EXTI Lines in range from 0 to 31 */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
+ * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval None
+ */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
+ EXTI_InitStruct->LineCommand = DISABLE;
+ EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
+ EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (EXTI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c
new file mode 100644
index 0000000..2b44d83
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c
@@ -0,0 +1,253 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_gpio.h"
+#include "stm32f1xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_GPIO_PIN(__VALUE__) ((((__VALUE__) & LL_GPIO_PIN_ALL)!= 0u) &&\
+ (((__VALUE__) & (~LL_GPIO_PIN_ALL))== 0u))
+
+#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_ANALOG) ||\
+ ((__VALUE__) == LL_GPIO_MODE_FLOATING) ||\
+ ((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE))
+
+#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
+ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_DOWN) ||\
+ ((__VALUE__) == LL_GPIO_PULL_UP))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize GPIO registers (Registers restored to their default values).
+ * @param GPIOx GPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are de-initialized
+ * - ERROR: Wrong GPIO Port
+ */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Force and Release reset on clock of GPIOx Port */
+ if (GPIOx == GPIOA)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD);
+ }
+#if defined(GPIOE)
+ else if (GPIOx == GPIOE)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE);
+ }
+#endif
+#if defined(GPIOF)
+ else if (GPIOx == GPIOF)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF);
+ }
+#endif
+#if defined(GPIOG)
+ else if (GPIOx == GPIOG)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG);
+ }
+#endif
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ * @param GPIOx GPIO Port
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * that contains the configuration information for the specified GPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ uint32_t pinmask;
+ uint32_t pinpos;
+ uint32_t currentpin;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+
+ pinmask = ((GPIO_InitStruct->Pin) << GPIO_PIN_MASK_POS) >> GPIO_PIN_NB;
+ pinpos = POSITION_VAL(pinmask);
+
+ /* Configure the port pins */
+ while ((pinmask >> pinpos) != 0u)
+ {
+ /* skip if bit is not set */
+ if ((pinmask & (1u << pinpos)) != 0u)
+ {
+ /* Get current io position */
+ if (pinpos < GPIO_PIN_MASK_POS)
+ {
+ currentpin = (0x00000101uL << pinpos);
+ }
+ else
+ {
+ currentpin = ((0x00010001u << (pinpos - GPIO_PIN_MASK_POS)) | 0x04000000u);
+ }
+
+ /* Check Pin Mode and Pin Pull parameters */
+ assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+ /* Pull-up Pull-down resistor configuration*/
+ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check speed and Output mode parameters */
+ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Speed mode configuration */
+ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
+ }
+ }
+ pinpos++;
+ }
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
+ GPIO_InitStruct->Mode = LL_GPIO_MODE_FLOATING;
+ GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+ GPIO_InitStruct->Pull = LL_GPIO_PULL_DOWN;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c
new file mode 100644
index 0000000..036adea
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c
@@ -0,0 +1,86 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_pwr.c
+ * @author MCD Application Team
+ * @brief PWR LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_pwr.h"
+#include "stm32f1xx_ll_bus.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PWR_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the PWR registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PWR registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_PWR_DeInit(void)
+{
+ /* Force reset of PWR clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ /* Release reset of PWR clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(PWR) */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c
new file mode 100644
index 0000000..9ab07cf
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c
@@ -0,0 +1,474 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_rcc.c
+ * @author MCD Application Team
+ * @brief RCC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+ * @{
+ */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(USB) || defined(USB_OTG_FS)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+#endif /* USB */
+
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+ * @{
+ */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+#if defined(RCC_PLLI2S_SUPPORT)
+uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLL2_SUPPORT)
+uint32_t RCC_PLL2_GetFreqClockFreq(void);
+#endif /* RCC_PLL2_SUPPORT */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE PLL, PLL2 & PLL3 are OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RCC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ LL_RCC_HSI_Enable();
+
+ /* Wait for HSI READY bit */
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {}
+
+ /* Configure HSI as system clock source */
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+
+ /* Wait till clock switch is ready */
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+ {}
+
+ /* Reset PLLON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+ /* Wait for PLL READY bit to be reset */
+ while (LL_RCC_PLL_IsReady() != 0U)
+ {}
+
+ /* Reset CFGR register */
+ LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+ /* Reset HSEON, HSEBYP & CSSON bits */
+ CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
+
+#if defined(RCC_CR_PLL2ON)
+ /* Reset PLL2ON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+#endif /* RCC_CR_PLL2ON */
+
+#if defined(RCC_CR_PLL3ON)
+ /* Reset PLL3ON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+#endif /* RCC_CR_PLL3ON */
+
+ /* Set HSITRIM bits to the reset value */
+ LL_RCC_HSI_SetCalibTrimming(0x10U);
+
+#if defined(RCC_CFGR2_PREDIV1)
+ /* Reset CFGR2 register */
+ LL_RCC_WriteReg(CFGR2, 0x00000000U);
+#endif /* RCC_CFGR2_PREDIV1 */
+
+ /* Disable all interrupts */
+ LL_RCC_WriteReg(CIR, 0x00000000U);
+
+ /* Clear reset flags */
+ LL_RCC_ClearResetFlags();
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * and different peripheral clocks available on the device.
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ * @note If SYSCLK source is PLL, function returns values based on
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ * @note (**) HSI_VALUE is a defined constant but the real value may vary
+ * depending on the variations in voltage and temperature.
+ * @note (***) HSE_VALUE is a defined constant, user has to ensure that
+ * HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ * @note The result of this function could be incorrect when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ * @{
+ */
+
+/**
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update structure fields. Otherwise, any
+ * configuration based on this function will be incorrect.
+ * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+ * @retval None
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+ /* Get SYSCLK frequency */
+ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/**
+ * @brief Return I2Sx clock frequency
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE
+ * @retval I2S clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+{
+ uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+
+ /* I2S1CLK clock frequency */
+ switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ {
+ case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
+ case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
+ i2s_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
+ case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
+ default:
+ i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
+ break;
+ }
+
+ return i2s_frequency;
+}
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB) || defined(USB_OTG_FS)
+/**
+ * @brief Return USBx clock frequency
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval USB clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
+ */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+ uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+ /* USBCLK clock frequency */
+ switch (LL_RCC_GetUSBClockSource(USBxSource))
+ {
+#if defined(RCC_CFGR_USBPRE)
+ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
+ }
+ break;
+#endif /* RCC_CFGR_USBPRE */
+#if defined(RCC_CFGR_OTGFSPRE)
+ /* USBCLK = PLLVCO/2
+ = (2 x PLLCLK) / 2
+ = PLLCLK */
+ case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ break;
+
+ /* USBCLK = PLLVCO/3
+ = (2 x PLLCLK) / 3 */
+ case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
+ }
+ break;
+#endif /* RCC_CFGR_OTGFSPRE */
+ }
+
+ return usb_frequency;
+}
+#endif /* USB */
+
+/**
+ * @brief Return ADCx clock frequency
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval ADC clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+ uint32_t adc_prescaler = 0U;
+ uint32_t adc_frequency = 0U;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
+
+ /* Get ADC prescaler */
+ adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
+
+ /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
+ adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
+ / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
+
+ return adc_frequency;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Return SYSTEM clock frequency
+ * @retval SYSTEM clock frequency (in Hz)
+ */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+ uint32_t frequency = 0U;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (LL_RCC_GetSysClkSource())
+ {
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ frequency = HSI_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ frequency = HSE_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
+ frequency = RCC_PLL_GetFreqDomain_SYS();
+ break;
+
+ default:
+ frequency = HSI_VALUE;
+ break;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Return HCLK clock frequency
+ * @param SYSCLK_Frequency SYSCLK clock frequency
+ * @retval HCLK clock frequency (in Hz)
+ */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+ * @brief Return PCLK1 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+ * @brief Return PCLK2 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK2 clock frequency */
+ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
+
+ /* Get PLL source */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE / 2U;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
+ break;
+
+#if defined(RCC_PLL2_SUPPORT)
+ case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
+ pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
+ break;
+#endif /* RCC_PLL2_SUPPORT */
+
+ default:
+ pllinputfreq = HSI_VALUE / 2U;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
+}
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL2_GetFreqClockFreq(void)
+{
+ return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
+{
+ return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c
new file mode 100644
index 0000000..7e3adfc
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c
@@ -0,0 +1,530 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_spi.c
+ * @author MCD Application Team
+ * @brief SPI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_spi.h"
+#include "stm32f1xx_ll_bus.h"
+#include "stm32f1xx_ll_rcc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @addtogroup SPI_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+ * @{
+ */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
+ SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
+ SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
+ SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
+ SPI_CR1_BIDIMODE)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @{
+ */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+ if (SPIx == SPI1)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ status = SUCCESS;
+ }
+#endif /* SPI1 */
+#if defined(SPI2)
+ if (SPIx == SPI2)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ status = SUCCESS;
+ }
+#endif /* SPI2 */
+#if defined(SPI3)
+ if (SPIx == SPI3)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ status = SUCCESS;
+ }
+#endif /* SPI3 */
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the SPI Instance SPIx*/
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Check the SPI parameters from SPI_InitStruct*/
+ assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+ assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+ if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx CR1 Configuration ------------------------
+ * Configure SPIx CR1 with parameters:
+ * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+ * - Master/Slave Mode: SPI_CR1_MSTR bit
+ * - DataWidth: SPI_CR1_DFF bit
+ * - ClockPolarity: SPI_CR1_CPOL bit
+ * - ClockPhase: SPI_CR1_CPHA bit
+ * - NSS management: SPI_CR1_SSM bit
+ * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+ * - BitOrder: SPI_CR1_LSBFIRST bit
+ * - CRCCalculation: SPI_CR1_CRCEN bit
+ */
+ MODIFY_REG(SPIx->CR1,
+ SPI_CR1_CLEAR_MASK,
+ SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
+ SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+ SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+ SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+ /*---------------------------- SPIx CR2 Configuration ------------------------
+ * Configure SPIx CR2 with parameters:
+ * - NSS management: SSOE bit
+ */
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
+
+ /*---------------------------- SPIx CRCPR Configuration ----------------------
+ * Configure SPIx CRCPR with parameters:
+ * - CRCPoly: CRCPOLY[15:0] bits
+ */
+ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ }
+ status = SUCCESS;
+ }
+
+#if defined (SPI_I2S_SUPPORT)
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2S_SUPPORT */
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ /* Set SPI_InitStruct fields to default values */
+ SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
+ SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
+ SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct->CRCPoly = 7U;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup I2S_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+ * @{
+ */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK 0x0002U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+ * @{
+ */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI/I2S registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_DeInit(SPIx);
+}
+
+/**
+ * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are Initialized
+ * - ERROR: SPI registers are not Initialized
+ */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint32_t i2sdiv = 2U;
+ uint32_t i2sodd = 0U;
+ uint32_t packetlength = 1U;
+ uint32_t tmp;
+ LL_RCC_ClocksTypeDef rcc_clocks;
+ uint32_t sourceclock;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+ assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(SPIx->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD);
+
+ /*---------------------------- SPIx I2SPR Configuration ----------------------
+ * Configure SPIx I2SPR with parameters:
+ * - MCLKOutput: SPI_I2SPR_MCKOE bit
+ * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+ */
+
+ /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+ * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
+ */
+ if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing)
+ * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+ */
+ if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2U;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = rcc_clocks.SYSCLK_Frequency;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (tmp & (uint16_t)0x0001U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = ((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
+ I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
+ I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
+ I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
+ I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
+ I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
+}
+
+/**
+ * @brief Set linear and parity prescaler.
+ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+ * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+ assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+ /* Write to SPIx I2SPR */
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c
new file mode 100644
index 0000000..e1435b0
--- /dev/null
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c
@@ -0,0 +1,624 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_utils.c
+ * @author MCD Application Team
+ * @brief UTILS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_rcc.h"
+#include "stm32f1xx_ll_utils.h"
+#include "stm32f1xx_ll_system.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UTILS_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+ * @{
+ */
+
+/* Defines used for PLL range */
+#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#if defined(FLASH_ACR_LATENCY)
+#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
+#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
+#else
+/*!< No Latency Configuration in this device */
+#endif
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#if defined(RCC_CFGR_PLLMULL6_5)
+#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
+#else
+#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_16))
+#endif /* RCC_CFGR_PLLMULL6_5 */
+
+#if defined(RCC_CFGR2_PREDIV1)
+#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
+#else
+#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
+#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
+
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+ * @{
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
+ * @note When a RTOS is used, it is recommended to avoid changing the Systick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on SysTick counter flag
+ * @note When a RTOS is used, it is recommended to avoid using blocking delay
+ * and use rather osDelay service.
+ * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ * will configure Systick to 1ms
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+
+ /* Add a period to guaranty minimum wait */
+ if (Delay < LL_MAX_DELAY)
+ {
+ Delay++;
+ }
+
+ while (Delay)
+ {
+ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ {
+ Delay--;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
+ @endverbatim
+ @internal
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ (++) +-----------------------------------------------+
+ (++) | Latency | SYSCLK clock frequency (MHz) |
+ (++) |---------------|-------------------------------|
+ (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ (++) |---------------|-------------------------------|
+ (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ (++) |---------------|-------------------------------|
+ (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+ (++) +-----------------------------------------------+
+ @endinternal
+ * @{
+ */
+
+/**
+ * @brief This function sets directly SystemCoreClock CMSIS variable.
+ * @note Variable can be calculated also through SystemCoreClockUpdate function.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+}
+
+/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param Frequency SYSCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+#if defined(FLASH_ACR_LATENCY)
+ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
+{
+ uint32_t timeout;
+ uint32_t getlatency;
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+ ErrorStatus status = SUCCESS;
+
+ /* Frequency cannot be equal to 0 */
+ if (Frequency == 0U)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (Frequency > UTILS_LATENCY2_FREQ)
+ {
+ /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if (Frequency > UTILS_LATENCY1_FREQ)
+ {
+ /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ else
+ {
+ /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
+ latency = LL_FLASH_LATENCY_0;
+ }
+ }
+
+ if (status != ERROR)
+ {
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ timeout = 2;
+ do
+ {
+ /* Wait for Flash latency to be updated */
+ getlatency = LL_FLASH_GetLatency();
+ timeout--;
+ } while ((getlatency != latency) && (timeout > 0));
+
+ if(getlatency != latency)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ }
+
+ return status;
+}
+#endif /* FLASH_ACR_LATENCY */
+
+/**
+ * @brief This function configures system clock with HSI as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
+ * - PREDIV: Set to 2 for few devices
+ * - PLLMUL: The application software must set correctly the PLL multiplication factor to
+ * not exceed 72MHz
+ * @note FLASH latency can be modified through this function.
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ /* Check PREDIV value */
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
+#else
+ /* Force PREDIV value to 2 */
+ UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+ /* Enable HSI if not enabled */
+ if (LL_RCC_HSI_IsReady() != 1U)
+ {
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {
+ /* Wait for HSI ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with HSE as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
+ * - PREDIV: Set to 2 for few devices
+ * - PLLMUL: The application software must set correctly the PLL multiplication factor to
+ * not exceed @ref UTILS_PLL_OUTPUT_MAX
+ * @note FLASH latency can be modified through this function.
+ * @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
+ * @param HSEBypass This parameter can be one of the following values:
+ * @arg @ref LL_UTILS_HSEBYPASS_ON
+ * @arg @ref LL_UTILS_HSEBYPASS_OFF
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+ assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
+
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+ /* Enable HSE if not enabled */
+ if (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Check if need to enable HSE bypass feature or not */
+ if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ {
+ LL_RCC_HSE_EnableBypass();
+ }
+ else
+ {
+ LL_RCC_HSE_DisableBypass();
+ }
+
+ /* Enable HSE */
+ LL_RCC_HSE_Enable();
+ while (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Wait for HSE ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
+/**
+ * @brief Function to check that PLL can be modified
+ * @param PLL_InputFrequency PLL input frequency (in Hz)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @retval PLL output frequency (in Hz)
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
+
+ /* Check different PLL parameters according to RM */
+#if defined (RCC_CFGR2_PREDIV1)
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
+#else
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+ return pllfreq;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PLL modification can be done
+ * - ERROR: PLL is busy
+ */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check if PLL is busy*/
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ /* PLL configuration cannot be modified */
+ status = ERROR;
+ }
+#if defined(RCC_PLL2_SUPPORT)
+ /* Check if PLL2 is busy*/
+ if (LL_RCC_PLL2_IsReady() != 0U)
+ {
+ /* PLL2 configuration cannot be modified */
+ status = ERROR;
+ }
+#endif /* RCC_PLL2_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+ /* Check if PLLI2S is busy*/
+ if (LL_RCC_PLLI2S_IsReady() != 0U)
+ {
+ /* PLLI2S configuration cannot be modified */
+ status = ERROR;
+ }
+#endif /* RCC_PLLI2S_SUPPORT */
+
+ return status;
+}
+
+/**
+ * @brief Function to enable PLL and switch system clock to PLL
+ * @param SYSCLK_Frequency SYSCLK frequency
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: No problem to switch system to PLL
+ * - ERROR: Problem to switch system to PLL
+ */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+#if defined(FLASH_ACR_LATENCY)
+ uint32_t sysclk_frequency_current = 0U;
+#endif /* FLASH_ACR_LATENCY */
+
+ assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+ assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+#if defined(FLASH_ACR_LATENCY)
+ /* Calculate current SYSCLK frequency */
+ sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
+#endif /* FLASH_ACR_LATENCY */
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+#if defined (FLASH_ACR_LATENCY)
+ if (sysclk_frequency_current < SYSCLK_Frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(SYSCLK_Frequency);
+ }
+#endif /* FLASH_ACR_LATENCY */
+
+ /* Update system clock configuration */
+ if (status == SUCCESS)
+ {
+#if defined(RCC_PLL2_SUPPORT)
+ if (LL_RCC_PLL_GetMainSource() != LL_RCC_PLLSOURCE_HSI_DIV_2)
+ {
+ /* Enable PLL2 */
+ LL_RCC_PLL2_Enable();
+ while (LL_RCC_PLL2_IsReady() != 1U)
+ {
+ /* Wait for PLL2 ready */
+ }
+ }
+#endif /* RCC_PLL2_SUPPORT */
+ /* Enable PLL */
+ LL_RCC_PLL_Enable();
+ while (LL_RCC_PLL_IsReady() != 1U)
+ {
+ /* Wait for PLL ready */
+ }
+
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+ /* Wait for system clock switch to PLL */
+ }
+
+ /* Set APB1 & APB2 prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+#if defined (FLASH_ACR_LATENCY)
+ if (sysclk_frequency_current > SYSCLK_Frequency)
+ {
+ /* Set FLASH latency to lowest latency */
+ status = LL_SetFlashLatency(SYSCLK_Frequency);
+ }
+#endif /* FLASH_ACR_LATENCY */
+
+ /* Update SystemCoreClock variable */
+ if (status == SUCCESS)
+ {
+ LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/main.h b/Inc/main.h
index 11a739d..6175e12 100644
--- a/Inc/main.h
+++ b/Inc/main.h
@@ -28,7 +28,20 @@ extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
+#include "stm32f1xx_ll_dma.h"
+#include "stm32f1xx_ll_rcc.h"
+#include "stm32f1xx_ll_bus.h"
+#include "stm32f1xx_ll_system.h"
+#include "stm32f1xx_ll_exti.h"
+#include "stm32f1xx_ll_cortex.h"
+#include "stm32f1xx_ll_utils.h"
+#include "stm32f1xx_ll_pwr.h"
+#include "stm32f1xx_ll_spi.h"
+#include "stm32f1xx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
@@ -59,6 +72,18 @@ void Error_Handler(void);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+ 1 bit for subpriority */
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+ 0 bit for subpriority */
+#endif
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
diff --git a/Inc/spi.h b/Inc/spi.h
index 7ec5f44..52fc1ae 100644
--- a/Inc/spi.h
+++ b/Inc/spi.h
@@ -30,8 +30,6 @@
/* USER CODE END Includes */
-extern SPI_HandleTypeDef hspi1;
-
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
diff --git a/Inc/stm32_assert.h b/Inc/stm32_assert.h
new file mode 100644
index 0000000..ca09699
--- /dev/null
+++ b/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/**
+ ******************************************************************************
+ * @file stm32_assert.h
+ * @brief STM32 assert file.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f1xx_hal_conf.h b/Inc/stm32f1xx_hal_conf.h
deleted file mode 100644
index ae922e0..0000000
--- a/Inc/stm32f1xx_hal_conf.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_conf.h
- * @brief HAL configuration file.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CONF_H
-#define __STM32F1xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-
-#define HAL_MODULE_ENABLED
- /*#define HAL_ADC_MODULE_ENABLED */
-/*#define HAL_CRYP_MODULE_ENABLED */
-/*#define HAL_CAN_MODULE_ENABLED */
-/*#define HAL_CAN_LEGACY_MODULE_ENABLED */
-/*#define HAL_CEC_MODULE_ENABLED */
-/*#define HAL_CORTEX_MODULE_ENABLED */
-/*#define HAL_CRC_MODULE_ENABLED */
-/*#define HAL_DAC_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/*#define HAL_ETH_MODULE_ENABLED */
-/*#define HAL_FLASH_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-/*#define HAL_I2C_MODULE_ENABLED */
-/*#define HAL_I2S_MODULE_ENABLED */
-/*#define HAL_IRDA_MODULE_ENABLED */
-/*#define HAL_IWDG_MODULE_ENABLED */
-/*#define HAL_NOR_MODULE_ENABLED */
-/*#define HAL_NAND_MODULE_ENABLED */
-/*#define HAL_PCCARD_MODULE_ENABLED */
-/*#define HAL_PCD_MODULE_ENABLED */
-/*#define HAL_HCD_MODULE_ENABLED */
-/*#define HAL_PWR_MODULE_ENABLED */
-/*#define HAL_RCC_MODULE_ENABLED */
-/*#define HAL_RTC_MODULE_ENABLED */
-/*#define HAL_SD_MODULE_ENABLED */
-/*#define HAL_MMC_MODULE_ENABLED */
-/*#define HAL_SDRAM_MODULE_ENABLED */
-/*#define HAL_SMARTCARD_MODULE_ENABLED */
-#define HAL_SPI_MODULE_ENABLED
-/*#define HAL_SRAM_MODULE_ENABLED */
-/*#define HAL_TIM_MODULE_ENABLED */
-/*#define HAL_UART_MODULE_ENABLED */
-/*#define HAL_USART_MODULE_ENABLED */
-/*#define HAL_WWDG_MODULE_ENABLED */
-
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
- #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief Internal Low Speed oscillator (LSI) value.
- */
-#if !defined (LSI_VALUE)
- #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
-#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature. */
-
-/**
- * @brief External Low Speed oscillator (LSE) value.
- * This value is used by the UART, RTC HAL module to compute the system frequency
- */
-#if !defined (LSE_VALUE)
- #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
- === you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
- * @brief This is the HAL system configuration section
- */
-#define VDD_VALUE 3300U /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority (lowest by default) */
-#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1U
-
-#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
-#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
-#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
-#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
-#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
-#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
-#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
-#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
-#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
-#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
-#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
-#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
-#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
-#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
-#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
-#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
-#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
-#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
-#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
-#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
-#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
-#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
-#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
-
-/* ########################## Assert Selection ############################## */
-/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
-/* #define USE_FULL_ASSERT 1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0 2U
-#define MAC_ADDR1 0U
-#define MAC_ADDR2 0U
-#define MAC_ADDR3 0U
-#define MAC_ADDR4 0U
-#define MAC_ADDR5 0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB 8U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848_PHY_ADDRESS Address*/
-#define DP83848_PHY_ADDRESS 0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY 0x00000FFFU
-
-#define PHY_READ_TO 0x0000FFFFU
-#define PHY_WRITE_TO 0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
-
-#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
-#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
-#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
-#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
-#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
-#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
-#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
-
-#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
-#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
-#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
-
-/* Section 4: Extended PHY Registers */
-#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
-
-#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
-#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC 0U
-
-/* Includes ------------------------------------------------------------------*/
-/**
- * @brief Include module's header file
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-#include "stm32f1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-#include "stm32f1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-#include "stm32f1xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-#include "stm32f1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-#include "stm32f1xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-#include "stm32f1xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
- #include "Legacy/stm32f1xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-#include "stm32f1xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-#include "stm32f1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-#include "stm32f1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-#include "stm32f1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-#include "stm32f1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-#include "stm32f1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-#include "stm32f1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-#include "stm32f1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-#include "stm32f1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-#include "stm32f1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-#include "stm32f1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-#include "stm32f1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-#include "stm32f1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-#include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
-#include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-#include "stm32f1xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
-#include "stm32f1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-#include "stm32f1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
-#include "stm32f1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
-#include "stm32f1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
-#include "stm32f1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-#include "stm32f1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-#include "stm32f1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-#include "stm32f1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
-#include "stm32f1xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
-#include "stm32f1xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
-#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-void assert_failed(uint8_t* file, uint32_t line);
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CONF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NeoPixelF103MVP.ioc b/NeoPixelF103MVP.ioc
index 542489c..423ae29 100644
--- a/NeoPixelF103MVP.ioc
+++ b/NeoPixelF103MVP.ioc
@@ -1,129 +1,130 @@
#MicroXplorer Configuration settings - do not modify
-Mcu.Family=STM32F1
-RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
-ProjectManager.MainLocation=Src
-PC15-OSC32_OUT.Mode=LSE-External-Oscillator
-RCC.MCOFreq_Value=52000000
+Dma.Request0=SPI1_TX
+Dma.RequestsNb=1
+Dma.SPI1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI1_TX.0.Instance=DMA1_Channel3
+Dma.SPI1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_TX.0.MemInc=DMA_MINC_ENABLE
-ProjectManager.ProjectFileName=NeoPixelF103MVP.ioc
+Dma.SPI1_TX.0.Mode=DMA_NORMAL
+Dma.SPI1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_TX.0.PeriphInc=DMA_PINC_DISABLE
-PA7.Mode=TX_Only_Simplex_Unidirect_Master
-PD1-OSC_OUT.Mode=HSE-External-Oscillator
-ProjectManager.KeepUserCode=true
-Mcu.UserName=STM32F103C8Tx
-Mcu.PinsNb=10
-SPI1.VirtualType=VM_MASTER
-ProjectManager.NoMain=false
-SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
-RCC.PLLCLKFreq_Value=52000000
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_SPI1_Init-SPI1-false-HAL-true
-PC13-TAMPER-RTC.Signal=GPIO_Output
-RCC.ADCFreqValue=26000000
-ProjectManager.DefaultFWLocation=true
-PD0-OSC_IN.Signal=RCC_OSC_IN
-ProjectManager.DeletePrevious=true
-RCC.APB1CLKDivider=RCC_HCLK_DIV2
-PC14-OSC32_IN.Signal=RCC_OSC32_IN
-PinOutPanel.RotationAngle=0
-RCC.FamilyName=M
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-ProjectManager.StackSize=0x400
-PD1-OSC_OUT.Signal=RCC_OSC_OUT
-NVIC.DMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:false\:true
-PA13.Signal=SYS_JTMS-SWDIO
-Mcu.IP4=SYS
-RCC.FCLKCortexFreq_Value=52000000
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-Mcu.IP2=RCC
-Mcu.IP3=SPI1
+Dma.SPI1_TX.0.Priority=DMA_PRIORITY_HIGH
+Dma.SPI1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32F1
Mcu.IP0=DMA
Mcu.IP1=NVIC
-Dma.SPI1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
-Mcu.UserConstants=
-ProjectManager.TargetToolchain=STM32CubeIDE
-Mcu.ThirdPartyNb=0
-SPI1.Direction=SPI_DIRECTION_2LINES
-Dma.SPI1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
-RCC.HCLKFreq_Value=52000000
-Dma.SPI1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Mcu.IP2=RCC
+Mcu.IP3=SPI1
+Mcu.IP4=SYS
Mcu.IPNb=5
-ProjectManager.PreviousToolchain=STM32CubeIDE
-RCC.APB2TimFreq_Value=52000000
-SPI1.CalculateBaudRate=3.25 MBits/s
-Mcu.Pin6=PA7
-Mcu.Pin7=PA13
-ProjectManager.RegisterCallBack=
-PC13-TAMPER-RTC.Locked=true
-Mcu.Pin8=PA14
-RCC.USBFreq_Value=52000000
-Mcu.Pin9=VP_SYS_VS_Systick
-PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
-RCC.AHBFreq_Value=52000000
+Mcu.Name=STM32F103C(8-B)Tx
+Mcu.Package=LQFP48
Mcu.Pin0=PC13-TAMPER-RTC
Mcu.Pin1=PC14-OSC32_IN
Mcu.Pin2=PC15-OSC32_OUT
-PD0-OSC_IN.Mode=HSE-External-Oscillator
Mcu.Pin3=PD0-OSC_IN
Mcu.Pin4=PD1-OSC_OUT
Mcu.Pin5=PA5
-PA5.Signal=SPI1_SCK
-ProjectManager.ProjectBuild=false
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-board=custom
-NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
-ProjectManager.LastFirmware=true
-RCC.PLLMUL=RCC_PLL_MUL13
-RCC.VCOOutput2Freq_Value=4000000
-ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.3
-MxDb.Version=DB.6.0.0
-RCC.APB2Freq_Value=52000000
-ProjectManager.BackupPrevious=true
+Mcu.Pin6=PA7
+Mcu.Pin7=PA13
+Mcu.Pin8=PA14
+Mcu.Pin9=VP_SYS_VS_Systick
+Mcu.PinsNb=10
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F103C8Tx
MxCube.Version=6.0.1
-PC14-OSC32_IN.Mode=LSE-External-Oscillator
-SPI1.Mode=SPI_MODE_MASTER
-PA14.Mode=Serial_Wire
-File.Version=6
-VP_SYS_VS_Systick.Mode=SysTick
-Dma.SPI1_TX.0.Instance=DMA1_Channel3
+MxDb.Version=DB.6.0.0
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-PA13.Mode=Serial_Wire
-ProjectManager.FreePins=false
-RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSEDivPLL,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
-ProjectManager.AskForMigrate=true
-Mcu.Name=STM32F103C(8-B)Tx
-Dma.RequestsNb=1
-ProjectManager.HalAssertFull=false
-ProjectManager.ProjectName=NeoPixelF103MVP
-ProjectManager.UnderRoot=true
-RCC.PLLMCOFreq_Value=26000000
-ProjectManager.CoupleFile=true
-Dma.SPI1_TX.0.Mode=DMA_NORMAL
-RCC.SYSCLKFreq_VALUE=52000000
-Mcu.Package=LQFP48
-RCC.TimSysFreq_Value=52000000
-NVIC.ForceEnableDMAVector=true
-KeepUserPlacement=false
-RCC.HSEDivPLL=RCC_HSE_PREDIV_DIV2
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-ProjectManager.CompilerOptimize=6
-ProjectManager.ToolChainLocation=
-VP_SYS_VS_Systick.Signal=SYS_VS_Systick
-PA14.Signal=SYS_JTCK-SWCLK
-ProjectManager.HeapSize=0x200
-Dma.SPI1_TX.0.Priority=DMA_PRIORITY_HIGH
-Dma.SPI1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-ProjectManager.ComputerToolchain=false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-RCC.APB1TimFreq_Value=52000000
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-Dma.Request0=SPI1_TX
-RCC.APB1Freq_Value=26000000
-SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
-ProjectManager.CustomerFirmwarePackage=
-ProjectManager.DeviceId=STM32F103C8Tx
-ProjectManager.LibraryCopy=1
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
PA5.Mode=TX_Only_Simplex_Unidirect_Master
+PA5.Signal=SPI1_SCK
+PA7.Mode=TX_Only_Simplex_Unidirect_Master
PA7.Signal=SPI1_MOSI
+PC13-TAMPER-RTC.Locked=true
+PC13-TAMPER-RTC.Signal=GPIO_Output
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+PD0-OSC_IN.Mode=HSE-External-Oscillator
+PD0-OSC_IN.Signal=RCC_OSC_IN
+PD1-OSC_OUT.Mode=HSE-External-Oscillator
+PD1-OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=true
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=true
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F103C8Tx
+ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.3
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=STM32CubeIDE
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=NeoPixelF103MVP.ioc
+ProjectManager.ProjectName=NeoPixelF103MVP
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-LL-true,3-SystemClock_Config-RCC-false-LL-false,4-MX_SPI1_Init-SPI1-false-LL-true
+RCC.ADCFreqValue=26000000
+RCC.AHBFreq_Value=52000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV2
+RCC.APB1Freq_Value=26000000
+RCC.APB1TimFreq_Value=52000000
+RCC.APB2Freq_Value=52000000
+RCC.APB2TimFreq_Value=52000000
+RCC.FCLKCortexFreq_Value=52000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=52000000
+RCC.HSEDivPLL=RCC_HSE_PREDIV_DIV2
+RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSEDivPLL,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
+RCC.MCOFreq_Value=52000000
+RCC.PLLCLKFreq_Value=52000000
+RCC.PLLMCOFreq_Value=26000000
+RCC.PLLMUL=RCC_PLL_MUL13
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.SYSCLKFreq_VALUE=52000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TimSysFreq_Value=52000000
+RCC.USBFreq_Value=52000000
+RCC.VCOOutput2Freq_Value=4000000
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
+SPI1.CalculateBaudRate=3.25 MBits/s
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.VirtualType=VM_MASTER
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
+isbadioc=false
diff --git a/STM32F103C8TX_FLASH.ld b/STM32F103C8TX_FLASH.ld
index 5b74398..16057bc 100644
--- a/STM32F103C8TX_FLASH.ld
+++ b/STM32F103C8TX_FLASH.ld
@@ -30,8 +30,8 @@ ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
-_Min_Heap_Size = 0x200; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
/* Memories definition */
MEMORY
diff --git a/Src/dma.c b/Src/dma.c
index c62ffb7..48e8006 100644
--- a/Src/dma.c
+++ b/Src/dma.c
@@ -38,13 +38,14 @@
void MX_DMA_Init(void)
{
+ /* Init with LL driver */
/* DMA controller clock enable */
- __HAL_RCC_DMA1_CLK_ENABLE();
+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
/* DMA interrupt init */
/* DMA1_Channel3_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0);
- HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
+ NVIC_SetPriority(DMA1_Channel3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+ NVIC_EnableIRQ(DMA1_Channel3_IRQn);
}
diff --git a/Src/gpio.c b/Src/gpio.c
index 6024168..5ed24a3 100644
--- a/Src/gpio.c
+++ b/Src/gpio.c
@@ -40,22 +40,22 @@
void MX_GPIO_Init(void)
{
- GPIO_InitTypeDef GPIO_InitStruct = {0};
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
- __HAL_RCC_GPIOC_CLK_ENABLE();
- __HAL_RCC_GPIOD_CLK_ENABLE();
- __HAL_RCC_GPIOA_CLK_ENABLE();
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOC);
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOD);
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_RESET);
+ /**/
+ LL_GPIO_ResetOutputPin(GPIOC, LL_GPIO_PIN_13);
- /*Configure GPIO pin : PC13 */
- GPIO_InitStruct.Pin = GPIO_PIN_13;
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ /**/
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_13;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
}
diff --git a/Src/main.c b/Src/main.c
index 1064e3c..bf566a5 100644
--- a/Src/main.c
+++ b/Src/main.c
@@ -77,7 +77,17 @@ int main(void)
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- HAL_Init();
+
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+
+ NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* System interrupt init*/
+
+ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ */
+ LL_GPIO_AF_Remap_SWJ_NOJTAG();
/* USER CODE BEGIN Init */
@@ -115,36 +125,37 @@ int main(void)
*/
void SystemClock_Config(void)
{
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-
- /** Initializes the RCC Oscillators according to the specified parameters
- * in the RCC_OscInitTypeDef structure.
- */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL13;
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
+ while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_2)
{
- Error_Handler();
}
- /** Initializes the CPU, AHB and APB buses clocks
- */
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ LL_RCC_HSE_Enable();
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ /* Wait till HSE is ready */
+ while(LL_RCC_HSE_IsReady() != 1)
{
- Error_Handler();
+
}
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE_DIV_2, LL_RCC_PLL_MUL_13);
+ LL_RCC_PLL_Enable();
+
+ /* Wait till PLL is ready */
+ while(LL_RCC_PLL_IsReady() != 1)
+ {
+
+ }
+ LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
+ LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+
+ /* Wait till System clock is ready */
+ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+
+ }
+ LL_Init1msTick(52000000);
+ LL_SetSystemCoreClock(52000000);
}
/* USER CODE BEGIN 4 */
diff --git a/Src/spi.c b/Src/spi.c
index 93764eb..6930971 100644
--- a/Src/spi.c
+++ b/Src/spi.c
@@ -24,100 +24,56 @@
/* USER CODE END 0 */
-SPI_HandleTypeDef hspi1;
-DMA_HandleTypeDef hdma_spi1_tx;
-
/* SPI1 init function */
void MX_SPI1_Init(void)
{
+ LL_SPI_InitTypeDef SPI_InitStruct = {0};
- hspi1.Instance = SPI1;
- hspi1.Init.Mode = SPI_MODE_MASTER;
- hspi1.Init.Direction = SPI_DIRECTION_2LINES;
- hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
- hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
- hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
- hspi1.Init.NSS = SPI_NSS_SOFT;
- hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
- hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
- hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
- hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
- hspi1.Init.CRCPolynomial = 10;
- if (HAL_SPI_Init(&hspi1) != HAL_OK)
- {
- Error_Handler();
- }
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
-}
+ /* Peripheral clock enable */
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
-void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
-{
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
+ /**SPI1 GPIO Configuration
+ PA5 ------> SPI1_SCK
+ PA7 ------> SPI1_MOSI
+ */
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_7;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- if(spiHandle->Instance==SPI1)
- {
- /* USER CODE BEGIN SPI1_MspInit 0 */
+ /* SPI1 DMA Init */
- /* USER CODE END SPI1_MspInit 0 */
- /* SPI1 clock enable */
- __HAL_RCC_SPI1_CLK_ENABLE();
+ /* SPI1_TX Init */
+ LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
- __HAL_RCC_GPIOA_CLK_ENABLE();
- /**SPI1 GPIO Configuration
- PA5 ------> SPI1_SCK
- PA7 ------> SPI1_MOSI
- */
- GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PRIORITY_HIGH);
- /* SPI1 DMA Init */
- /* SPI1_TX Init */
- hdma_spi1_tx.Instance = DMA1_Channel3;
- hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
- hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
- hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
- hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- hdma_spi1_tx.Init.Mode = DMA_NORMAL;
- hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH;
- if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
- {
- Error_Handler();
- }
+ LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MODE_NORMAL);
- __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi1_tx);
+ LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PERIPH_NOINCREMENT);
- /* USER CODE BEGIN SPI1_MspInit 1 */
+ LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MEMORY_INCREMENT);
- /* USER CODE END SPI1_MspInit 1 */
- }
-}
+ LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PDATAALIGN_BYTE);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
-{
+ LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MDATAALIGN_BYTE);
- if(spiHandle->Instance==SPI1)
- {
- /* USER CODE BEGIN SPI1_MspDeInit 0 */
+ SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct.CRCPoly = 10;
+ LL_SPI_Init(SPI1, &SPI_InitStruct);
- /* USER CODE END SPI1_MspDeInit 0 */
- /* Peripheral clock disable */
- __HAL_RCC_SPI1_CLK_DISABLE();
-
- /**SPI1 GPIO Configuration
- PA5 ------> SPI1_SCK
- PA7 ------> SPI1_MOSI
- */
- HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_7);
-
- /* SPI1 DMA DeInit */
- HAL_DMA_DeInit(spiHandle->hdmatx);
- /* USER CODE BEGIN SPI1_MspDeInit 1 */
-
- /* USER CODE END SPI1_MspDeInit 1 */
- }
}
/* USER CODE BEGIN 1 */
diff --git a/Src/stm32f1xx_hal_msp.c b/Src/stm32f1xx_hal_msp.c
deleted file mode 100644
index 5b17adc..0000000
--- a/Src/stm32f1xx_hal_msp.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * File Name : stm32f1xx_hal_msp.c
- * Description : This file provides code for the MSP Initialization
- * and de-Initialization codes.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN Define */
-
-/* USER CODE END Define */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN Macro */
-
-/* USER CODE END Macro */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* External functions --------------------------------------------------------*/
-/* USER CODE BEGIN ExternalFunctions */
-
-/* USER CODE END ExternalFunctions */
-
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-/**
- * Initializes the Global MSP.
- */
-void HAL_MspInit(void)
-{
- /* USER CODE BEGIN MspInit 0 */
-
- /* USER CODE END MspInit 0 */
-
- __HAL_RCC_AFIO_CLK_ENABLE();
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* System interrupt init*/
-
- /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
- */
- __HAL_AFIO_REMAP_SWJ_NOJTAG();
-
- /* USER CODE BEGIN MspInit 1 */
-
- /* USER CODE END MspInit 1 */
-}
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f1xx_it.c b/Src/stm32f1xx_it.c
index 0b0473c..09e085c 100644
--- a/Src/stm32f1xx_it.c
+++ b/Src/stm32f1xx_it.c
@@ -23,6 +23,8 @@
#include "stm32f1xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
+#include "App/App.h"
+
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@@ -56,7 +58,7 @@
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
-extern DMA_HandleTypeDef hdma_spi1_tx;
+
/* USER CODE BEGIN EV */
/* USER CODE END EV */
@@ -182,9 +184,9 @@ void PendSV_Handler(void)
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
-
+ HandleSystick();
/* USER CODE END SysTick_IRQn 0 */
- HAL_IncTick();
+
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
@@ -203,9 +205,11 @@ void SysTick_Handler(void)
void DMA1_Channel3_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
+ /* SPI1 TX DMA interrupt */
+ HandleSpiDmaIrq();
/* USER CODE END DMA1_Channel3_IRQn 0 */
- HAL_DMA_IRQHandler(&hdma_spi1_tx);
+
/* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
/* USER CODE END DMA1_Channel3_IRQn 1 */