diff --git a/.cproject b/.cproject
index e0bef60..f0248b5 100644
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+++ b/.cproject
@@ -1,268 +1,261 @@
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diff --git a/.mxproject b/.mxproject
index 526776d..ce3dcb2 100644
--- a/.mxproject
+++ b/.mxproject
@@ -8,7 +8,7 @@ SourceFiles=gpio.c;stm32f1xx_it.c;main.c;
LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
[PreviousUsedSW4STM32Files]
-SourceFiles=../Src/main.c;../Src/gpio.c;../Src/stm32f1xx_it.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c;..//Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null;
+SourceFiles=../Src/main.c;../Src/gpio.c;../Src/stm32f1xx_it.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c;..//Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;/home/abody/work/private/NeoPixelF103MVP//startup/startup_stm32f103xb.s;
HeaderPath=../Drivers/STM32F1xx_HAL_Driver/Inc;../Drivers/CMSIS/Device/ST/STM32F1xx/Include;../Drivers/CMSIS/Include;../Inc;
CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;HSI_VALUE:8000000;LSI_VALUE:40000;VDD_VALUE:3300;PREFETCH_ENABLE:1;__weak:"__attribute__((weak))";__packed:"__attribute__((__packed__))";
diff --git a/Inc/bitband.h b/Inc/bitband.h
new file mode 100644
index 0000000..4d3221d
--- /dev/null
+++ b/Inc/bitband.h
@@ -0,0 +1,27 @@
+/*
+ * bitband.h
+ *
+ * Created on: Dec 14, 2018
+ * Author: abody
+ */
+
+#ifndef BITBAND_H_
+#define BITBAND_H_
+
+#include
+
+#define RAM_BASE 0x20000000
+#define RAM_BB_BASE 0x22000000
+#define RAM_ResetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 0)
+#define RAM_SetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 1)
+#define RAM_GetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)))
+#define BITBAND_RAM(address, bit) ( (__IO uint32_t *) (RAM_BB_BASE + (((uint32_t)address) - RAM_BASE) * 32 + (bit) * 4))
+
+#define IO_BASE 0x20000000
+#define IO_BB_BASE 0x22000000
+#define IO_ResetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (IO_BB_BASE | ((VarAddr - IO_BASE) << 5) | ((BitNumber) << 2)) = 0)
+#define IO_SetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (IO_BB_BASE | ((VarAddr - IO_BASE) << 5) | ((BitNumber) << 2)) = 1)
+#define IO_GetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (IO_BB_BASE | ((VarAddr - IO_BASE) << 5) | ((BitNumber) << 2)))
+#define BITBAND_IO(address, bit) ( (__IO uint32_t *) (IO_BB_BASE + (((uint32_t)address) - IO_BASE) * 32 + (bit) * 4))
+
+#endif /* BITBAND_H_ */
diff --git a/NeoPixelF103MVP Debug.cfg b/NeoPixelF103MVP Debug.cfg
new file mode 100644
index 0000000..d815a00
--- /dev/null
+++ b/NeoPixelF103MVP Debug.cfg
@@ -0,0 +1,28 @@
+# This is an NeoPixelF103MVP board with a single STM32F103C8Tx chip
+#
+# Generated by System Workbench for STM32
+# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
+
+source [find interface/stlink.cfg]
+
+set WORKAREASIZE 0x5000
+
+transport select "hla_swd"
+
+set CHIPNAME STM32F103C8Tx
+set BOARDNAME NeoPixelF103MVP
+
+# Enable debug when in low power modes
+set ENABLE_LOW_POWER 1
+
+# Stop Watchdog counters when halt
+set STOP_WATCHDOG 1
+
+# STlink Debug clock frequency
+set CLOCK_FREQ 4000
+
+# use software system reset
+reset_config none
+set CONNECT_UNDER_RESET 0
+
+source [find target/stm32f1x.cfg]
diff --git a/NeoPixelF103MVP.ioc b/NeoPixelF103MVP.ioc
index eea342f..2bad45f 100644
--- a/NeoPixelF103MVP.ioc
+++ b/NeoPixelF103MVP.ioc
@@ -85,13 +85,27 @@ ProjectManager.TargetToolchain=SW4STM32
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false
-RCC.APB1Freq_Value=8000000
-RCC.APB2Freq_Value=8000000
+RCC.ADCFreqValue=36000000
+RCC.AHBFreq_Value=72000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV2
+RCC.APB1Freq_Value=36000000
+RCC.APB1TimFreq_Value=72000000
+RCC.APB2Freq_Value=72000000
+RCC.APB2TimFreq_Value=72000000
+RCC.FCLKCortexFreq_Value=72000000
RCC.FamilyName=M
-RCC.IPParameters=APB1Freq_Value,APB2Freq_Value,FamilyName,PLLCLKFreq_Value,PLLMCOFreq_Value,TimSysFreq_Value
-RCC.PLLCLKFreq_Value=8000000
-RCC.PLLMCOFreq_Value=4000000
-RCC.TimSysFreq_Value=8000000
+RCC.HCLKFreq_Value=72000000
+RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
+RCC.MCOFreq_Value=72000000
+RCC.PLLCLKFreq_Value=72000000
+RCC.PLLMCOFreq_Value=36000000
+RCC.PLLMUL=RCC_PLL_MUL9
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.SYSCLKFreq_VALUE=72000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TimSysFreq_Value=72000000
+RCC.USBFreq_Value=72000000
+RCC.VCOOutput2Freq_Value=8000000
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
diff --git a/Src/main.c b/Src/main.c
index 4ffb873..c8f275c 100644
--- a/Src/main.c
+++ b/Src/main.c
@@ -41,7 +41,7 @@
#include "gpio.h"
/* USER CODE BEGIN Includes */
-
+#include "bitband.h"
/* USER CODE END Includes */
/* Private variables ---------------------------------------------------------*/
@@ -99,17 +99,42 @@ int main(void)
/* Infinite loop */
/* USER CODE BEGIN WHILE */
- while (1)
+ GPIOB->ODR = 0;
+ volatile uint32_t v;
+ uint8_t ledbytes[] = {0x0f, 0xf0, 0};
+
+ __disable_irq();
+
+ while(1)
{
+ uint32_t *bitPtr = BITBAND_RAM(ledbytes, 0);
+ uint32_t cnt = sizeof(ledbytes)*8 + 1;
+
+ while(--cnt) {
+
+ if(*bitPtr++) {
+ GPIOB->BSRR = 1 << 11; //set
+ for( v=5; v != 0; --v); //long
+ GPIOB->BSRR = 1 << (16+11); //clear
+ ++v; ++v; //short
+ } else {
+ GPIOB->BSRR = 1 << 11; //set
+ for( v=0; v != 0; --v); //short
+ ++v;++v;
+ GPIOB->BSRR = 1 << (16+11); //clear
+ for( v=3; v != 0; --v); //long
+ ++v; ++v;
+ }
+ }
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
-
+ for( v=400; v != 0; --v); //long
}
/* USER CODE END 3 */
-
}
+
static void LL_Init(void)
{
@@ -148,39 +173,46 @@ static void LL_Init(void)
void SystemClock_Config(void)
{
- LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
+ LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
- if(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0)
+ if(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_2)
{
Error_Handler();
}
- LL_RCC_HSI_SetCalibTrimming(16);
+ LL_RCC_HSE_Enable();
- LL_RCC_HSI_Enable();
+ /* Wait till HSE is ready */
+ while(LL_RCC_HSE_IsReady() != 1)
+ {
+
+ }
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE_DIV_1, LL_RCC_PLL_MUL_9);
- /* Wait till HSI is ready */
- while(LL_RCC_HSI_IsReady() != 1)
+ LL_RCC_PLL_Enable();
+
+ /* Wait till PLL is ready */
+ while(LL_RCC_PLL_IsReady() != 1)
{
}
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
- LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
/* Wait till System clock is ready */
- while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{
}
- LL_Init1msTick(8000000);
+ LL_Init1msTick(72000000);
LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);
- LL_SetSystemCoreClock(8000000);
+ LL_SetSystemCoreClock(72000000);
/* SysTick_IRQn interrupt configuration */
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));