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This commit is contained in:
Attila Body 2019-11-15 20:45:11 +01:00
parent ef3698135e
commit c34b20ad8c
2 changed files with 22 additions and 11 deletions
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2
src/packetusart.cpp
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@ -19,6 +19,8 @@ PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream
: UsartCore(usart, dma, streamRx, streamTx)
{
CrcHandler::Instance().AttachSlot(m_crcSlot);
LL_USART_EnableIT_IDLE(usart);
LL_USART_EnableIT_ERROR(usart);
}

23
src/usartcore.cpp
View file

@ -14,28 +14,37 @@ UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx,
, m_rxDma(dma, streamRx)
, m_txDma(dma, streamTx)
{
uint32_t status = usart->SR;
volatile uint32_t tmpreg = usart->DR; // clearing some of the error/status bits in the USART
(void) tmpreg;
(void) status;
*m_txDma.GetIfcReg() =
m_txDma.GetTcMask() | m_rxDma.GetHtMask() | m_txDma.GetTeMask() | m_rxDma.GetFeMask() | m_rxDma.GetDmeMask();
*m_rxDma.GetIfcReg() =
m_rxDma.GetTcMask() | m_rxDma.GetHtMask() | m_rxDma.GetTeMask() | m_rxDma.GetFeMask() | m_rxDma.GetDmeMask();
LL_DMA_EnableIT_TC(dma, streamRx);
LL_DMA_EnableIT_TE(dma, streamRx);
LL_DMA_EnableIT_TC(dma, streamTx);
LL_DMA_EnableIT_TE(dma, streamTx);
LL_USART_EnableIT_IDLE(usart);
LL_USART_EnableIT_ERROR(usart);
}
void UsartCore::UsartIsr()
{
if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
LL_USART_DisableIT_TC(m_usart);
TransmissionComplete();
} else if(LL_USART_IsEnabledIT_ERROR(m_usart)) {
uint32_t status = m_usart->SR;
volatile uint32_t tmpreg = m_usart->DR; // clearing some of the error/status bits in the HW
(void) tmpreg;
if(status & USART_SR_IDLE) {
if(LL_USART_IsEnabledIT_TC(m_usart) && LL_USART_IsActiveFlag_TC(m_usart)) { // transmission complete
LL_USART_DisableIT_TC(m_usart);
TransmissionComplete();
}
if(LL_USART_IsEnabledIT_IDLE(m_usart) && (status & USART_SR_IDLE)) {
ReceiverIdle();
}
if(LL_USART_IsEnabledIT_ERROR(m_usart)) {
if(status & USART_SR_FE) {
FramingError();
}