removing prefix LL_ from class/struct names under f4ll namespace
This commit is contained in:
parent
366d0f991d
commit
a2cb50a1af
13 changed files with 147 additions and 146 deletions
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@ -8,15 +8,15 @@
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#ifndef LL_CONSOLEHANDLER_H_
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#define LL_CONSOLEHANDLER_H_
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#include "f4ll/ll_hsusart.h"
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#include "f4ll/hsusart.h"
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#include "singleton.h"
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namespace f4ll {
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class LL_ConsoleHandler: public LL_UsartCore, public Singleton<LL_ConsoleHandler>
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class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
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{
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friend class Singleton<LL_ConsoleHandler>;
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friend class Singleton<ConsoleHandler>;
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public:
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// LL_UsartCore pure virtual function implementations
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@ -24,15 +24,15 @@ public:
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virtual void TransmissionComplete(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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void PrintStats(uint8_t id, LL_HsUsart &usart);
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void PrintStats(uint8_t id, HsUsart &usart);
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private:
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LL_ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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char m_buffer[128];
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uint16_t m_used = 0;
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@ -9,16 +9,16 @@
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#define LL_CRCHANDLER_H_
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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#include "f4ll/ll_dmahelper.h"
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#include "f4ll/dmahelper.h"
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#include "singleton.h"
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extern "C" void _HandleCrcDmaIrq(void);
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namespace f4ll {
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class LL_CrcHandler : public Singleton<LL_CrcHandler>
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class CrcHandler : public Singleton<CrcHandler>
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{
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friend class Singleton<LL_CrcHandler>;
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friend class Singleton<CrcHandler>;
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public:
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struct ICallback
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@ -29,12 +29,12 @@ public:
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class SlotBase
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{
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friend class LL_CrcHandler;
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friend class CrcHandler;
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public:
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struct CrcTask {
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void const * volatile m_address; // changed to nullptr when execution starts
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uint16_t volatile m_wordCount;
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LL_CrcHandler::ICallback *m_callback;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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};
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@ -71,13 +71,13 @@ public:
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void DmaTransferCompleted(void);
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private:
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LL_CrcHandler(DMA_TypeDef *dma, uint32_t stream);
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CrcHandler(DMA_TypeDef *dma, uint32_t stream);
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friend void ::_HandleCrcDmaIrq(void);
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void StartNextTask(void);
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void WaitResults(SlotBase &slot, uint8_t task) const;
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LL_DmaHelper m_dma;
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DmaHelper m_dma;
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SlotBase * volatile m_firstSlot = nullptr;
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SlotBase * volatile m_activeSlot = nullptr;
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int volatile m_activeTask;
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@ -13,10 +13,10 @@
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namespace f4ll {
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class LL_DmaHelper {
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class DmaHelper {
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public:
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LL_DmaHelper(DMA_TypeDef *dma, uint32_t stream);
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LL_DmaHelper(LL_DmaHelper const &base) = default;
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DmaHelper(DMA_TypeDef *dma, uint32_t stream);
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DmaHelper(DmaHelper const &base) = default;
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inline DMA_TypeDef* GetDma() const { return m_dma; }
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inline uint32_t GetStream() const { return m_stream; }
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@ -8,17 +8,17 @@
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#ifndef LL_HSUSART_H_
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#define LL_HSUSART_H_
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#include <platform/usart_ll.h>
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#include "f4ll/ll_usartcore.h"
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#include "f4ll/ll_crchandler.h"
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#include "f4ll/usartcore.h"
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#include "f4ll/crchandler.h"
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namespace f4ll {
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struct DMAINFO;
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class LL_HsUsart : public LL_CrcHandler::ICallback, public LL_UsartCore
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class HsUsart : public CrcHandler::ICallback, public UsartCore
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{
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public:
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LL_HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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struct PacketHeader { // !!! size should be multiple of 4 !!!
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uint8_t startByte;
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@ -48,22 +48,22 @@ public:
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};
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struct IHsUsartCallback {
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virtual bool PacketReceived(LL_HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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virtual bool PacketReceived(HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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};
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// LL_CRCHandler::ICallback interface functions
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// CRCHandler::ICallback interface functions
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
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// LL_UsartCore pure virtual function implementations
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// UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
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void SetupReceive(void);
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@ -100,7 +100,7 @@ private:
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Stats m_stats;
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bool m_rxBufferSelector = false;
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LL_CrcHandler::Slot<2> m_crcSlot;
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CrcHandler::Slot<2> m_crcSlot;
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IHsUsartCallback *m_userCallback = nullptr;
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uintptr_t m_userCallbackParam = 0;
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Buffer m_txBuffer;
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@ -7,19 +7,19 @@
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#ifndef LL_MEMCPY_DMA_H_
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#define LL_MEMCPY_DMA_H_
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#include "f4ll/ll_dmahelper.h"
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#include "f4ll/dmahelper.h"
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#include "singleton.h"
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namespace f4ll {
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class LL_MemcpyDma : public Singleton<LL_MemcpyDma>, private LL_DmaHelper
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class MemcpyDma : public Singleton<MemcpyDma>, private DmaHelper
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{
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friend class Singleton<LL_MemcpyDma>;
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friend class Singleton<MemcpyDma>;
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public:
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void* Copy(void *dst, void const *src, uint16_t length);
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void DmaTransferCompleted();
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private:
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LL_MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
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MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
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bool volatile m_busy = false;
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};
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@ -9,30 +9,30 @@
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#define LL_USARTCORE_H_
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#include <platform/usart_ll.h>
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#include "f4ll/ll_dmahelper.h"
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#include "f4ll/dmahelper.h"
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namespace f4ll {
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class LL_UsartCore
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class UsartCore
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{
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public:
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static inline void HandleUsartIrq(LL_UsartCore *_this) { _this->UsartIsr(); }
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static inline void HandleRxDmaIrq(LL_UsartCore *_this) { _this->RxDmaIsr(); }
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static inline void HandleTxDmaIrq(LL_UsartCore *_this) { _this->TxDmaIsr(); }
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static inline void HandleUsartIrq(UsartCore *_this) { _this->UsartIsr(); }
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static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
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static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
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protected:
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LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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virtual void ReceiverIdle() = 0;
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virtual void TransmissionComplete() = 0;
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virtual void RxDmaTransferComplete() = 0;
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virtual void RxDmaHalfTransfer() = 0;
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virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason) = 0;
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virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
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virtual void TxDmaTransferComplete() = 0;
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virtual void TxDmaHalfTransfer() = 0;
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virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason) = 0;
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virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
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void SetupTransmit(void const *buffer, uint16_t length);
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void SetupReceive(void *buffer, uint16_t length);
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void TxDmaIsr();
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USART_TypeDef *m_usart;
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LL_DmaHelper m_rxDma;
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LL_DmaHelper m_txDma;
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DmaHelper m_rxDma;
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DmaHelper m_txDma;
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};
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} /* namespace f4ll */
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@ -5,39 +5,39 @@
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* Author: abody
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*/
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#include "f4ll/ll_consolehandler.h"
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#include "f4ll/consolehandler.h"
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#include <f4ll_c/strutil.h>
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namespace f4ll {
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LL_ConsoleHandler::LL_ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
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: LL_UsartCore(usart, dma, streamRx, streamTx)
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ConsoleHandler::ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
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: UsartCore(usart, dma, streamRx, streamTx)
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{
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}
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void LL_ConsoleHandler::ReceiverIdle(void) {}
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void LL_ConsoleHandler::TransmissionComplete(void) {}
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void LL_ConsoleHandler::RxDmaTransferComplete(void) {}
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void LL_ConsoleHandler::RxDmaHalfTransfer(void) {}
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void LL_ConsoleHandler::RxDmaError(LL_DmaHelper::DmaErrorType reason) {}
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void LL_ConsoleHandler::TxDmaTransferComplete(void)
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void ConsoleHandler::ReceiverIdle(void) {}
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void ConsoleHandler::TransmissionComplete(void) {}
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void ConsoleHandler::RxDmaTransferComplete(void) {}
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void ConsoleHandler::RxDmaHalfTransfer(void) {}
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void ConsoleHandler::RxDmaError(DmaHelper::DmaErrorType reason) {}
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void ConsoleHandler::TxDmaTransferComplete(void)
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{
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LL_USART_EnableIT_TC(m_usart);
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LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
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}
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void LL_ConsoleHandler::TxDmaHalfTransfer(void) {}
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void LL_ConsoleHandler::TxDmaError(LL_DmaHelper::DmaErrorType reason) {}
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void ConsoleHandler::TxDmaHalfTransfer(void) {}
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void ConsoleHandler::TxDmaError(DmaHelper::DmaErrorType reason) {}
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#define ADDINFO(b,s,u) \
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b += strcpy_ex(b,s); \
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b += uitodec(b,u);
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void LL_ConsoleHandler::PrintStats(uint8_t id, LL_HsUsart &usart)
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void ConsoleHandler::PrintStats(uint8_t id, HsUsart &usart)
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{
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char ids[] = " : ";
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char *buffer = m_buffer;
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LL_HsUsart::Stats const &stats(usart.GetStats());
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HsUsart::Stats const &stats(usart.GetStats());
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ids[0] = id + '0';
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buffer += strcpy_ex(buffer, ids);
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@ -4,11 +4,11 @@
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* Created on: Oct 26, 2019
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* Author: compi
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*/
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#include "f4ll/ll_crchandler.h"
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#include "f4ll/crchandler.h"
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namespace f4ll {
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LL_CrcHandler::LL_CrcHandler(DMA_TypeDef *dma, uint32_t stream)
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CrcHandler::CrcHandler(DMA_TypeDef *dma, uint32_t stream)
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: m_dma(dma, stream)
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{
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LL_DMA_EnableIT_TC(dma, stream);
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}
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void LL_CrcHandler::AttachSlot(SlotBase &slot)
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void CrcHandler::AttachSlot(SlotBase &slot)
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{
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for(unsigned int i = 0; i < slot.m_taskCount; ++i ) {
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auto &task(slot[i]);
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}
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bool LL_CrcHandler::Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam)
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bool CrcHandler::Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam)
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{
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uint32_t prim = __get_PRIMASK();
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bool immediate;
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return immediate;
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}
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bool LL_CrcHandler::IsActive(SlotBase &slot, uint8_t task) const
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bool CrcHandler::IsActive(SlotBase &slot, uint8_t task) const
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{
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return task < slot.m_taskCount && slot[task].m_wordCount != 0;
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}
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bool LL_CrcHandler::IsQueued(SlotBase &slot, uint8_t task) const
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bool CrcHandler::IsQueued(SlotBase &slot, uint8_t task) const
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{
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return task < slot.m_taskCount && slot[task].m_address != nullptr;
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}
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bool LL_CrcHandler::IsRunning(SlotBase &slot, uint8_t task) const
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bool CrcHandler::IsRunning(SlotBase &slot, uint8_t task) const
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{
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return task < slot.m_taskCount && slot[task].m_wordCount && ! slot[task].m_address;
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}
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void LL_CrcHandler::DmaTransferCompleted(void)
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void CrcHandler::DmaTransferCompleted(void)
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{
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if(* m_dma.GetIsReg() & m_dma.GetTcMask()) { // DMA transfer complete
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* m_dma.GetIfcReg() = m_dma.GetTcMask();
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}
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void LL_CrcHandler::StartNextTask(void)
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void CrcHandler::StartNextTask(void)
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{
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bool stillMore;
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int index = 0;
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bool moreTasks;
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uint8_t index = 0;
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do {
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SlotBase *slot = m_firstSlot;
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stillMore = false;
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moreTasks = false;
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while(slot) {
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if(index < slot->m_taskCount) {
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if((*slot)[index].m_address) {
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return;
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}
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if(index + 1 < slot->m_taskCount)
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stillMore = true;
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moreTasks = true;
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}
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slot = slot->m_next;
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}
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++index;
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} while(stillMore);
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} while(moreTasks);
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m_activeSlot = nullptr;
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}
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void LL_CrcHandler::WaitResults(SlotBase &slot, uint8_t task) const
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void CrcHandler::WaitResults(SlotBase &slot, uint8_t task) const
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{
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while(IsQueued(slot, task));
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while(IsActive(slot, task));
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}
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uint32_t LL_CrcHandler::Compute(
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uint32_t CrcHandler::Compute(
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SlotBase &slot, uint8_t task, void const *address, uint16_t len)
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{
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uint32_t result;
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26
src/dmahelper.cpp
Normal file
26
src/dmahelper.cpp
Normal file
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/*
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q * ll_dmahelper.cpp
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*
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* Created on: Oct 25, 2019
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* Author: abody
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*/
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#include "f4ll/dmahelper.h"
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namespace f4ll {
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const uint32_t DmaHelper::m_FEMasks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
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const uint32_t DmaHelper::m_DMEMasks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
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const uint32_t DmaHelper::m_TEMasks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
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const uint32_t DmaHelper::m_HTMasks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
|
||||
const uint32_t DmaHelper::m_TCMasks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
|
||||
|
||||
DmaHelper::DmaHelper(DMA_TypeDef *dma, uint32_t stream)
|
||||
: m_dma(dma)
|
||||
, m_stream(stream)
|
||||
, m_isReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR))
|
||||
, m_ifcReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR))
|
||||
{
|
||||
}
|
||||
|
||||
} /* namespace f4ll */
|
|
@ -5,7 +5,7 @@
|
|||
* Author: abody
|
||||
*/
|
||||
#include <string.h>
|
||||
#include "f4ll/ll_hsusart.h"
|
||||
#include "f4ll/hsusart.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
|
@ -15,68 +15,68 @@ template<typename T> static inline T RoundUpTo4(T input)
|
|||
}
|
||||
|
||||
|
||||
LL_HsUsart::LL_HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
: LL_UsartCore(usart, dma, streamRx, streamTx)
|
||||
HsUsart::HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
: UsartCore(usart, dma, streamRx, streamTx)
|
||||
{
|
||||
LL_CrcHandler::Instance().AttachSlot(m_crcSlot);
|
||||
CrcHandler::Instance().AttachSlot(m_crcSlot);
|
||||
}
|
||||
|
||||
|
||||
uint8_t *LL_HsUsart::GetTxPacketBuffer(void)
|
||||
uint8_t* HsUsart::GetTxPacketBuffer(void)
|
||||
{
|
||||
return m_txBuffer.packet.payload;
|
||||
}
|
||||
|
||||
|
||||
USART_TypeDef* LL_HsUsart::GetUsart(void)
|
||||
USART_TypeDef* HsUsart::GetUsart(void)
|
||||
{
|
||||
return m_usart;
|
||||
}
|
||||
|
||||
|
||||
LL_HsUsart::Stats const & LL_HsUsart::GetStats(void)
|
||||
HsUsart::Stats const & HsUsart::GetStats(void)
|
||||
{
|
||||
return m_stats;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::IsTxBusy()
|
||||
bool HsUsart::IsTxBusy()
|
||||
{
|
||||
return m_txBuffer.busy;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::IsTxFailed()
|
||||
bool HsUsart::IsTxFailed()
|
||||
{
|
||||
return m_txBuffer.error;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::IsRxBusy(bool second)
|
||||
bool HsUsart::IsRxBusy(bool second)
|
||||
{
|
||||
return m_rxBuffers[second].busy;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::IsRxFailed(bool second)
|
||||
bool HsUsart::IsRxFailed(bool second)
|
||||
{
|
||||
return m_rxBuffers[second].error;
|
||||
|
||||
}
|
||||
|
||||
void LL_HsUsart::RxProcessed(bool second)
|
||||
void HsUsart::RxProcessed(bool second)
|
||||
{
|
||||
m_rxBuffers[second].busy = false;
|
||||
m_rxBuffers[second].error = false;
|
||||
}
|
||||
|
||||
void LL_HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
|
||||
void HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
|
||||
{
|
||||
m_userCallback = callback;
|
||||
m_userCallbackParam = callbackParam;
|
||||
}
|
||||
|
||||
void LL_HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
|
||||
void HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
|
||||
{
|
||||
uint8_t hash = STARTMARKER;
|
||||
|
||||
|
@ -89,13 +89,13 @@ void LL_HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
|
|||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::CheckHeader(PacketHeader &header)
|
||||
bool HsUsart::CheckHeader(PacketHeader &header)
|
||||
{
|
||||
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
|
||||
void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
|
||||
{
|
||||
uint16_t payloadLength = RoundUpTo4((uint16_t)length);
|
||||
|
||||
|
@ -106,10 +106,10 @@ void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFor
|
|||
m_txBuffer.busy = true;
|
||||
m_txBuffer.error = false;
|
||||
|
||||
LL_CrcHandler::Instance().Enqueue(m_crcSlot, 0, &m_txBuffer.packet, sizeof(PacketHeader) + payloadLength,
|
||||
CrcHandler::Instance().Enqueue(m_crcSlot, 0, &m_txBuffer.packet, sizeof(PacketHeader) + payloadLength,
|
||||
nullptr, reinterpret_cast<uintptr_t>(m_txBuffer.packet.payload + payloadLength));
|
||||
|
||||
while(waitForCrcQueue && LL_CrcHandler::Instance().IsQueued(m_crcSlot, 0));
|
||||
while(waitForCrcQueue && CrcHandler::Instance().IsQueued(m_crcSlot, 0));
|
||||
|
||||
SetupTransmit(&m_txBuffer.packet, m_txBuffer.requestedLength);
|
||||
|
||||
|
@ -117,14 +117,14 @@ void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFor
|
|||
}
|
||||
|
||||
|
||||
void LL_HsUsart::SetupReceive()
|
||||
void HsUsart::SetupReceive()
|
||||
{
|
||||
m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
|
||||
LL_UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
|
||||
UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::ReceiverIdle(void)
|
||||
void HsUsart::ReceiverIdle(void)
|
||||
{
|
||||
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
if(rcvdLen >= sizeof(PacketHeader)) {
|
||||
|
@ -144,7 +144,7 @@ void LL_HsUsart::ReceiverIdle(void)
|
|||
}
|
||||
|
||||
|
||||
void LL_HsUsart::TransmissionComplete(void)
|
||||
void HsUsart::TransmissionComplete(void)
|
||||
{
|
||||
LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(m_usart);
|
||||
|
@ -152,10 +152,10 @@ void LL_HsUsart::TransmissionComplete(void)
|
|||
}
|
||||
|
||||
|
||||
void LL_HsUsart::RxDmaTransferComplete(void)
|
||||
void HsUsart::RxDmaTransferComplete(void)
|
||||
{
|
||||
if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
|
||||
LL_CrcHandler::Instance().Enqueue(m_crcSlot, 1,
|
||||
CrcHandler::Instance().Enqueue(m_crcSlot, 1,
|
||||
&m_rxBuffers[m_rxBufferSelector].packet,
|
||||
sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength),
|
||||
this, m_rxBufferSelector);
|
||||
|
@ -166,38 +166,38 @@ void LL_HsUsart::RxDmaTransferComplete(void)
|
|||
SwitchRxBuffers();
|
||||
}
|
||||
|
||||
void LL_HsUsart::RxDmaHalfTransfer(void)
|
||||
void HsUsart::RxDmaHalfTransfer(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::RxDmaError(LL_DmaHelper::DmaErrorType reason)
|
||||
void HsUsart::RxDmaError(DmaHelper::DmaErrorType reason)
|
||||
{
|
||||
m_rxBuffers[m_rxBufferSelector].error = 1;
|
||||
++m_stats.rxDmaError;
|
||||
SwitchRxBuffers();
|
||||
}
|
||||
|
||||
void LL_HsUsart::TxDmaTransferComplete(void)
|
||||
void HsUsart::TxDmaTransferComplete(void)
|
||||
{
|
||||
LL_USART_EnableIT_TC(m_usart);
|
||||
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::TxDmaHalfTransfer(void)
|
||||
void HsUsart::TxDmaHalfTransfer(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::TxDmaError(LL_DmaHelper::DmaErrorType reason)
|
||||
void HsUsart::TxDmaError(DmaHelper::DmaErrorType reason)
|
||||
{
|
||||
m_txBuffer.error = 1;
|
||||
++m_stats.txDmaError;
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::SwitchRxBuffers(void)
|
||||
void HsUsart::SwitchRxBuffers(void)
|
||||
{
|
||||
++m_stats.rcvd;
|
||||
m_rxBufferSelector = !m_rxBufferSelector;
|
||||
|
@ -208,7 +208,7 @@ void LL_HsUsart::SwitchRxBuffers(void)
|
|||
}
|
||||
|
||||
|
||||
void LL_HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
{
|
||||
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
|
||||
|
||||
|
@ -223,7 +223,7 @@ void LL_HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t tas
|
|||
}
|
||||
|
||||
|
||||
void LL_HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
void HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
{
|
||||
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
|
||||
buf.busy = buf.error = true;
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
q * ll_dmahelper.cpp
|
||||
*
|
||||
* Created on: Oct 25, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#include "f4ll/ll_dmahelper.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
const uint32_t LL_DmaHelper::m_FEMasks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
|
||||
const uint32_t LL_DmaHelper::m_DMEMasks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
|
||||
const uint32_t LL_DmaHelper::m_TEMasks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
|
||||
const uint32_t LL_DmaHelper::m_HTMasks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
|
||||
const uint32_t LL_DmaHelper::m_TCMasks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
|
||||
|
||||
LL_DmaHelper::LL_DmaHelper(DMA_TypeDef *dma, uint32_t stream)
|
||||
: m_dma(dma)
|
||||
, m_stream(stream)
|
||||
, m_isReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR))
|
||||
, m_ifcReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR))
|
||||
{
|
||||
}
|
||||
|
||||
} /* namespace f4ll */
|
|
@ -5,17 +5,17 @@
|
|||
* Author: abody
|
||||
*/
|
||||
|
||||
#include "f4ll/ll_memcpydma.h"
|
||||
#include "f4ll/memcpydma.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
LL_MemcpyDma::LL_MemcpyDma(DMA_TypeDef *dma, uint32_t stream)
|
||||
: LL_DmaHelper(dma, stream)
|
||||
MemcpyDma::MemcpyDma(DMA_TypeDef *dma, uint32_t stream)
|
||||
: DmaHelper(dma, stream)
|
||||
{
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
}
|
||||
|
||||
void* LL_MemcpyDma::Copy(void *dst, void const *src, uint16_t length)
|
||||
void* MemcpyDma::Copy(void *dst, void const *src, uint16_t length)
|
||||
{
|
||||
LL_DMA_SetM2MSrcAddress(GetDma(), GetStream(), (uint32_t)src);
|
||||
LL_DMA_SetM2MDstAddress(GetDma(), GetStream(), (uint32_t)dst);
|
||||
|
@ -26,7 +26,7 @@ void* LL_MemcpyDma::Copy(void *dst, void const *src, uint16_t length)
|
|||
return dst;
|
||||
}
|
||||
|
||||
void LL_MemcpyDma::DmaTransferCompleted()
|
||||
void MemcpyDma::DmaTransferCompleted()
|
||||
{
|
||||
if(*GetIsReg() & GetTcMask()) { // DMA transfer complete
|
||||
*GetIfcReg() = GetTcMask();
|
|
@ -5,11 +5,11 @@
|
|||
* Author: abody
|
||||
*/
|
||||
|
||||
#include "f4ll/ll_usartcore.h"
|
||||
#include "f4ll/usartcore.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
LL_UsartCore::LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
: m_usart(usart)
|
||||
, m_rxDma(dma, streamRx)
|
||||
, m_txDma(dma, streamTx)
|
||||
|
@ -21,7 +21,7 @@ LL_UsartCore::LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stre
|
|||
LL_USART_EnableIT_IDLE(usart);
|
||||
}
|
||||
|
||||
void LL_UsartCore::UsartIsr()
|
||||
void UsartCore::UsartIsr()
|
||||
{
|
||||
if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(m_usart);
|
||||
|
@ -33,7 +33,7 @@ void LL_UsartCore::UsartIsr()
|
|||
}
|
||||
|
||||
|
||||
void LL_UsartCore::RxDmaIsr()
|
||||
void UsartCore::RxDmaIsr()
|
||||
{
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
|
||||
|
@ -48,22 +48,22 @@ void LL_UsartCore::RxDmaIsr()
|
|||
if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
|
||||
if(m_rxDma.IsEnabledIt_TE())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::Transfer);
|
||||
RxDmaError(DmaHelper::DmaErrorType::Transfer);
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetFeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetFeMask();
|
||||
if(m_rxDma.IsEnabledIt_FE())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::Fifo);
|
||||
RxDmaError(DmaHelper::DmaErrorType::Fifo);
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetDmeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetDmeMask();
|
||||
if(m_rxDma.IsEnabledIt_DME())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::DirectMode);
|
||||
RxDmaError(DmaHelper::DmaErrorType::DirectMode);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::TxDmaIsr()
|
||||
void UsartCore::TxDmaIsr()
|
||||
{
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
|
||||
|
@ -78,22 +78,22 @@ void LL_UsartCore::TxDmaIsr()
|
|||
if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
|
||||
if(m_txDma.IsEnabledIt_TE())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::Transfer);
|
||||
TxDmaError(DmaHelper::DmaErrorType::Transfer);
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetFeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
|
||||
if(m_txDma.IsEnabledIt_FE())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::Fifo);
|
||||
TxDmaError(DmaHelper::DmaErrorType::Fifo);
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetDmeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
|
||||
if(m_txDma.IsEnabledIt_DME())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::DirectMode);
|
||||
TxDmaError(DmaHelper::DmaErrorType::DirectMode);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::SetupTransmit(void const *buffer, uint16_t length)
|
||||
void UsartCore::SetupTransmit(void const *buffer, uint16_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(m_txDma.GetDma(), m_txDma.GetStream(), reinterpret_cast<uint32_t>(buffer),
|
||||
LL_USART_DMA_GetRegAddr(m_usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
|
@ -103,7 +103,7 @@ void LL_UsartCore::SetupTransmit(void const *buffer, uint16_t length)
|
|||
}
|
||||
|
||||
|
||||
void LL_UsartCore::SetupReceive(void *buffer, uint16_t length)
|
||||
void UsartCore::SetupReceive(void *buffer, uint16_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(m_rxDma.GetDma(), m_rxDma.GetStream(), LL_USART_DMA_GetRegAddr(m_usart),
|
||||
reinterpret_cast<uint32_t>(buffer), LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
Loading…
Add table
Add a link
Reference in a new issue