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removing prefix LL_ from class/struct names under f4ll namespace

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This commit is contained in:
Attila Body 2019-11-12 15:26:16 +01:00
parent 366d0f991d
commit a2cb50a1af
13 changed files with 147 additions and 146 deletions
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14
inc/ll_consolehandler.h → inc/consolehandler.h
View file

@ -8,15 +8,15 @@
#ifndef LL_CONSOLEHANDLER_H_
#define LL_CONSOLEHANDLER_H_
#include "f4ll/ll_hsusart.h"
#include "f4ll/hsusart.h"
#include "singleton.h"
namespace f4ll {
class LL_ConsoleHandler: public LL_UsartCore, public Singleton<LL_ConsoleHandler>
class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
{
friend class Singleton<LL_ConsoleHandler>;
friend class Singleton<ConsoleHandler>;
public:
// LL_UsartCore pure virtual function implementations
@ -24,15 +24,15 @@ public:
virtual void TransmissionComplete(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
void PrintStats(uint8_t id, LL_HsUsart &usart);
void PrintStats(uint8_t id, HsUsart &usart);
private:
LL_ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
char m_buffer[128];
uint16_t m_used = 0;

14
inc/ll_crchandler.h → inc/crchandler.h
View file

@ -9,16 +9,16 @@
#define LL_CRCHANDLER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
#include "f4ll/ll_dmahelper.h"
#include "f4ll/dmahelper.h"
#include "singleton.h"
extern "C" void _HandleCrcDmaIrq(void);
namespace f4ll {
class LL_CrcHandler : public Singleton<LL_CrcHandler>
class CrcHandler : public Singleton<CrcHandler>
{
friend class Singleton<LL_CrcHandler>;
friend class Singleton<CrcHandler>;
public:
struct ICallback
@ -29,12 +29,12 @@ public:
class SlotBase
{
friend class LL_CrcHandler;
friend class CrcHandler;
public:
struct CrcTask {
void const * volatile m_address; // changed to nullptr when execution starts
uint16_t volatile m_wordCount;
LL_CrcHandler::ICallback *m_callback;
ICallback *m_callback;
uintptr_t m_callbackParam;
};
@ -71,13 +71,13 @@ public:
void DmaTransferCompleted(void);
private:
LL_CrcHandler(DMA_TypeDef *dma, uint32_t stream);
CrcHandler(DMA_TypeDef *dma, uint32_t stream);
friend void ::_HandleCrcDmaIrq(void);
void StartNextTask(void);
void WaitResults(SlotBase &slot, uint8_t task) const;
LL_DmaHelper m_dma;
DmaHelper m_dma;
SlotBase * volatile m_firstSlot = nullptr;
SlotBase * volatile m_activeSlot = nullptr;
int volatile m_activeTask;

6
inc/ll_dmahelper.h → inc/dmahelper.h
View file

@ -13,10 +13,10 @@
namespace f4ll {
class LL_DmaHelper {
class DmaHelper {
public:
LL_DmaHelper(DMA_TypeDef *dma, uint32_t stream);
LL_DmaHelper(LL_DmaHelper const &base) = default;
DmaHelper(DMA_TypeDef *dma, uint32_t stream);
DmaHelper(DmaHelper const &base) = default;
inline DMA_TypeDef* GetDma() const { return m_dma; }
inline uint32_t GetStream() const { return m_stream; }

20
inc/ll_hsusart.h → inc/hsusart.h
View file

@ -8,17 +8,17 @@
#ifndef LL_HSUSART_H_
#define LL_HSUSART_H_
#include <platform/usart_ll.h>
#include "f4ll/ll_usartcore.h"
#include "f4ll/ll_crchandler.h"
#include "f4ll/usartcore.h"
#include "f4ll/crchandler.h"
namespace f4ll {
struct DMAINFO;
class LL_HsUsart : public LL_CrcHandler::ICallback, public LL_UsartCore
class HsUsart : public CrcHandler::ICallback, public UsartCore
{
public:
LL_HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
struct PacketHeader { // !!! size should be multiple of 4 !!!
uint8_t startByte;
@ -48,22 +48,22 @@ public:
};
struct IHsUsartCallback {
virtual bool PacketReceived(LL_HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
virtual bool PacketReceived(HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
};
// LL_CRCHandler::ICallback interface functions
// CRCHandler::ICallback interface functions
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
// LL_UsartCore pure virtual function implementations
// UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
void SetupReceive(void);
@ -100,7 +100,7 @@ private:
Stats m_stats;
bool m_rxBufferSelector = false;
LL_CrcHandler::Slot<2> m_crcSlot;
CrcHandler::Slot<2> m_crcSlot;
IHsUsartCallback *m_userCallback = nullptr;
uintptr_t m_userCallbackParam = 0;
Buffer m_txBuffer;

8
inc/ll_memcpydma.h → inc/memcpydma.h
View file

@ -7,19 +7,19 @@
#ifndef LL_MEMCPY_DMA_H_
#define LL_MEMCPY_DMA_H_
#include "f4ll/ll_dmahelper.h"
#include "f4ll/dmahelper.h"
#include "singleton.h"
namespace f4ll {
class LL_MemcpyDma : public Singleton<LL_MemcpyDma>, private LL_DmaHelper
class MemcpyDma : public Singleton<MemcpyDma>, private DmaHelper
{
friend class Singleton<LL_MemcpyDma>;
friend class Singleton<MemcpyDma>;
public:
void* Copy(void *dst, void const *src, uint16_t length);
void DmaTransferCompleted();
private:
LL_MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
bool volatile m_busy = false;
};

20
inc/ll_usartcore.h → inc/usartcore.h
View file

@ -9,30 +9,30 @@
#define LL_USARTCORE_H_
#include <platform/usart_ll.h>
#include "f4ll/ll_dmahelper.h"
#include "f4ll/dmahelper.h"
namespace f4ll {
class LL_UsartCore
class UsartCore
{
public:
static inline void HandleUsartIrq(LL_UsartCore *_this) { _this->UsartIsr(); }
static inline void HandleRxDmaIrq(LL_UsartCore *_this) { _this->RxDmaIsr(); }
static inline void HandleTxDmaIrq(LL_UsartCore *_this) { _this->TxDmaIsr(); }
static inline void HandleUsartIrq(UsartCore *_this) { _this->UsartIsr(); }
static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
protected:
LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
virtual void ReceiverIdle() = 0;
virtual void TransmissionComplete() = 0;
virtual void RxDmaTransferComplete() = 0;
virtual void RxDmaHalfTransfer() = 0;
virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason) = 0;
virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
virtual void TxDmaTransferComplete() = 0;
virtual void TxDmaHalfTransfer() = 0;
virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason) = 0;
virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
void SetupTransmit(void const *buffer, uint16_t length);
void SetupReceive(void *buffer, uint16_t length);
@ -42,8 +42,8 @@ protected:
void TxDmaIsr();
USART_TypeDef *m_usart;
LL_DmaHelper m_rxDma;
LL_DmaHelper m_txDma;
DmaHelper m_rxDma;
DmaHelper m_txDma;
};
} /* namespace f4ll */

26
src/ll_consolehandler.cpp → src/consolehandler.cpp
View file

@ -5,39 +5,39 @@
* Author: abody
*/
#include "f4ll/ll_consolehandler.h"
#include "f4ll/consolehandler.h"
#include <f4ll_c/strutil.h>
namespace f4ll {
LL_ConsoleHandler::LL_ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
: LL_UsartCore(usart, dma, streamRx, streamTx)
ConsoleHandler::ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
: UsartCore(usart, dma, streamRx, streamTx)
{
}
void LL_ConsoleHandler::ReceiverIdle(void) {}
void LL_ConsoleHandler::TransmissionComplete(void) {}
void LL_ConsoleHandler::RxDmaTransferComplete(void) {}
void LL_ConsoleHandler::RxDmaHalfTransfer(void) {}
void LL_ConsoleHandler::RxDmaError(LL_DmaHelper::DmaErrorType reason) {}
void LL_ConsoleHandler::TxDmaTransferComplete(void)
void ConsoleHandler::ReceiverIdle(void) {}
void ConsoleHandler::TransmissionComplete(void) {}
void ConsoleHandler::RxDmaTransferComplete(void) {}
void ConsoleHandler::RxDmaHalfTransfer(void) {}
void ConsoleHandler::RxDmaError(DmaHelper::DmaErrorType reason) {}
void ConsoleHandler::TxDmaTransferComplete(void)
{
LL_USART_EnableIT_TC(m_usart);
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
}
void LL_ConsoleHandler::TxDmaHalfTransfer(void) {}
void LL_ConsoleHandler::TxDmaError(LL_DmaHelper::DmaErrorType reason) {}
void ConsoleHandler::TxDmaHalfTransfer(void) {}
void ConsoleHandler::TxDmaError(DmaHelper::DmaErrorType reason) {}
#define ADDINFO(b,s,u) \
b += strcpy_ex(b,s); \
b += uitodec(b,u);
void LL_ConsoleHandler::PrintStats(uint8_t id, LL_HsUsart &usart)
void ConsoleHandler::PrintStats(uint8_t id, HsUsart &usart)
{
char ids[] = " : ";
char *buffer = m_buffer;
LL_HsUsart::Stats const &stats(usart.GetStats());
HsUsart::Stats const &stats(usart.GetStats());
ids[0] = id + '0';
buffer += strcpy_ex(buffer, ids);

33
src/ll_crchandler.cpp → src/crchandler.cpp
View file

@ -4,11 +4,11 @@
* Created on: Oct 26, 2019
* Author: compi
*/
#include "f4ll/ll_crchandler.h"
#include "f4ll/crchandler.h"
namespace f4ll {
LL_CrcHandler::LL_CrcHandler(DMA_TypeDef *dma, uint32_t stream)
CrcHandler::CrcHandler(DMA_TypeDef *dma, uint32_t stream)
: m_dma(dma, stream)
{
LL_DMA_EnableIT_TC(dma, stream);
@ -17,7 +17,7 @@ LL_CrcHandler::LL_CrcHandler(DMA_TypeDef *dma, uint32_t stream)
}
void LL_CrcHandler::AttachSlot(SlotBase &slot)
void CrcHandler::AttachSlot(SlotBase &slot)
{
for(unsigned int i = 0; i < slot.m_taskCount; ++i ) {
auto &task(slot[i]);
@ -34,7 +34,7 @@ void LL_CrcHandler::AttachSlot(SlotBase &slot)
}
bool LL_CrcHandler::Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam)
bool CrcHandler::Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam)
{
uint32_t prim = __get_PRIMASK();
bool immediate;
@ -63,22 +63,22 @@ bool LL_CrcHandler::Enqueue(SlotBase &slot, uint8_t task, void const *address, u
return immediate;
}
bool LL_CrcHandler::IsActive(SlotBase &slot, uint8_t task) const
bool CrcHandler::IsActive(SlotBase &slot, uint8_t task) const
{
return task < slot.m_taskCount && slot[task].m_wordCount != 0;
}
bool LL_CrcHandler::IsQueued(SlotBase &slot, uint8_t task) const
bool CrcHandler::IsQueued(SlotBase &slot, uint8_t task) const
{
return task < slot.m_taskCount && slot[task].m_address != nullptr;
}
bool LL_CrcHandler::IsRunning(SlotBase &slot, uint8_t task) const
bool CrcHandler::IsRunning(SlotBase &slot, uint8_t task) const
{
return task < slot.m_taskCount && slot[task].m_wordCount && ! slot[task].m_address;
}
void LL_CrcHandler::DmaTransferCompleted(void)
void CrcHandler::DmaTransferCompleted(void)
{
if(* m_dma.GetIsReg() & m_dma.GetTcMask()) { // DMA transfer complete
* m_dma.GetIfcReg() = m_dma.GetTcMask();
@ -107,13 +107,14 @@ void LL_CrcHandler::DmaTransferCompleted(void)
}
void LL_CrcHandler::StartNextTask(void)
void CrcHandler::StartNextTask(void)
{
bool stillMore;
int index = 0;
bool moreTasks;
uint8_t index = 0;
do {
SlotBase *slot = m_firstSlot;
stillMore = false;
moreTasks = false;
while(slot) {
if(index < slot->m_taskCount) {
if((*slot)[index].m_address) {
@ -127,24 +128,24 @@ void LL_CrcHandler::StartNextTask(void)
return;
}
if(index + 1 < slot->m_taskCount)
stillMore = true;
moreTasks = true;
}
slot = slot->m_next;
}
++index;
} while(stillMore);
} while(moreTasks);
m_activeSlot = nullptr;
}
void LL_CrcHandler::WaitResults(SlotBase &slot, uint8_t task) const
void CrcHandler::WaitResults(SlotBase &slot, uint8_t task) const
{
while(IsQueued(slot, task));
while(IsActive(slot, task));
}
uint32_t LL_CrcHandler::Compute(
uint32_t CrcHandler::Compute(
SlotBase &slot, uint8_t task, void const *address, uint16_t len)
{
uint32_t result;

26
src/dmahelper.cpp Normal file
View file

@ -0,0 +1,26 @@
/*
q * ll_dmahelper.cpp
*
* Created on: Oct 25, 2019
* Author: abody
*/
#include "f4ll/dmahelper.h"
namespace f4ll {
const uint32_t DmaHelper::m_FEMasks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
const uint32_t DmaHelper::m_DMEMasks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
const uint32_t DmaHelper::m_TEMasks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
const uint32_t DmaHelper::m_HTMasks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
const uint32_t DmaHelper::m_TCMasks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
DmaHelper::DmaHelper(DMA_TypeDef *dma, uint32_t stream)
: m_dma(dma)
, m_stream(stream)
, m_isReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR))
, m_ifcReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR))
{
}
} /* namespace f4ll */

64
src/ll_hsusart.cpp → src/hsusart.cpp
View file

@ -5,7 +5,7 @@
* Author: abody
*/
#include <string.h>
#include "f4ll/ll_hsusart.h"
#include "f4ll/hsusart.h"
namespace f4ll {
@ -15,68 +15,68 @@ template<typename T> static inline T RoundUpTo4(T input)
}
LL_HsUsart::LL_HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
: LL_UsartCore(usart, dma, streamRx, streamTx)
HsUsart::HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
: UsartCore(usart, dma, streamRx, streamTx)
{
LL_CrcHandler::Instance().AttachSlot(m_crcSlot);
CrcHandler::Instance().AttachSlot(m_crcSlot);
}
uint8_t *LL_HsUsart::GetTxPacketBuffer(void)
uint8_t* HsUsart::GetTxPacketBuffer(void)
{
return m_txBuffer.packet.payload;
}
USART_TypeDef* LL_HsUsart::GetUsart(void)
USART_TypeDef* HsUsart::GetUsart(void)
{
return m_usart;
}
LL_HsUsart::Stats const & LL_HsUsart::GetStats(void)
HsUsart::Stats const & HsUsart::GetStats(void)
{
return m_stats;
}
bool LL_HsUsart::IsTxBusy()
bool HsUsart::IsTxBusy()
{
return m_txBuffer.busy;
}
bool LL_HsUsart::IsTxFailed()
bool HsUsart::IsTxFailed()
{
return m_txBuffer.error;
}
bool LL_HsUsart::IsRxBusy(bool second)
bool HsUsart::IsRxBusy(bool second)
{
return m_rxBuffers[second].busy;
}
bool LL_HsUsart::IsRxFailed(bool second)
bool HsUsart::IsRxFailed(bool second)
{
return m_rxBuffers[second].error;
}
void LL_HsUsart::RxProcessed(bool second)
void HsUsart::RxProcessed(bool second)
{
m_rxBuffers[second].busy = false;
m_rxBuffers[second].error = false;
}
void LL_HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
void HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
{
m_userCallback = callback;
m_userCallbackParam = callbackParam;
}
void LL_HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
void HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
{
uint8_t hash = STARTMARKER;
@ -89,13 +89,13 @@ void LL_HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
}
bool LL_HsUsart::CheckHeader(PacketHeader &header)
bool HsUsart::CheckHeader(PacketHeader &header)
{
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
}
void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
{
uint16_t payloadLength = RoundUpTo4((uint16_t)length);
@ -106,10 +106,10 @@ void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFor
m_txBuffer.busy = true;
m_txBuffer.error = false;
LL_CrcHandler::Instance().Enqueue(m_crcSlot, 0, &m_txBuffer.packet, sizeof(PacketHeader) + payloadLength,
CrcHandler::Instance().Enqueue(m_crcSlot, 0, &m_txBuffer.packet, sizeof(PacketHeader) + payloadLength,
nullptr, reinterpret_cast<uintptr_t>(m_txBuffer.packet.payload + payloadLength));
while(waitForCrcQueue && LL_CrcHandler::Instance().IsQueued(m_crcSlot, 0));
while(waitForCrcQueue && CrcHandler::Instance().IsQueued(m_crcSlot, 0));
SetupTransmit(&m_txBuffer.packet, m_txBuffer.requestedLength);
@ -117,14 +117,14 @@ void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFor
}
void LL_HsUsart::SetupReceive()
void HsUsart::SetupReceive()
{
m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
LL_UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
}
void LL_HsUsart::ReceiverIdle(void)
void HsUsart::ReceiverIdle(void)
{
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
if(rcvdLen >= sizeof(PacketHeader)) {
@ -144,7 +144,7 @@ void LL_HsUsart::ReceiverIdle(void)
}
void LL_HsUsart::TransmissionComplete(void)
void HsUsart::TransmissionComplete(void)
{
LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
LL_USART_EnableDirectionTx(m_usart);
@ -152,10 +152,10 @@ void LL_HsUsart::TransmissionComplete(void)
}
void LL_HsUsart::RxDmaTransferComplete(void)
void HsUsart::RxDmaTransferComplete(void)
{
if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
LL_CrcHandler::Instance().Enqueue(m_crcSlot, 1,
CrcHandler::Instance().Enqueue(m_crcSlot, 1,
&m_rxBuffers[m_rxBufferSelector].packet,
sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength),
this, m_rxBufferSelector);
@ -166,38 +166,38 @@ void LL_HsUsart::RxDmaTransferComplete(void)
SwitchRxBuffers();
}
void LL_HsUsart::RxDmaHalfTransfer(void)
void HsUsart::RxDmaHalfTransfer(void)
{
}
void LL_HsUsart::RxDmaError(LL_DmaHelper::DmaErrorType reason)
void HsUsart::RxDmaError(DmaHelper::DmaErrorType reason)
{
m_rxBuffers[m_rxBufferSelector].error = 1;
++m_stats.rxDmaError;
SwitchRxBuffers();
}
void LL_HsUsart::TxDmaTransferComplete(void)
void HsUsart::TxDmaTransferComplete(void)
{
LL_USART_EnableIT_TC(m_usart);
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
}
void LL_HsUsart::TxDmaHalfTransfer(void)
void HsUsart::TxDmaHalfTransfer(void)
{
}
void LL_HsUsart::TxDmaError(LL_DmaHelper::DmaErrorType reason)
void HsUsart::TxDmaError(DmaHelper::DmaErrorType reason)
{
m_txBuffer.error = 1;
++m_stats.txDmaError;
}
void LL_HsUsart::SwitchRxBuffers(void)
void HsUsart::SwitchRxBuffers(void)
{
++m_stats.rcvd;
m_rxBufferSelector = !m_rxBufferSelector;
@ -208,7 +208,7 @@ void LL_HsUsart::SwitchRxBuffers(void)
}
void LL_HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
{
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
@ -223,7 +223,7 @@ void LL_HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t tas
}
void LL_HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
void HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
{
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
buf.busy = buf.error = true;

26
src/ll_dmahelper.cpp
View file

@ -1,26 +0,0 @@
/*
q * ll_dmahelper.cpp
*
* Created on: Oct 25, 2019
* Author: abody
*/
#include "f4ll/ll_dmahelper.h"
namespace f4ll {
const uint32_t LL_DmaHelper::m_FEMasks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
const uint32_t LL_DmaHelper::m_DMEMasks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
const uint32_t LL_DmaHelper::m_TEMasks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
const uint32_t LL_DmaHelper::m_HTMasks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
const uint32_t LL_DmaHelper::m_TCMasks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
LL_DmaHelper::LL_DmaHelper(DMA_TypeDef *dma, uint32_t stream)
: m_dma(dma)
, m_stream(stream)
, m_isReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR))
, m_ifcReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR))
{
}
} /* namespace f4ll */

10
src/ll_memcpydma.cpp → src/memcpydma.cpp
View file

@ -5,17 +5,17 @@
* Author: abody
*/
#include "f4ll/ll_memcpydma.h"
#include "f4ll/memcpydma.h"
namespace f4ll {
LL_MemcpyDma::LL_MemcpyDma(DMA_TypeDef *dma, uint32_t stream)
: LL_DmaHelper(dma, stream)
MemcpyDma::MemcpyDma(DMA_TypeDef *dma, uint32_t stream)
: DmaHelper(dma, stream)
{
LL_DMA_EnableIT_TC(dma, stream);
}
void* LL_MemcpyDma::Copy(void *dst, void const *src, uint16_t length)
void* MemcpyDma::Copy(void *dst, void const *src, uint16_t length)
{
LL_DMA_SetM2MSrcAddress(GetDma(), GetStream(), (uint32_t)src);
LL_DMA_SetM2MDstAddress(GetDma(), GetStream(), (uint32_t)dst);
@ -26,7 +26,7 @@ void* LL_MemcpyDma::Copy(void *dst, void const *src, uint16_t length)
return dst;
}
void LL_MemcpyDma::DmaTransferCompleted()
void MemcpyDma::DmaTransferCompleted()
{
if(*GetIsReg() & GetTcMask()) { // DMA transfer complete
*GetIfcReg() = GetTcMask();

26
src/ll_usartcore.cpp → src/usartcore.cpp
View file

@ -5,11 +5,11 @@
* Author: abody
*/
#include "f4ll/ll_usartcore.h"
#include "f4ll/usartcore.h"
namespace f4ll {
LL_UsartCore::LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
: m_usart(usart)
, m_rxDma(dma, streamRx)
, m_txDma(dma, streamTx)
@ -21,7 +21,7 @@ LL_UsartCore::LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stre
LL_USART_EnableIT_IDLE(usart);
}
void LL_UsartCore::UsartIsr()
void UsartCore::UsartIsr()
{
if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) { // receiver idle
LL_USART_ClearFlag_IDLE(m_usart);
@ -33,7 +33,7 @@ void LL_UsartCore::UsartIsr()
}
void LL_UsartCore::RxDmaIsr()
void UsartCore::RxDmaIsr()
{
if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
@ -48,22 +48,22 @@ void LL_UsartCore::RxDmaIsr()
if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
if(m_rxDma.IsEnabledIt_TE())
RxDmaError(LL_DmaHelper::DmaErrorType::Transfer);
RxDmaError(DmaHelper::DmaErrorType::Transfer);
}
if(*m_rxDma.GetIsReg() & m_rxDma.GetFeMask()) {
*m_rxDma.GetIfcReg() = m_rxDma.GetFeMask();
if(m_rxDma.IsEnabledIt_FE())
RxDmaError(LL_DmaHelper::DmaErrorType::Fifo);
RxDmaError(DmaHelper::DmaErrorType::Fifo);
}
if(*m_rxDma.GetIsReg() & m_rxDma.GetDmeMask()) {
*m_rxDma.GetIfcReg() = m_rxDma.GetDmeMask();
if(m_rxDma.IsEnabledIt_DME())
RxDmaError(LL_DmaHelper::DmaErrorType::DirectMode);
RxDmaError(DmaHelper::DmaErrorType::DirectMode);
}
}
void LL_UsartCore::TxDmaIsr()
void UsartCore::TxDmaIsr()
{
if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
@ -78,22 +78,22 @@ void LL_UsartCore::TxDmaIsr()
if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
if(m_txDma.IsEnabledIt_TE())
TxDmaError(LL_DmaHelper::DmaErrorType::Transfer);
TxDmaError(DmaHelper::DmaErrorType::Transfer);
}
if(*m_txDma.GetIsReg() & m_txDma.GetFeMask()) {
*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
if(m_txDma.IsEnabledIt_FE())
TxDmaError(LL_DmaHelper::DmaErrorType::Fifo);
TxDmaError(DmaHelper::DmaErrorType::Fifo);
}
if(*m_txDma.GetIsReg() & m_txDma.GetDmeMask()) {
*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
if(m_txDma.IsEnabledIt_DME())
TxDmaError(LL_DmaHelper::DmaErrorType::DirectMode);
TxDmaError(DmaHelper::DmaErrorType::DirectMode);
}
}
void LL_UsartCore::SetupTransmit(void const *buffer, uint16_t length)
void UsartCore::SetupTransmit(void const *buffer, uint16_t length)
{
LL_DMA_ConfigAddresses(m_txDma.GetDma(), m_txDma.GetStream(), reinterpret_cast<uint32_t>(buffer),
LL_USART_DMA_GetRegAddr(m_usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
@ -103,7 +103,7 @@ void LL_UsartCore::SetupTransmit(void const *buffer, uint16_t length)
}
void LL_UsartCore::SetupReceive(void *buffer, uint16_t length)
void UsartCore::SetupReceive(void *buffer, uint16_t length)
{
LL_DMA_ConfigAddresses(m_rxDma.GetDma(), m_rxDma.GetStream(), LL_USART_DMA_GetRegAddr(m_usart),
reinterpret_cast<uint32_t>(buffer), LL_DMA_DIRECTION_PERIPH_TO_MEMORY);