HsUsart renamed to PacketUsart, volatile usage review
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a2cb50a1af
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708435dcc5
8 changed files with 153 additions and 148 deletions
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@ -8,7 +8,7 @@
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#ifndef LL_CONSOLEHANDLER_H_
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#define LL_CONSOLEHANDLER_H_
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#include "f4ll/hsusart.h"
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#include "f4ll/packetusart.h"
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#include "singleton.h"
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@ -19,9 +19,16 @@ class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
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friend class Singleton<ConsoleHandler>;
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public:
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void PrintStats(uint8_t id, PacketUsart &usart);
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private:
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ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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@ -29,11 +36,6 @@ public:
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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void PrintStats(uint8_t id, HsUsart &usart);
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private:
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ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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char m_buffer[128];
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uint16_t m_used = 0;
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};
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@ -32,17 +32,17 @@ public:
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friend class CrcHandler;
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public:
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struct CrcTask {
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void const * volatile m_address; // changed to nullptr when execution starts
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uint16_t volatile m_wordCount;
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void const * m_address; // changed to nullptr when execution starts
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uint16_t m_wordCount;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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};
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private:
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SlotBase *m_next = nullptr;
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SlotBase volatile *m_next = nullptr;
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uint8_t m_taskCount;
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virtual CrcTask& operator[](int index) = 0;
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virtual CrcTask volatile & operator[](int index) volatile = 0;
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protected:
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SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
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@ -54,7 +54,7 @@ public:
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{
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public:
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Slot() : SlotBase(n) {}
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virtual CrcTask& operator[](int index) { return m_tasks[index]; }
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virtual CrcTask volatile & operator[](int index) volatile { return m_tasks[index]; }
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private:
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Slot::CrcTask m_tasks[n];
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@ -78,8 +78,8 @@ private:
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void WaitResults(SlotBase &slot, uint8_t task) const;
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DmaHelper m_dma;
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SlotBase * volatile m_firstSlot = nullptr;
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SlotBase * volatile m_activeSlot = nullptr;
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SlotBase volatile *m_firstSlot = nullptr;
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SlotBase volatile *m_activeSlot = nullptr;
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int volatile m_activeTask;
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};
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@ -15,10 +15,11 @@ namespace f4ll {
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struct DMAINFO;
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class HsUsart : public CrcHandler::ICallback, public UsartCore
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class PacketUsart : public CrcHandler::ICallback, public UsartCore
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{
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// friend class UsartCore;
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public:
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HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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struct PacketHeader { // !!! size should be multiple of 4 !!!
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uint8_t startByte;
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@ -48,34 +49,27 @@ public:
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};
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struct IHsUsartCallback {
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virtual bool PacketReceived(HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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};
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// CRCHandler::ICallback interface functions
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
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// UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
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void SetupReceive(void);
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void RxProcessed(bool second);
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uint8_t* GetTxPacketBuffer(void);
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USART_TypeDef* GetUsart(void);
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Stats const & GetStats(void);
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bool IsTxBusy(void);
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bool IsTxFailed(void);
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bool IsRxBusy(bool second);
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bool IsRxFailed(bool second);
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// Getters
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uint8_t* GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
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uint8_t const * GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
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USART_TypeDef* GetUsart(void) const { return m_usart; }
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Stats const & GetStats(void) const { return m_stats; }
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inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
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inline bool IsTxFailed(void) const { return m_txBuffer.error; }
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inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
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inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
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void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
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@ -84,11 +78,23 @@ private:
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bool CheckHeader(PacketHeader &header);
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void SwitchRxBuffers(void);
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// UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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struct Buffer {
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Packet packet;
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//transfer area ends here
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volatile bool busy = 0;
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volatile bool error = 0;
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bool volatile busy = 0;
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bool volatile error = 0;
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uint16_t requestedLength = 0;
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uint32_t errorInfo = 0;
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};
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@ -20,30 +20,34 @@ public:
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static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
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static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
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void SetupTransmit(void const *buffer, uint16_t length);
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void SetupReceive(void *buffer, uint16_t length);
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protected:
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UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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virtual void ReceiverIdle() = 0;
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virtual void TransmissionComplete() = 0;
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USART_TypeDef *m_usart;
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DmaHelper m_rxDma;
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DmaHelper m_txDma;
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virtual void RxDmaTransferComplete() = 0;
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virtual void RxDmaHalfTransfer() = 0;
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private:
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virtual void ReceiverIdle(void) = 0;
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virtual void TransmissionComplete(void) = 0;
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virtual void FramingError(void) = 0;
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virtual void Overrun(void) = 0;
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virtual void RxDmaTransferComplete(void) = 0;
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virtual void RxDmaHalfTransfer(void) = 0;
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virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
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virtual void TxDmaTransferComplete() = 0;
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virtual void TxDmaHalfTransfer() = 0;
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virtual void TxDmaTransferComplete(void) = 0;
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virtual void TxDmaHalfTransfer(void) = 0;
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virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
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void SetupTransmit(void const *buffer, uint16_t length);
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void SetupReceive(void *buffer, uint16_t length);
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void UsartIsr();
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void RxDmaIsr();
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void TxDmaIsr();
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USART_TypeDef *m_usart;
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DmaHelper m_rxDma;
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DmaHelper m_txDma;
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};
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} /* namespace f4ll */
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@ -17,6 +17,8 @@ ConsoleHandler::ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t
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void ConsoleHandler::ReceiverIdle(void) {}
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void ConsoleHandler::TransmissionComplete(void) {}
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void ConsoleHandler::FramingError(void) {}
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void ConsoleHandler::Overrun(void) {}
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void ConsoleHandler::RxDmaTransferComplete(void) {}
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void ConsoleHandler::RxDmaHalfTransfer(void) {}
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void ConsoleHandler::RxDmaError(DmaHelper::DmaErrorType reason) {}
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@ -33,11 +35,11 @@ void ConsoleHandler::TxDmaError(DmaHelper::DmaErrorType reason) {}
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b += strcpy_ex(b,s); \
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b += uitodec(b,u);
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void ConsoleHandler::PrintStats(uint8_t id, HsUsart &usart)
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void ConsoleHandler::PrintStats(uint8_t id, PacketUsart &usart)
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{
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char ids[] = " : ";
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char *buffer = m_buffer;
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HsUsart::Stats const &stats(usart.GetStats());
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PacketUsart::Stats const &stats(usart.GetStats());
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ids[0] = id + '0';
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buffer += strcpy_ex(buffer, ids);
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@ -113,7 +113,7 @@ void CrcHandler::StartNextTask(void)
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uint8_t index = 0;
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do {
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SlotBase *slot = m_firstSlot;
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SlotBase volatile *slot = m_firstSlot;
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moreTasks = false;
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while(slot) {
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if(index < slot->m_taskCount) {
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@ -5,7 +5,7 @@
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* Author: abody
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*/
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#include <string.h>
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#include "f4ll/hsusart.h"
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#include "f4ll/packetusart.h"
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namespace f4ll {
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@ -15,87 +15,28 @@ template<typename T> static inline T RoundUpTo4(T input)
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}
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HsUsart::HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
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PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
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: UsartCore(usart, dma, streamRx, streamTx)
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{
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CrcHandler::Instance().AttachSlot(m_crcSlot);
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}
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uint8_t* HsUsart::GetTxPacketBuffer(void)
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{
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return m_txBuffer.packet.payload;
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}
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USART_TypeDef* HsUsart::GetUsart(void)
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{
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return m_usart;
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}
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HsUsart::Stats const & HsUsart::GetStats(void)
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{
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return m_stats;
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}
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bool HsUsart::IsTxBusy()
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{
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return m_txBuffer.busy;
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}
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bool HsUsart::IsTxFailed()
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{
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return m_txBuffer.error;
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}
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bool HsUsart::IsRxBusy(bool second)
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{
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return m_rxBuffers[second].busy;
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}
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bool HsUsart::IsRxFailed(bool second)
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{
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return m_rxBuffers[second].error;
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}
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void HsUsart::RxProcessed(bool second)
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void PacketUsart::RxProcessed(bool second)
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{
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m_rxBuffers[second].busy = false;
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m_rxBuffers[second].error = false;
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}
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void HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
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void PacketUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
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{
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m_userCallback = callback;
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m_userCallbackParam = callbackParam;
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}
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void HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
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{
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uint8_t hash = STARTMARKER;
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packet.header.startByte = STARTMARKER;
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packet.header.serial = serialNo;
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hash ^= serialNo;
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packet.header.payloadLength = length;
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hash ^= length;
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packet.header.hash = hash;
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}
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bool HsUsart::CheckHeader(PacketHeader &header)
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{
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return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
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}
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void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
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void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
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{
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uint16_t payloadLength = RoundUpTo4((uint16_t)length);
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@ -117,16 +58,21 @@ void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrc
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}
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void HsUsart::SetupReceive()
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void PacketUsart::SetupReceive()
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{
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m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
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UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
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}
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void HsUsart::ReceiverIdle(void)
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//////////////////////////////////////
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// UsartCore pure virtual functions //
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//////////////////////////////////////
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void PacketUsart::ReceiverIdle(void)
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{
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uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
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if(rcvdLen >= sizeof(PacketHeader)) {
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if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
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if(rcvdLen >= sizeof(PacketHeader) +
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@ -144,7 +90,7 @@ void HsUsart::ReceiverIdle(void)
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}
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void HsUsart::TransmissionComplete(void)
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void PacketUsart::TransmissionComplete(void)
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{
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LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
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LL_USART_EnableDirectionTx(m_usart);
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@ -152,7 +98,13 @@ void HsUsart::TransmissionComplete(void)
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}
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void HsUsart::RxDmaTransferComplete(void)
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void PacketUsart::FramingError(void) {}
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void PacketUsart::Overrun(void) {}
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void PacketUsart::RxDmaTransferComplete(void)
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{
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if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
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CrcHandler::Instance().Enqueue(m_crcSlot, 1,
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@ -166,38 +118,61 @@ void HsUsart::RxDmaTransferComplete(void)
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SwitchRxBuffers();
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}
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void HsUsart::RxDmaHalfTransfer(void)
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void PacketUsart::RxDmaHalfTransfer(void)
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{
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}
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void HsUsart::RxDmaError(DmaHelper::DmaErrorType reason)
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void PacketUsart::RxDmaError(DmaHelper::DmaErrorType reason)
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{
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m_rxBuffers[m_rxBufferSelector].error = 1;
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++m_stats.rxDmaError;
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SwitchRxBuffers();
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}
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void HsUsart::TxDmaTransferComplete(void)
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void PacketUsart::TxDmaTransferComplete(void)
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{
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LL_USART_EnableIT_TC(m_usart);
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LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
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}
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void HsUsart::TxDmaHalfTransfer(void)
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void PacketUsart::TxDmaHalfTransfer(void)
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{
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}
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void HsUsart::TxDmaError(DmaHelper::DmaErrorType reason)
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void PacketUsart::TxDmaError(DmaHelper::DmaErrorType reason)
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{
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m_txBuffer.error = 1;
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++m_stats.txDmaError;
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}
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void HsUsart::SwitchRxBuffers(void)
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///////////////////////
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// Private functions //
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///////////////////////
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void PacketUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
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{
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uint8_t hash = STARTMARKER;
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packet.header.startByte = STARTMARKER;
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packet.header.serial = serialNo;
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hash ^= serialNo;
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packet.header.payloadLength = length;
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hash ^= length;
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packet.header.hash = hash;
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}
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bool PacketUsart::CheckHeader(PacketHeader &header)
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{
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return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
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}
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void PacketUsart::SwitchRxBuffers(void)
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{
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++m_stats.rcvd;
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m_rxBufferSelector = !m_rxBufferSelector;
|
||||
|
|
@ -207,8 +182,11 @@ void HsUsart::SwitchRxBuffers(void)
|
|||
SetupReceive();
|
||||
}
|
||||
|
||||
///////////////////////////
|
||||
// CrcHandler::ICallback //
|
||||
///////////////////////////
|
||||
|
||||
void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
void PacketUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
{
|
||||
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
|
||||
|
||||
|
|
@ -223,7 +201,7 @@ void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
|||
}
|
||||
|
||||
|
||||
void HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
void PacketUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
|
||||
{
|
||||
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
|
||||
buf.busy = buf.error = true;
|
||||
|
|
@ -19,16 +19,29 @@ UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx,
|
|||
LL_DMA_EnableIT_TC(dma, streamTx);
|
||||
LL_DMA_EnableIT_TE(dma, streamTx);
|
||||
LL_USART_EnableIT_IDLE(usart);
|
||||
LL_USART_EnableIT_ERROR(usart);
|
||||
}
|
||||
|
||||
|
||||
void UsartCore::UsartIsr()
|
||||
{
|
||||
if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(m_usart);
|
||||
ReceiverIdle();
|
||||
} else if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
|
||||
if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(m_usart);
|
||||
TransmissionComplete();
|
||||
} else if(LL_USART_IsEnabledIT_ERROR(m_usart)) {
|
||||
uint32_t status = m_usart->SR;
|
||||
volatile uint32_t tmpreg = m_usart->DR; // clearing some of the error/status bits in the HW
|
||||
(void) tmpreg;
|
||||
|
||||
if(status & USART_SR_IDLE) {
|
||||
ReceiverIdle();
|
||||
}
|
||||
if(status & USART_SR_FE) {
|
||||
FramingError();
|
||||
}
|
||||
if(status & USART_SR_ORE) {
|
||||
Overrun();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue