HsUsart renamed to PacketUsart, volatile usage review
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8 changed files with 153 additions and 148 deletions
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@ -8,7 +8,7 @@
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#ifndef LL_CONSOLEHANDLER_H_
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#define LL_CONSOLEHANDLER_H_
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#include "f4ll/hsusart.h"
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#include "f4ll/packetusart.h"
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#include "singleton.h"
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@ -19,9 +19,16 @@ class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
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friend class Singleton<ConsoleHandler>;
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public:
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void PrintStats(uint8_t id, PacketUsart &usart);
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private:
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ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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@ -29,11 +36,6 @@ public:
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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void PrintStats(uint8_t id, HsUsart &usart);
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private:
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ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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char m_buffer[128];
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uint16_t m_used = 0;
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};
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@ -32,17 +32,17 @@ public:
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friend class CrcHandler;
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public:
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struct CrcTask {
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void const * volatile m_address; // changed to nullptr when execution starts
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uint16_t volatile m_wordCount;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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void const * m_address; // changed to nullptr when execution starts
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uint16_t m_wordCount;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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};
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private:
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SlotBase *m_next = nullptr;
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SlotBase volatile *m_next = nullptr;
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uint8_t m_taskCount;
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virtual CrcTask& operator[](int index) = 0;
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virtual CrcTask volatile & operator[](int index) volatile = 0;
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protected:
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SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
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@ -54,7 +54,7 @@ public:
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{
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public:
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Slot() : SlotBase(n) {}
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virtual CrcTask& operator[](int index) { return m_tasks[index]; }
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virtual CrcTask volatile & operator[](int index) volatile { return m_tasks[index]; }
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private:
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Slot::CrcTask m_tasks[n];
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@ -68,7 +68,7 @@ public:
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bool IsQueued(SlotBase &slot, uint8_t task) const;
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bool IsRunning(SlotBase &slot, uint8_t task) const;
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void DmaTransferCompleted(void);
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void DmaTransferCompleted(void);
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private:
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CrcHandler(DMA_TypeDef *dma, uint32_t stream);
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@ -77,10 +77,10 @@ private:
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void StartNextTask(void);
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void WaitResults(SlotBase &slot, uint8_t task) const;
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DmaHelper m_dma;
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SlotBase * volatile m_firstSlot = nullptr;
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SlotBase * volatile m_activeSlot = nullptr;
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int volatile m_activeTask;
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DmaHelper m_dma;
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SlotBase volatile *m_firstSlot = nullptr;
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SlotBase volatile *m_activeSlot = nullptr;
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int volatile m_activeTask;
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};
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@ -15,10 +15,11 @@ namespace f4ll {
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struct DMAINFO;
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class HsUsart : public CrcHandler::ICallback, public UsartCore
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class PacketUsart : public CrcHandler::ICallback, public UsartCore
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{
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// friend class UsartCore;
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public:
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HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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struct PacketHeader { // !!! size should be multiple of 4 !!!
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uint8_t startByte;
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@ -33,49 +34,42 @@ public:
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} __attribute__((aligned));
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struct Stats {
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uint32_t overrun = 0;
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uint32_t hdrError = 0;
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uint32_t payloadErrror = 0;
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uint32_t pep1 = 0;
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uint32_t pep2 = 0;
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uint32_t rxDmaError = 0;
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uint32_t txDmaError = 0;
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uint32_t rcvd = 0;
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uint32_t premature_hdr = 0;
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uint32_t overrun = 0;
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uint32_t hdrError = 0;
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uint32_t payloadErrror = 0;
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uint32_t pep1 = 0;
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uint32_t pep2 = 0;
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uint32_t rxDmaError = 0;
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uint32_t txDmaError = 0;
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uint32_t rcvd = 0;
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uint32_t premature_hdr = 0;
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uint32_t premature_payload = 0;
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uint32_t sent = 0;
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uint32_t skiped = 0;
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uint32_t sent = 0;
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uint32_t skiped = 0;
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};
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struct IHsUsartCallback {
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virtual bool PacketReceived(HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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};
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// CRCHandler::ICallback interface functions
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
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// UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
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void SetupReceive(void);
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void RxProcessed(bool second);
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uint8_t* GetTxPacketBuffer(void);
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USART_TypeDef* GetUsart(void);
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Stats const & GetStats(void);
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bool IsTxBusy(void);
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bool IsTxFailed(void);
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bool IsRxBusy(bool second);
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bool IsRxFailed(bool second);
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// Getters
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uint8_t* GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
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uint8_t const * GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
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USART_TypeDef* GetUsart(void) const { return m_usart; }
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Stats const & GetStats(void) const { return m_stats; }
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inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
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inline bool IsTxFailed(void) const { return m_txBuffer.error; }
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inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
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inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
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void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
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@ -84,13 +78,25 @@ private:
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bool CheckHeader(PacketHeader &header);
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void SwitchRxBuffers(void);
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// UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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struct Buffer {
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Packet packet;
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//transfer area ends here
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volatile bool busy = 0;
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volatile bool error = 0;
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bool volatile busy = 0;
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bool volatile error = 0;
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uint16_t requestedLength = 0;
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uint32_t errorInfo = 0;
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uint32_t errorInfo = 0;
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};
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static const uint8_t STARTMARKER = 0x95;
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@ -20,30 +20,34 @@ public:
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static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
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static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
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void SetupTransmit(void const *buffer, uint16_t length);
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void SetupReceive(void *buffer, uint16_t length);
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protected:
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UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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virtual void ReceiverIdle() = 0;
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virtual void TransmissionComplete() = 0;
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USART_TypeDef *m_usart;
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DmaHelper m_rxDma;
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DmaHelper m_txDma;
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virtual void RxDmaTransferComplete() = 0;
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virtual void RxDmaHalfTransfer() = 0;
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private:
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virtual void ReceiverIdle(void) = 0;
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virtual void TransmissionComplete(void) = 0;
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virtual void FramingError(void) = 0;
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virtual void Overrun(void) = 0;
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virtual void RxDmaTransferComplete(void) = 0;
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virtual void RxDmaHalfTransfer(void) = 0;
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virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
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virtual void TxDmaTransferComplete() = 0;
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virtual void TxDmaHalfTransfer() = 0;
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virtual void TxDmaTransferComplete(void) = 0;
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virtual void TxDmaHalfTransfer(void) = 0;
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virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
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void SetupTransmit(void const *buffer, uint16_t length);
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void SetupReceive(void *buffer, uint16_t length);
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void UsartIsr();
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void RxDmaIsr();
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void TxDmaIsr();
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USART_TypeDef *m_usart;
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DmaHelper m_rxDma;
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DmaHelper m_txDma;
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};
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} /* namespace f4ll */
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