Code compiles
This commit is contained in:
parent
7a74273ca7
commit
2aa08f20a0
118 changed files with 119250 additions and 34 deletions
60
lib/console_handler.c
Normal file
60
lib/console_handler.c
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@ -0,0 +1,60 @@
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/*
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* interrupt.c
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*
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* Created on: Aug 29, 2019
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* Author: abody
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*/
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#include "main.h"
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#include "globals.h"
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#include "usart_handler.h"
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#include "strutil.h"
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void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart) // debug usart
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{
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if(*info->isReg & info->tcMask) { // DMA transfer complete
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*info->ifcReg = info->tcMask;
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LL_USART_EnableIT_TC(usart);
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LL_DMA_DisableStream(info->dma, info->stream);
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}
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else if(*info->isReg & info->htMask)
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*info->ifcReg = info->htMask;
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else if(*info->isReg & info->teMask)
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*info->ifcReg = info->teMask;
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}
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void HandleConsoleUsartIrq(USART_TypeDef *usart)
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{
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if(LL_USART_IsActiveFlag_TC(usart) && LL_USART_IsEnabledIT_TC(usart)) // transmission complete
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LL_USART_DisableIT_TC(usart);
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}
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#define ADDINFO(b,s,u) \
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b += strcpy_ex(b,s); \
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b += uitodec(b,u);
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void PrintStats(char *buffer, uint8_t id, STATS *stats, USART_TypeDef *usart, DMAINFO *dmaInfo)
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{
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char ids[] = " : ";
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char *bs = buffer;
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ids[0] = id + '0';
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buffer += strcpy_ex(buffer, ids);
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ADDINFO(buffer, " s: ", stats->sent);
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ADDINFO(buffer, " r: ", stats->rcvd);
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ADDINFO(buffer, " sk: ", stats->skiped);
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ADDINFO(buffer, " or: ", stats->overrun);
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ADDINFO(buffer, " he: ", stats->hdrError);
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buffer += strcpy_ex(buffer,",0x");
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buffer += uitohex(buffer, stats->lastErrHdr, 8);
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ADDINFO(buffer, " pe: ", stats->payloadErrror);
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buffer += strcpy_ex(buffer,",0x");
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buffer += uitohex(buffer, stats->pep1, 8);
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buffer += strcpy_ex(buffer,",0x");
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buffer += uitohex(buffer, stats->pep2, 8);
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ADDINFO(buffer, " de: ", stats->dmaError);
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ADDINFO(buffer, " pmh: ", stats->premature_hdr);
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ADDINFO(buffer, " pmp: ", stats->premature_payload);
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buffer += strcpy_ex(buffer, "\r\n");
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SetupTransmit(usart, dmaInfo->dma, dmaInfo->stream, bs, buffer - bs + 1);
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}
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19
lib/console_handler.h
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19
lib/console_handler.h
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/*
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* interrupt.h
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*
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* Created on: Aug 29, 2019
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* Author: abody
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*/
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#ifndef INTERRUPT_HANDLERS_H_
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#define INTERRUPT_HANDLERS_H_
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#include "usart.h"
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#include "dma_helper.h"
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void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart);
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void HandleConsoleUsartIrq(USART_TypeDef *usart);
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void PrintStats(char *buffer, uint8_t id, STATS *stats, USART_TypeDef *usart, DMAINFO *dmaInfo);
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#endif /* INTERRUPT_HANDLERS_H_ */
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122
lib/crc_handler.c
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122
lib/crc_handler.c
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/*
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* interrupt.c
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*
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* Created on: Aug 29, 2019
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* Author: abody
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*/
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#include <dma.h>
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#include <string.h>
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#include "crc.h"
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#include "dma_helper.h"
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#include "diag.h"
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#include "crc_handler.h"
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#ifndef DIAG_CRC_CALC_START
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# define DIAG_CRC_CALC_START()
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#endif
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#ifndef DIAG_CRC_CALC_END
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# define DIAG_CRC_CALC_END()
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#endif
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void InitCrcStatus(struct crcstatus_t *st, DMA_TypeDef *dma, uint32_t stream)
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{
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InitDmaInfo(&st->dmaInfo, dma, stream);
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LL_DMA_EnableIT_TC(dma, stream);
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LL_DMA_EnableIT_TE(dma, stream);
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LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
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st->activeSlot = 0xff;
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memset((void*)st->crcTasks, 0, sizeof(st->crcTasks));
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}
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uint8_t EnqueueCrcTask(struct crcstatus_t *status, uint8_t slot, uint8_t *address, uint16_t len,
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void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
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{
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uint32_t prim = __get_PRIMASK();
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uint16_t need_start;
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while(status->activeSlot == slot);
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__disable_irq();
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need_start = (status->activeSlot == 0xff);
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status->crcTasks[slot].address = need_start ? NULL : address;
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status->crcTasks[slot].wordCount = (len+3)/4;
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status->crcTasks[slot].callback = callback;
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status->crcTasks[slot].callbackParam = callbackParam;
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if(need_start)
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status->activeSlot = slot;
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__set_PRIMASK(prim);
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if(need_start) {
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CRC->CR = 1;
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LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)address);
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LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, (len+3)/4);
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DIAG_CRC_CALC_START();
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LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
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}
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return need_start;
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}
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void WaitCrcResults(struct crcstatus_t *status, uint8_t slot)
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{
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while(IsSlotQueued(status, slot));
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while(GetActiveSlot(status) == slot);
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}
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uint32_t ComputeCrc(struct crcstatus_t *status, uint8_t slot, uint8_t *address, uint16_t len)
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{
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uint32_t result;
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EnqueueCrcTask(status, slot, address, len, NULL, &result);
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while(status->crcTasks[slot].callbackParam);
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return result;
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}
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void StartNextCrcTask(struct crcstatus_t *status)
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{
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uint16_t slot;
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for(slot = 0; slot < CRCTASKCOUNT; ++slot)
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if(status->crcTasks[slot].address) {
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status->activeSlot = slot;
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CRC->CR = 1;
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LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)status->crcTasks[slot].address);
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LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, status->crcTasks[slot].wordCount);
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DIAG_CRC_CALC_START();
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LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
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status->crcTasks[slot].address = NULL; // marking as started
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return;
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}
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status->activeSlot = 0xff;
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}
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void HandleCrcDmaIrq(struct crcstatus_t *status)
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{
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if(*status->dmaInfo.isReg & status->dmaInfo.tcMask) { // DMA transfer complete
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*status->dmaInfo.ifcReg = status->dmaInfo.tcMask;
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LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
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if(status->activeSlot != 0xff) {
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struct crctask_t *tsk = (struct crctask_t *)&status->crcTasks[status->activeSlot];
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if(tsk->callback)
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tsk->callback(tsk->callbackParam, CRC->DR, 1);
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else if(tsk->callbackParam)
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*(uint32_t*)tsk->callbackParam = CRC->DR;
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tsk->callback = tsk->callbackParam = NULL; // marking as inactive
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DIAG_CRC_CALC_END();
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StartNextCrcTask(status);
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}
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}
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else if(*status->dmaInfo.isReg & status->dmaInfo.teMask) {
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*status->dmaInfo.ifcReg = status->dmaInfo.teMask;
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LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
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if(status->activeSlot != 0xff) {
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struct crctask_t *tsk = (struct crctask_t *)&status->crcTasks[status->activeSlot];
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if(tsk->callback)
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tsk->callback(tsk->callbackParam, CRC->DR, 0);
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else if(tsk->callbackParam)
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*(uint32_t*)tsk->callbackParam = 0xffffffff;
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tsk->callback = tsk->callbackParam = NULL; // marking as inactive
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DIAG_CRC_CALC_END();
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StartNextCrcTask(status);
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}
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}
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}
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51
lib/crc_handler.h
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51
lib/crc_handler.h
Normal file
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/*
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* interrupt.h
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*
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* Created on: Aug 29, 2019
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* Author: abody
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*/
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#ifndef CRC_HANDLER_H_
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#define CRC_HANDLER_H_
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#include <inttypes.h>
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#include <dma_helper.h>
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#include "config.h"
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#ifndef CRCTASKCOUNT
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#define CRCTASKCOUNT 8
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#endif
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struct crcstatus_t {
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DMAINFO dmaInfo;
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volatile uint8_t activeSlot;
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struct crctask_t {
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void *address;
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uint16_t wordCount;
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void (*callback)(void*, uint32_t, uint8_t);
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void *callbackParam;
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} volatile crcTasks[CRCTASKCOUNT];
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};
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//#define CRCTASKCOUNT (sizeof(((struct crcstatus_t*)0)->crcTasks)/sizeof(struct crctask_t))
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void InitCrcStatus(struct crcstatus_t *status, DMA_TypeDef *dma, uint32_t stream);
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static inline uint8_t GetActiveSlot(struct crcstatus_t *status) {
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return status->activeSlot;
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}
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static inline uint8_t IsSlotQueued(struct crcstatus_t *status, uint8_t slot) {
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return status->crcTasks[slot].address != NULL;
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}
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static inline uint8_t IsSlotActive(struct crcstatus_t *status, uint8_t slot) {
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return status->crcTasks[slot].callback != NULL || status->crcTasks[slot].callbackParam != NULL;
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}
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uint8_t EnqueueCrcTask(struct crcstatus_t *crcStatus, uint8_t slot, uint8_t *address, uint16_t len,
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void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
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void WaitCrcResults(struct crcstatus_t *status, uint8_t slot);
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uint32_t ComputeCrc(struct crcstatus_t *status, uint8_t slot, uint8_t *address, uint16_t len);
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void ComputeCrcAsync(struct crcstatus_t *status, uint8_t slot,
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uint8_t *address, uint16_t len,
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void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
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void HandleCrcDmaIrq(struct crcstatus_t *status);
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#endif /* CRC_HANDLER_H_ */
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78
lib/dma_helper.c
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78
lib/dma_helper.c
Normal file
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/*
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* dma_helper.c
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*
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* Created on: Sep 18, 2019
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* Author: abody
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*/
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#include "dma_helper.h"
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volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream)
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{
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if(dma == DMA1)
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return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR;
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else
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return (stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR;
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}
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volatile uint32_t* GetIcfReg(DMA_TypeDef *dma, uint32_t stream)
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{
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if(dma == DMA1)
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return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR;
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else
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return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR;
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}
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uint32_t GetFeMask(uint32_t stream)
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{
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static const uint32_t masks[8] = {
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DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7
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};
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return masks[stream];
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}
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uint32_t GetDmeMask(uint32_t stream)
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{
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static const uint32_t teMasks[8] = {
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DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7
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};
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return teMasks[stream];
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}
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uint32_t GetTeMask(uint32_t stream)
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{
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static const uint32_t teMasks[8] = {
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DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7
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};
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return teMasks[stream];
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}
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uint32_t GetHtMask(uint32_t stream)
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{
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static const uint32_t teMasks[8] = {
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DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7
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};
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return teMasks[stream];
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}
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uint32_t GetTcMask(uint32_t stream)
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{
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static const uint32_t tcMasks[8] = {
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DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7
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};
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return tcMasks[stream];
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}
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void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream)
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{
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info->dma = dma;
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info->stream = stream;
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info->isReg = GetIsReg(dma, stream);
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info->ifcReg = GetIcfReg(dma, stream);
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info->feMask = GetFeMask(stream);
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info->dmeMask = GetDmeMask(stream);
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info->teMask = GetTeMask(stream);
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info->htMask = GetHtMask(stream);
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info->tcMask = GetTcMask(stream);
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}
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34
lib/dma_helper.h
Normal file
34
lib/dma_helper.h
Normal file
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/*
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* dma_helper.h
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*
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* Created on: Sep 18, 2019
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* Author: abody
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*/
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#ifndef DMA_HELPER_H_
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#define DMA_HELPER_H_
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#include <inttypes.h>
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#include "dma.h"
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typedef struct {
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DMA_TypeDef *dma;
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uint32_t stream;
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volatile uint32_t *isReg;
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volatile uint32_t *ifcReg;
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uint32_t feMask;
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uint32_t dmeMask;
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uint32_t teMask;
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uint32_t htMask;
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uint32_t tcMask;
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} DMAINFO;
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volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream);
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volatile uint32_t* GetIcfReg(DMA_TypeDef *dma, uint32_t stream);
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uint32_t GetDmeMask(uint32_t stream);
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uint32_t GetTeMask(uint32_t stream);
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uint32_t GetHtMask(uint32_t stream);
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uint32_t GetTcMask(uint32_t stream);
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void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream);
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#endif /* DMA_HELPER_H_ */
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110
lib/strutil.c
Normal file
110
lib/strutil.c
Normal file
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#include <stdint.h>
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#include "strutil.h"
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//////////////////////////////////////////////////////////////////////////////
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size_t strcpy_ex(char *dst, char const *src)
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{
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size_t ret = 0;
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do {
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*dst++ = *src;
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++ret;
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} while(*src++);
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return ret - 1;
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}
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//////////////////////////////////////////////////////////////////////////////
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void strrev(char *first, char *last)
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{
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char tmp;
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while(last > first) {
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tmp = *first;
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*first++ = *last;
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*last-- = tmp;
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}
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}
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//////////////////////////////////////////////////////////////////////////////
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char tochr(const uint8_t in, const uint8_t upper)
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{
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return in + ((in < 10) ? '0' : (upper ? 'A' : 'a') - 10);
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}
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//////////////////////////////////////////////////////////////////////////////
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size_t uitodec(char* buffer, uint32_t data)
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{
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char *b2 = buffer;
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if(!data) {
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*b2++ = '0';
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*b2 = '\0';
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return 1;
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}
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while(data) {
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*b2++ = (data % 10) + '0';
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data /= 10;
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}
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size_t ret = b2 - buffer;
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*b2-- = 0;
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strrev(buffer, b2);
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return ret;
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}
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//////////////////////////////////////////////////////////////////////////////
|
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size_t uitohex(char* buffer, uint32_t data, uint8_t chars)
|
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{
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char *b2 = buffer;
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size_t ret = 0;
|
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|
||||
if(chars == 0xff || !chars)
|
||||
{
|
||||
if(!data) {
|
||||
*b2++ = '0';
|
||||
*b2 = '\0';
|
||||
return 1;
|
||||
}
|
||||
|
||||
while(data) {
|
||||
uint8_t curval = data & 0x0f;
|
||||
*b2++ = tochr(curval, 1);
|
||||
data >>= 4;
|
||||
}
|
||||
ret = b2 - buffer;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = chars;
|
||||
for(uint8_t pos = 0; pos < (uint8_t)ret; ++pos) {
|
||||
*b2++ = tochr(data & 0x0f, 1);
|
||||
data >>= 4;
|
||||
}
|
||||
|
||||
}
|
||||
*b2-- = 0;
|
||||
strrev(buffer, b2);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t itodec(char* buffer, int data)
|
||||
{
|
||||
if(data < 0) {
|
||||
*buffer++ = '-';
|
||||
return uitodec(buffer, -data) + 1;
|
||||
}
|
||||
|
||||
return uitodec(buffer, data);
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t itohex(char* buffer, int data)
|
||||
{
|
||||
if(data < 0) {
|
||||
*buffer++ = '-';
|
||||
return uitohex(buffer, -data, 0) + 1;
|
||||
}
|
||||
return uitohex(buffer, data, 0);
|
||||
}
|
31
lib/strutil.h
Normal file
31
lib/strutil.h
Normal file
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* strutil.h
|
||||
*
|
||||
* Created on: Feb 11, 2017
|
||||
* Author: compi
|
||||
*/
|
||||
|
||||
#ifndef _STM32PLUS_STRUTIL_H_
|
||||
#define _STM32PLUS_STRUTIL_H_
|
||||
|
||||
#include <stddef.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t strcpy_ex(char *dst, char const *src);
|
||||
size_t uitodec(char* buffer, uint32_t data);
|
||||
size_t uitohex(char* buffer, uint32_t data, uint8_t chars);
|
||||
size_t itodec(char* buffer, int data);
|
||||
size_t itohex(char* buffer, int data);
|
||||
void strrev(char *first, char *last);
|
||||
char tochr(const uint8_t in, const uint8_t upper);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _STM32PLUS_STRUTIL_H_ */
|
213
lib/usart_handler.c
Normal file
213
lib/usart_handler.c
Normal file
|
@ -0,0 +1,213 @@
|
|||
/*
|
||||
* uart_handler.c
|
||||
*
|
||||
* Created on: Sep 16, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include "globals.h"
|
||||
#include "diag.h"
|
||||
#include "usart_handler.h"
|
||||
#include "dma_helper.h"
|
||||
#include "crc_handler.h"
|
||||
|
||||
#ifndef DIAG_RX_BUFFER_SWITCH
|
||||
# define DIAG_RX_BUFFER_SWITCH(x)
|
||||
#endif
|
||||
|
||||
|
||||
void InitUartStatus(
|
||||
UARTSTATUS *st, USART_TypeDef *uart, DMA_TypeDef *dma,
|
||||
uint32_t stream_rx, uint32_t stream_tx,
|
||||
struct crcstatus_t *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot)
|
||||
{
|
||||
st->uart = uart;
|
||||
InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
|
||||
InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
|
||||
st->txBuffer.busy = 0;
|
||||
st->txBuffer.error = 0;
|
||||
st->txBuffer.requestedLength = 0;
|
||||
st->rxBuffers[0].busy = 0;
|
||||
st->rxBuffers[1].busy = 0;
|
||||
st->rxBuffers[0].error = 0;
|
||||
st->rxBuffers[1].error = 0;
|
||||
st->rxBuffers[0].requestedLength = 0;
|
||||
st->rxBuffers[1].requestedLength = 0;
|
||||
st->rxSerial = -1;
|
||||
st->txSerial = 0;
|
||||
st->activeRxBuf = 0;
|
||||
st->crcStatus = crcStatus;
|
||||
st->txCrcSlot = txCrcSlot;
|
||||
st->rxCrcSlot = rxCrcSlot;
|
||||
memset(&st->stats, 0, sizeof(st->stats));
|
||||
|
||||
LL_DMA_EnableIT_TC(dma, stream_rx);
|
||||
LL_DMA_EnableIT_TE(dma, stream_rx);
|
||||
LL_DMA_EnableIT_TC(dma, stream_tx);
|
||||
LL_DMA_EnableIT_TE(dma, stream_tx);
|
||||
LL_USART_EnableIT_IDLE(uart);
|
||||
}
|
||||
|
||||
static inline void BuildHeader(UARTBUFFER *buffer, uint8_t serial, uint8_t length)
|
||||
{
|
||||
uint8_t hash = STARTMARKER;
|
||||
buffer->packet.header.startByte = STARTMARKER;
|
||||
buffer->packet.header.serial = serial;
|
||||
hash ^= serial;
|
||||
buffer->packet.header.payloadLength = length - 1;
|
||||
hash ^= length - 1;
|
||||
buffer->packet.header.hash = hash;
|
||||
}
|
||||
|
||||
static inline uint8_t CheckHeader(UARTPACKET *packet) {
|
||||
return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
|
||||
}
|
||||
|
||||
|
||||
uint8_t PostPacket(UARTSTATUS *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus)
|
||||
{
|
||||
if(length > 256)
|
||||
return 1;
|
||||
|
||||
BuildHeader(&status->txBuffer, status->txSerial++, length);
|
||||
uint16_t payloadLength = (length+3) & 0xfffc; // round up to 4
|
||||
if(payload)
|
||||
memcpy(status->txBuffer.packet.payload, payload, length);
|
||||
status->txBuffer.requestedLength = sizeof(UARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
|
||||
status->txBuffer.busy = 1;
|
||||
status->txBuffer.error = 0;
|
||||
EnqueueCrcTask(crcStatus, status->txCrcSlot, status->txBuffer.packet.payload, length,
|
||||
NULL, (uint32_t*)(status->txBuffer.packet.payload + payloadLength));
|
||||
while(IsSlotQueued(crcStatus, status->txCrcSlot));
|
||||
SetupTransmit(status->uart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
|
||||
|
||||
StatsIncSent(&status->stats);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void SetupReceive(UARTSTATUS *status)
|
||||
{
|
||||
uint8_t packetIndex = status->activeRxBuf;
|
||||
|
||||
LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->uart), (uint32_t)&status->rxBuffers[packetIndex],
|
||||
LL_DMA_GetDataTransferDirection(status->rxDmaInfo.dma, status->rxDmaInfo.stream));
|
||||
status->rxBuffers[packetIndex].requestedLength = sizeof(status->rxBuffers[packetIndex].packet);
|
||||
LL_DMA_SetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream, status->rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
|
||||
LL_USART_EnableDMAReq_RX(status->uart);
|
||||
LL_USART_ClearFlag_ORE(status->uart);
|
||||
LL_DMA_EnableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
}
|
||||
|
||||
void ConsumePacket(UARTSTATUS *status, uint8_t packetIndex, struct crcstatus_t *crcStatus)
|
||||
{
|
||||
UARTBUFFER *buffer = &status->rxBuffers[packetIndex];
|
||||
if(buffer->busy) {
|
||||
if(buffer->error)
|
||||
StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + ((buffer->packet.header.payloadLength + 1 + 3) & 0xfffc)));
|
||||
else {
|
||||
uint8_t diff = buffer->packet.header.serial - status->rxSerial;
|
||||
if(diff > 1)
|
||||
StatsAddSkiped(&status->stats, diff - 1);
|
||||
status->rxSerial = buffer->packet.header.serial;
|
||||
}
|
||||
}
|
||||
|
||||
buffer->busy = buffer->error = 0;
|
||||
}
|
||||
|
||||
void SetupTransmit(USART_TypeDef *uart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(uart),LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_SetDataLength(dma, stream, length);
|
||||
LL_USART_EnableDMAReq_TX(uart);
|
||||
LL_DMA_EnableStream(dma, stream);
|
||||
}
|
||||
|
||||
void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
|
||||
{
|
||||
UARTBUFFER *ub = (UARTBUFFER*) callbackParm;
|
||||
if(!success)
|
||||
ub->error = 1;
|
||||
else if(*(uint32_t*) (ub->packet.payload + ((ub->packet.header.payloadLength + 1 + 3) & 0xfffc)) == calculatedCrc)
|
||||
ub->busy = 1;
|
||||
else {
|
||||
ub->error = ub->busy = 1;
|
||||
ub->errorInfo = calculatedCrc;
|
||||
}
|
||||
}
|
||||
|
||||
void HandleUsartRxDmaIrq(UARTSTATUS *status)
|
||||
{
|
||||
StatsIncRcvd(&status->stats);
|
||||
if(*status->rxDmaInfo.isReg & status->rxDmaInfo.tcMask) {
|
||||
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.tcMask;
|
||||
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet))
|
||||
EnqueueCrcTask(status->crcStatus, status->rxCrcSlot,
|
||||
status->rxBuffers[status->activeRxBuf].packet.payload,
|
||||
status->rxBuffers[status->activeRxBuf].packet.header.payloadLength +1,
|
||||
RxCrcComputedCallback, &status->rxBuffers[status->activeRxBuf]);
|
||||
else {
|
||||
StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
}
|
||||
} else if(*status->rxDmaInfo.isReg & status->rxDmaInfo.teMask) {
|
||||
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.teMask;
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
}
|
||||
|
||||
status->activeRxBuf ^= 1;
|
||||
|
||||
DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
|
||||
if(status->rxBuffers[status->activeRxBuf].busy)
|
||||
StatsIncOverrun(&status->stats);
|
||||
SetupReceive(status);
|
||||
}
|
||||
|
||||
void HandleUsartTxDmaIrq(UARTSTATUS *status)
|
||||
{
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
|
||||
LL_USART_EnableIT_TC(status->uart);
|
||||
LL_DMA_DisableStream(status->txDmaInfo.dma, status->txDmaInfo.stream);
|
||||
}
|
||||
else if(*status->txDmaInfo.isReg & status->txDmaInfo.teMask) {
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.teMask;
|
||||
status->txBuffer.error = 1;
|
||||
StatsIncDmaError(&status->stats);
|
||||
}
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.feMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.feMask;
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.htMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.htMask;
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.dmeMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.dmeMask;
|
||||
|
||||
}
|
||||
|
||||
void HandleUsartIrq(UARTSTATUS *status)
|
||||
{
|
||||
if(LL_USART_IsActiveFlag_IDLE(status->uart) && LL_USART_IsEnabledIT_IDLE(status->uart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(status->uart);
|
||||
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
if(rcvdLen >= sizeof(UARTPACKETHEADER)) {
|
||||
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
|
||||
if(rcvdLen >= sizeof(UARTPACKETHEADER) + ((status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1 + 3) &0xfffc) + sizeof(uint32_t))
|
||||
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
else
|
||||
StatsIncPremature_payload(&status->stats);
|
||||
} else {
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
}
|
||||
} else
|
||||
StatsIncPremature_hdr(&status->stats);
|
||||
}
|
||||
else if(LL_USART_IsActiveFlag_TC(status->uart) && LL_USART_IsEnabledIT_TC(status->uart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(status->uart);
|
||||
LL_USART_DisableDirectionTx(status->uart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(status->uart);
|
||||
status->txBuffer.busy = 0;
|
||||
}
|
||||
}
|
||||
|
81
lib/usart_handler.h
Normal file
81
lib/usart_handler.h
Normal file
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* uart_handler.h
|
||||
*
|
||||
* Created on: Sep 16, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef UART_HANDLER_H_
|
||||
#define UART_HANDLER_H_
|
||||
#include <inttypes.h>
|
||||
#include <dma.h>
|
||||
#include <stats.h>
|
||||
|
||||
#include "dma_helper.h"
|
||||
#include "crc_handler.h"
|
||||
|
||||
/*
|
||||
* TH UART RXDMA TXDMA
|
||||
* 0 1 D2S5 D2S7
|
||||
* 1 3 D1S1 D1S3
|
||||
* 2 2 D1S5 D1S6
|
||||
* 3 6 D2S2 D2S6
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
uint8_t startByte;
|
||||
uint8_t serial;
|
||||
uint8_t payloadLength;
|
||||
uint8_t hash;
|
||||
} UARTPACKETHEADER;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UARTPACKETHEADER header;
|
||||
//!!! should start on word offset !!!
|
||||
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
|
||||
} __attribute__((aligned)) UARTPACKET;
|
||||
|
||||
typedef struct _UARTBUFFER {
|
||||
UARTPACKET packet;
|
||||
//transfer area ends here
|
||||
volatile uint8_t busy;
|
||||
volatile uint8_t error;
|
||||
uint16_t requestedLength;
|
||||
uint32_t errorInfo;
|
||||
} UARTBUFFER;
|
||||
|
||||
typedef struct {
|
||||
USART_TypeDef *uart;
|
||||
DMAINFO rxDmaInfo;
|
||||
DMAINFO txDmaInfo;
|
||||
struct crcstatus_t *crcStatus;
|
||||
uint8_t rxSerial;
|
||||
uint8_t txSerial;
|
||||
STATS stats;
|
||||
uint8_t activeRxBuf;
|
||||
uint8_t rxCrcSlot;
|
||||
uint8_t txCrcSlot;
|
||||
UARTBUFFER txBuffer;
|
||||
UARTBUFFER rxBuffers[2];
|
||||
} UARTSTATUS;
|
||||
|
||||
#define STARTMARKER 0xa5
|
||||
|
||||
void InitUartStatus(
|
||||
UARTSTATUS *st, USART_TypeDef *uart, DMA_TypeDef *dma,
|
||||
uint32_t stream_rx, uint32_t stream_tx,
|
||||
struct crcstatus_t *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot);
|
||||
static inline uint8_t* GetTxBuffer(UARTSTATUS *status) {
|
||||
return status->txBuffer.packet.payload;
|
||||
}
|
||||
uint8_t PostPacket(UARTSTATUS *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus);
|
||||
void SetupReceive(UARTSTATUS *status);
|
||||
void SetupTransmit(USART_TypeDef *uart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length);
|
||||
void ConsumePacket(UARTSTATUS *status, uint8_t packetIndex, struct crcstatus_t *crcStatus);
|
||||
|
||||
void HandleUsartRxDmaIrq(UARTSTATUS *status);
|
||||
void HandleUsartTxDmaIrq(UARTSTATUS *status);
|
||||
void HandleUsartIrq(UARTSTATUS *status);
|
||||
|
||||
#endif /* UART_HANDLER_H_ */
|
Loading…
Add table
Add a link
Reference in a new issue