Attila BODY
5e44fa81ac
subrepo: subdir: "components/f4ll_c" merged: "7570c78" upstream: origin: "git@git.pcmuhely.hu:compi/f4ll_c.git" branch: "master" commit: "7570c78" git-subrepo: version: "0.4.0" origin: "https://github.com/ingydotnet/git-subrepo" commit: "5d6aba9"
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* memcpy_dma.c
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*
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* Created on: Oct 1, 2019
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* Author: abody
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*/
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#include <f4ll_c/dmahelper.h>
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#include <f4ll_c/memcpydma.h>
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#ifndef DIAG_INTERRUPT_IN
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# define DIAG_INTERRUPT_IN()
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#endif
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#ifndef DIAG_INTERRUPT_OUT
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# define DIAG_INTERRUPT_OUT()
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#endif
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volatile uint8_t g_memcpyDmaBusy = 0;
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static DMAINFO g_memcpyDmaInfo;
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void Mcd_Init(DMA_TypeDef *dma, uint32_t stream)
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{
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Dma_Init(&g_memcpyDmaInfo, dma, stream);
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LL_DMA_EnableIT_TC(dma, stream);
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}
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void * Mcd_Copy(void *dst, void const *src, size_t length)
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{
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LL_DMA_SetM2MSrcAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)src);
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LL_DMA_SetM2MDstAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)dst);
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LL_DMA_SetDataLength(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (length+3)/4 );
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g_memcpyDmaBusy = 1;
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LL_DMA_EnableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
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while(g_memcpyDmaBusy);
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return dst;
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}
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void Mcd_HandleDmaIrq()
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{
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DIAG_INTERRUPT_IN();
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if(*g_memcpyDmaInfo.isReg & g_memcpyDmaInfo.tcMask) { // DMA transfer complete
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*g_memcpyDmaInfo.ifcReg = g_memcpyDmaInfo.tcMask;
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LL_DMA_DisableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
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g_memcpyDmaBusy = 0;
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}
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DIAG_INTERRUPT_OUT();
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}
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