238 lines
17 KiB
C
238 lines
17 KiB
C
#ifndef __PLATFORM_USART_LL_H_INCLUDED
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#define __PLATFORM_USART_LL_H_INCLUDED
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#include <platform/cmsis.h>
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#include <platform/mockme.h>
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typedef struct
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{
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__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
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__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
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__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
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__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
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__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
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__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
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__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
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} USART_TypeDef;
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/*----------- cut here -----------*/
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/******************* Bit definition for USART_SR register *******************/
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#define USART_SR_PE_Pos (0U)
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#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
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#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
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#define USART_SR_FE_Pos (1U)
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#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
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#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
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#define USART_SR_NE_Pos (2U)
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#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
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#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
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#define USART_SR_ORE_Pos (3U)
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#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
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#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
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#define USART_SR_IDLE_Pos (4U)
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#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
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#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
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#define USART_SR_RXNE_Pos (5U)
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#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
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#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
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#define USART_SR_TC_Pos (6U)
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#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
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#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
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#define USART_SR_TXE_Pos (7U)
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#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
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#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
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#define USART_SR_LBD_Pos (8U)
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#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
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#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
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#define USART_SR_CTS_Pos (9U)
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#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
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#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
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/******************* Bit definition for USART_DR register *******************/
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#define USART_DR_DR_Pos (0U)
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#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */
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#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
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/****************** Bit definition for USART_BRR register *******************/
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#define USART_BRR_DIV_Fraction_Pos (0U)
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#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
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#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
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#define USART_BRR_DIV_Mantissa_Pos (4U)
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#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
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#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
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/****************** Bit definition for USART_CR1 register *******************/
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#define USART_CR1_SBK_Pos (0U)
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#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */
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#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
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#define USART_CR1_RWU_Pos (1U)
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#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */
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#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
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#define USART_CR1_RE_Pos (2U)
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#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
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#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
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#define USART_CR1_TE_Pos (3U)
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#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
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#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
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#define USART_CR1_IDLEIE_Pos (4U)
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#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
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#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
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#define USART_CR1_RXNEIE_Pos (5U)
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#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
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#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
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#define USART_CR1_TCIE_Pos (6U)
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#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
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#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
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#define USART_CR1_TXEIE_Pos (7U)
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#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
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#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
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#define USART_CR1_PEIE_Pos (8U)
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#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
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#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
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#define USART_CR1_PS_Pos (9U)
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#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
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#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
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#define USART_CR1_PCE_Pos (10U)
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#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
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#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
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#define USART_CR1_WAKE_Pos (11U)
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#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
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#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
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#define USART_CR1_M_Pos (12U)
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#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
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#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
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#define USART_CR1_UE_Pos (13U)
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#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
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#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
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#define USART_CR1_OVER8_Pos (15U)
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#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
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#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
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/****************** Bit definition for USART_CR2 register *******************/
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#define USART_CR2_ADD_Pos (0U)
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#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */
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#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
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#define USART_CR2_LBDL_Pos (5U)
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#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
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#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
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#define USART_CR2_LBDIE_Pos (6U)
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#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
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#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
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#define USART_CR2_LBCL_Pos (8U)
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#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
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#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
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#define USART_CR2_CPHA_Pos (9U)
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#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
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#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
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#define USART_CR2_CPOL_Pos (10U)
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#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
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#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
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#define USART_CR2_CLKEN_Pos (11U)
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#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
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#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
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#define USART_CR2_STOP_Pos (12U)
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#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
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#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
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#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x1000 */
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#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x2000 */
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#define USART_CR2_LINEN_Pos (14U)
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#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
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#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
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/****************** Bit definition for USART_CR3 register *******************/
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#define USART_CR3_EIE_Pos (0U)
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#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
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#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
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#define USART_CR3_IREN_Pos (1U)
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#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
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#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
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#define USART_CR3_IRLP_Pos (2U)
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#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
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#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
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#define USART_CR3_HDSEL_Pos (3U)
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#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
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#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
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#define USART_CR3_NACK_Pos (4U)
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#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
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#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
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#define USART_CR3_SCEN_Pos (5U)
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#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
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#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
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#define USART_CR3_DMAR_Pos (6U)
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#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
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#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
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#define USART_CR3_DMAT_Pos (7U)
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#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
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#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
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#define USART_CR3_RTSE_Pos (8U)
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#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
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#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
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#define USART_CR3_CTSE_Pos (9U)
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#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
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#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
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#define USART_CR3_CTSIE_Pos (10U)
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#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
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#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
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#define USART_CR3_ONEBIT_Pos (11U)
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#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
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#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
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/****************** Bit definition for USART_GTPR register ******************/
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#define USART_GTPR_PSC_Pos (0U)
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#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
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#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
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#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x0001 */
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#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x0002 */
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#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x0004 */
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#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x0008 */
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#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x0010 */
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#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x0020 */
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#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x0040 */
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#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x0080 */
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#define USART_GTPR_GT_Pos (8U)
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#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
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#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
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/*----------- cut here -----------*/
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extern USART_TypeDef *USART1;
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extern USART_TypeDef *USART2;
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extern USART_TypeDef *USART3;
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extern USART_TypeDef *USART6;
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void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx);
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void LL_USART_EnableIT_TC(USART_TypeDef *USARTx);
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void LL_USART_DisableIT_TC(USART_TypeDef *USARTx);
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uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx);
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uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx);
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void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx);
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void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx);
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uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx);
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uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx);
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uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx);
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void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx);
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void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx);
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void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx);
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void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx);
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DECLARE_MOCK(LL_USART_EnableIT_IDLE);
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DECLARE_MOCK(LL_USART_EnableIT_TC);
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DECLARE_MOCK(LL_USART_DisableIT_TC);
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DECLARE_MOCK(LL_USART_IsEnabledIT_IDLE);
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DECLARE_MOCK(LL_USART_IsEnabledIT_TC);
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DECLARE_MOCK(LL_USART_EnableDMAReq_RX);
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DECLARE_MOCK(LL_USART_EnableDMAReq_TX);
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DECLARE_MOCK(LL_USART_DMA_GetRegAddr);
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DECLARE_MOCK(LL_USART_IsActiveFlag_IDLE);
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DECLARE_MOCK(LL_USART_IsActiveFlag_TC);
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DECLARE_MOCK(LL_USART_ClearFlag_ORE);
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DECLARE_MOCK(LL_USART_ClearFlag_IDLE);
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DECLARE_MOCK(LL_USART_EnableDirectionTx);
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DECLARE_MOCK(LL_USART_DisableDirectionTx);
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//DECLARE_MOCK();
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#endif // __PLATFORM_USART_LL_H_INCLUDED
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