166 lines
6.3 KiB
C
166 lines
6.3 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file dma.c
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* @brief This file provides code for the configuration
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* of all the requested memory to memory DMA transfers.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2025 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "dma.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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/*----------------------------------------------------------------------------*/
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/* Configure DMA */
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/*----------------------------------------------------------------------------*/
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/**
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* Enable DMA controller clock
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*/
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void MX_DMA_Init(void)
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{
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/* Init with LL driver */
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/* DMA controller clock enable */
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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/* Configure DMA request MEMTOMEM_DMA2_Stream4 */
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/* Select channel */
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LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_4, LL_DMA_CHANNEL_0);
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/* Set transfer direction */
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LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_4, LL_DMA_DIRECTION_MEMORY_TO_MEMORY);
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/* Set priority level */
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LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_4, LL_DMA_PRIORITY_LOW);
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/* Set DMA mode */
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LL_DMA_SetMode(DMA2, LL_DMA_STREAM_4, LL_DMA_MODE_NORMAL);
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/* Set peripheral increment mode */
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LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_4, LL_DMA_PERIPH_INCREMENT);
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/* Set memory increment mode */
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LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_4, LL_DMA_MEMORY_NOINCREMENT);
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/* Set peripheral data width */
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LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_4, LL_DMA_PDATAALIGN_WORD);
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/* Set memory data width */
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LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_4, LL_DMA_MDATAALIGN_WORD);
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/* Enable FIFO mode */
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LL_DMA_EnableFifoMode(DMA2, LL_DMA_STREAM_4);
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/* Set FIFO threshold */
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LL_DMA_SetFIFOThreshold(DMA2, LL_DMA_STREAM_4, LL_DMA_FIFOTHRESHOLD_FULL);
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/* Set memory burst size */
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LL_DMA_SetMemoryBurstxfer(DMA2, LL_DMA_STREAM_4, LL_DMA_MBURST_SINGLE);
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/* Set peripheral burst size */
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LL_DMA_SetPeriphBurstxfer(DMA2, LL_DMA_STREAM_4, LL_DMA_PBURST_SINGLE);
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/* Configure DMA request MEMTOMEM_DMA2_Stream3 */
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/* Select channel */
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LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_3, LL_DMA_CHANNEL_0);
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/* Set transfer direction */
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LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_3, LL_DMA_DIRECTION_MEMORY_TO_MEMORY);
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/* Set priority level */
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LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_3, LL_DMA_PRIORITY_LOW);
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/* Set DMA mode */
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LL_DMA_SetMode(DMA2, LL_DMA_STREAM_3, LL_DMA_MODE_NORMAL);
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/* Set peripheral increment mode */
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LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_3, LL_DMA_PERIPH_INCREMENT);
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/* Set memory increment mode */
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LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_3, LL_DMA_MEMORY_INCREMENT);
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/* Set peripheral data width */
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LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_3, LL_DMA_PDATAALIGN_WORD);
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/* Set memory data width */
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LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_3, LL_DMA_MDATAALIGN_WORD);
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/* Enable FIFO mode */
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LL_DMA_EnableFifoMode(DMA2, LL_DMA_STREAM_3);
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/* Set FIFO threshold */
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LL_DMA_SetFIFOThreshold(DMA2, LL_DMA_STREAM_3, LL_DMA_FIFOTHRESHOLD_FULL);
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/* Set memory burst size */
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LL_DMA_SetMemoryBurstxfer(DMA2, LL_DMA_STREAM_3, LL_DMA_MBURST_SINGLE);
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/* Set peripheral burst size */
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LL_DMA_SetPeriphBurstxfer(DMA2, LL_DMA_STREAM_3, LL_DMA_PBURST_SINGLE);
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/* DMA interrupt init */
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/* DMA1_Stream1_IRQn interrupt configuration */
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NVIC_SetPriority(DMA1_Stream1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA1_Stream1_IRQn);
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/* DMA1_Stream2_IRQn interrupt configuration */
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NVIC_SetPriority(DMA1_Stream2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA1_Stream2_IRQn);
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/* DMA1_Stream3_IRQn interrupt configuration */
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NVIC_SetPriority(DMA1_Stream3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA1_Stream3_IRQn);
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/* DMA1_Stream4_IRQn interrupt configuration */
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NVIC_SetPriority(DMA1_Stream4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA1_Stream4_IRQn);
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/* DMA1_Stream5_IRQn interrupt configuration */
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NVIC_SetPriority(DMA1_Stream5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA1_Stream5_IRQn);
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/* DMA1_Stream6_IRQn interrupt configuration */
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NVIC_SetPriority(DMA1_Stream6_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA1_Stream6_IRQn);
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/* DMA2_Stream1_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA2_Stream1_IRQn);
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/* DMA2_Stream2_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA2_Stream2_IRQn);
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/* DMA2_Stream3_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
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NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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/* DMA2_Stream4_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
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NVIC_EnableIRQ(DMA2_Stream4_IRQn);
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/* DMA2_Stream6_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream6_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA2_Stream6_IRQn);
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/* DMA2_Stream7_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA2_Stream7_IRQn);
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}
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/* USER CODE BEGIN 2 */
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/* USER CODE END 2 */
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