git subrepo pull components/f4ll_c
subrepo: subdir: "components/f4ll_c" merged: "3f84137" upstream: origin: "git@git.pcmuhely.hu:compi/f4ll_c.git" branch: "master" commit: "3f84137" git-subrepo: version: "0.4.0" origin: "https://github.com/ingydotnet/git-subrepo" commit: "5d6aba9"
This commit is contained in:
parent
f62880b4fa
commit
fc93297737
3 changed files with 1124 additions and 2 deletions
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@ -6,7 +6,7 @@
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[subrepo]
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remote = git@git.pcmuhely.hu:compi/f4ll_c.git
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branch = master
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commit = 5d26fdc64d86cdbf16d6796c3c51cef3ef05a8dc
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parent = 357b30b34479b3f45b97b60068d7d0fcaa4d98eb
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commit = 3f841370ef21911ef034d622fd98a53463d94b10
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parent = f62880b4fa42f6c72823cb0b247caae481df7077
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method = merge
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cmdver = 0.4.0
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412
components/f4ll_c/test/crcscheduler_unittests.cpp
Normal file
412
components/f4ll_c/test/crcscheduler_unittests.cpp
Normal file
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@ -0,0 +1,412 @@
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/*
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============================================================================
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Name : unittest.c
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Author :
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Version :
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Copyright : Your copyright notice
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Description : Hello World in C, Ansi-style
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============================================================================
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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#include <f4ll_c/crcscheduler.h>
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#include <gtest/gtest.h>
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#include <platform/mockme.h>
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#include <thread>
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#include <future>
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extern "C" void Crc_StartNextTask(struct crcstatus_t *status);
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DMA_TypeDef * DMA1 __attribute__((weak));
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DMA_TypeDef * DMA2 __attribute__((weak));
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static DMA_TypeDef dma1, dma2;
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static crcstatus_t crcStatus;
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static crcslotlistitem_t slot1, slot2;
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static crcslottask_t tasks1[2], tasks2[2];
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static CRC_TypeDef fakeCrc;
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static DMA_TypeDef *expectedDma;
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static uint32_t expectedStream;
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static uint32_t expectedSrcAddress;
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static uint32_t expectedDstAddress;
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static uint32_t expectedLength;
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static void *expectedCustomPtr;
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static uint8_t expectedSuccess;
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static uint32_t expectedCrc;
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//////////////////////////////////////////////////////////////////////////////
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DEFINE_MOCK_RET(uint32_t, __get_PRIMASK, mock) {
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RETURN_MOCK_PREDEF(__get_PRIMASK, mock);
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}
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DEFINE_MOCK_VAR(uint32_t, __set_PRIMASK, mock, lastprimask);
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DEFINE_MOCK(__set_PRIMASK, mock, uint32_t primask) {
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MOCK_STORE(__set_PRIMASK, mock, lastprimask, primask);
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LEAVE_MOCK;
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}
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DEFINE_MOCK_VAR(crcslotlistitem_t *, __disable_irq, mock, compare);
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DEFINE_MOCK(__disable_irq, mock) {
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if(!MOCK_VAR(__disable_irq, mock, callcount)) {
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EXPECT_EQ(crcStatus.firstSlot, MOCK_VAR(__disable_irq, mock, compare));
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}
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LEAVE_MOCK;
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}
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DEFINE_MOCK(LL_DMA_EnableIT_TC, mock, DMA_TypeDef *dma, uint32_t stream) {
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EXPECT_EQ(expectedDma, dma);
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EXPECT_EQ(expectedStream, stream);
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LEAVE_MOCK;
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}
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DEFINE_MOCK(LL_DMA_EnableIT_TE, mock, DMA_TypeDef *dma, uint32_t stream) {
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EXPECT_EQ(expectedDma, dma);
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EXPECT_EQ(expectedStream, stream);
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LEAVE_MOCK;
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}
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DEFINE_MOCK(LL_DMA_SetM2MDstAddress, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t address) {
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EXPECT_EQ(expectedDma, dma);
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EXPECT_EQ(expectedStream, stream);
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EXPECT_EQ(expectedDstAddress, address);
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LEAVE_MOCK;
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}
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DEFINE_MOCK(LL_DMA_SetM2MSrcAddress, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t address) {
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EXPECT_EQ(expectedDma, dma);
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EXPECT_EQ(expectedStream, stream);
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EXPECT_EQ(expectedSrcAddress, address);
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LEAVE_MOCK;
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}
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DEFINE_MOCK(LL_DMA_SetDataLength, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t length) {
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EXPECT_EQ(expectedDma, dma);
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EXPECT_EQ(expectedStream, stream);
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EXPECT_EQ(expectedLength, length);
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LEAVE_MOCK;
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}
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DEFINE_MOCK(LL_DMA_EnableStream, mock, DMA_TypeDef *dma, uint32_t stream)
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{
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EXPECT_EQ(expectedDma, dma);
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EXPECT_EQ(expectedStream, stream);
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LEAVE_MOCK;
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}
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DEFINE_MOCK(LL_DMA_DisableStream, mock, DMA_TypeDef *dma, uint32_t stream)
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{
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EXPECT_EQ(expectedDma, dma);
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EXPECT_EQ(expectedStream, stream);
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LEAVE_MOCK;
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}
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DEFINE_MOCK(Crc_StartNextTask, mock, struct crcstatus_t *status)
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{
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EXPECT_EQ(status, &crcStatus);
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LEAVE_MOCK
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}
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void FakeCallback_1(void*, uint32_t, uint8_t) {}
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void FakeCallback_2(void*, uint32_t, uint8_t) {}
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void FakeCallback_3(void*, uint32_t, uint8_t) {}
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void FakeCallbackCheck(void* ptr, uint32_t crc, uint8_t success)
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{
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EXPECT_EQ(ptr, expectedCustomPtr);
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EXPECT_EQ(crc, expectedCrc);
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EXPECT_EQ(success, expectedSuccess);
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}
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DEFINE_MOCK(Dma_Init, mock, struct dmainfo_t * info, DMA_TypeDef *dma, uint32_t stream)
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{
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LEAVE_MOCK;
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}
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//////////////////////////////////////////////////////////////////////////////
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TEST(CrcScheduler, InitStatus)
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{
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expectedDma = DMA2;
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expectedStream = LL_DMA_STREAM_4;
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expectedDstAddress = (uint32_t)&fakeCrc;
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memset(&crcStatus, 0xff, sizeof(crcStatus));
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ACTIVATE_MOCK(LL_DMA_EnableIT_TC, mock);
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ACTIVATE_MOCK(LL_DMA_EnableIT_TE, mock);
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ACTIVATE_MOCK(LL_DMA_SetM2MDstAddress, mock);
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ACTIVATE_MOCK(Dma_Init, mock);
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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EXPECT_EQ(crcStatus.crcUnit, &fakeCrc);
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EXPECT_EQ(crcStatus.activeSlot, nullptr);
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EXPECT_EQ(crcStatus.firstSlot, nullptr);
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EXPECT_EQ(MOCK_VAR(Dma_Init, mock, callcount), 1);
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}
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TEST(CrcScheduler, AttachTask_single)
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{
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ACTIVATE_MOCK_RV(__get_PRIMASK, mock, 1);
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ACTIVATE_MOCK(__set_PRIMASK, mock);
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ACTIVATE_MOCK(__disable_irq, mock);
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MOCK_STORE(__disable_irq, mock, compare, nullptr);
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DMA1 = &dma1;
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DMA2 = &dma2;
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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EXPECT_EQ(MOCK_VAR(__get_PRIMASK, mock, callcount), 1);
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EXPECT_EQ(MOCK_VAR(__set_PRIMASK, mock, callcount), 1);
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EXPECT_EQ(MOCK_VAR(__disable_irq, mock, callcount), 1);
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EXPECT_EQ(crcStatus.firstSlot, &slot1);
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EXPECT_EQ(slot1.next, nullptr);
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EXPECT_EQ(slot1.count, 2);
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EXPECT_EQ(crcStatus.activeSlot, nullptr);
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}
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TEST(CrcScheduler, AttachTask_multiple)
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{
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ACTIVATE_MOCK_RV(__get_PRIMASK, mock, 1);
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ACTIVATE_MOCK(__set_PRIMASK, mock);
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ACTIVATE_MOCK(__disable_irq, mock);
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MOCK_STORE(__disable_irq, mock, compare, nullptr);
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DMA1 = &dma1;
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DMA2 = &dma2;
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Crc_InitStatus(&crcStatus, NULL, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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MOCK_STORE(__disable_irq, mock, compare, &slot1);
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Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
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EXPECT_EQ(__get_PRIMASK_mock_callcount, 2);
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EXPECT_EQ(__set_PRIMASK_mock_callcount, 2);
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EXPECT_EQ(__disable_irq_mock_callcount, 2);
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EXPECT_EQ(crcStatus.firstSlot, &slot2);
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EXPECT_EQ(slot2.next, &slot1);
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EXPECT_EQ(slot1.next, nullptr);
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EXPECT_EQ(slot2.count, 2);
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EXPECT_EQ(crcStatus.activeSlot, nullptr);
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}
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TEST(CrcScheduler, Enqueue_nowait)
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{
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uint32_t fakeCrcResult;
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uint8_t testData[] = "qwerty";
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expectedDma = DMA2;
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expectedStream = LL_DMA_STREAM_4;
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expectedSrcAddress = (uint32_t)testData;
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memset(tasks1, 0, sizeof(tasks1));
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memset(&fakeCrc, 0, sizeof(fakeCrc));
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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expectedLength = 2;
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ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
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ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
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ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
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EXPECT_TRUE(Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult));
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//first task should be picked up before return;
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EXPECT_EQ(slot1.tasks[0].address, nullptr);
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EXPECT_EQ((uintptr_t)slot1.tasks[0].callback, (uintptr_t)FakeCallback_1);
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EXPECT_EQ(MOCK_VAR(LL_DMA_SetM2MSrcAddress, mock, callcount), 1);
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EXPECT_EQ(MOCK_VAR(LL_DMA_SetDataLength, mock, callcount), 1);
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EXPECT_EQ(MOCK_VAR(LL_DMA_EnableStream, mock, callcount), 1);
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EXPECT_FALSE(Crc_Enqueue(&crcStatus, &slot1, 1, testData, 4, FakeCallback_1, &fakeCrcResult));
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// second task should be queued
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EXPECT_EQ(slot1.tasks[1].address, testData);
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EXPECT_EQ((uintptr_t)slot1.tasks[1].callback, (uintptr_t)FakeCallback_1);
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EXPECT_EQ(slot1.tasks[1].wordCount, 1);
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// should be no new calls to hardware handling functions
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EXPECT_EQ(MOCK_VAR(LL_DMA_SetM2MSrcAddress, mock, callcount), 1);
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EXPECT_EQ(MOCK_VAR(LL_DMA_SetDataLength, mock, callcount), 1);
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EXPECT_EQ(MOCK_VAR(LL_DMA_EnableStream, mock, callcount), 1);
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}
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TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
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{
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uint8_t testData[] = "qwerty";
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uint32_t fakeCrcResult;
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memset(tasks1, 0, sizeof(tasks1));
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memset(&fakeCrc, 0, sizeof(fakeCrc));
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult);
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// black magic to test if the function blocks (at least for 100ms)
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std::promise<bool> promisedFinished;
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auto futureResult = promisedFinished.get_future();
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pthread_t th;
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std::thread t([&testData](std::promise<bool>& finished) {
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pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS,NULL);
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Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, nullptr);
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finished.set_value(true);
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}, std::ref(promisedFinished));
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th = t.native_handle();
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t.detach();
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EXPECT_EQ(futureResult.wait_for(std::chrono::milliseconds(100)), std::future_status::timeout);
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tasks1[0].callback = nullptr;
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tasks1[0].callbackParam = nullptr;
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auto waitResult(futureResult.wait_for(std::chrono::milliseconds(100)));
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EXPECT_NE(waitResult, std::future_status::timeout);
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if(waitResult == std::future_status::timeout)
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pthread_cancel(th);
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}
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TEST(CrcScheduler, Crc_StartNextTask)
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{
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uint8_t testData[] = "qwerty";
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uint32_t fakeCrcResult1, fakeCrcResult2, fakeCrcResult3;
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memset(tasks1, 0, sizeof(tasks1));
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memset(tasks2, 0, sizeof(tasks2));
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memset(&fakeCrc, 0, sizeof(fakeCrc));
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
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Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult1);
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Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_2, &fakeCrcResult2);
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Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallback_3, &fakeCrcResult3);
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EXPECT_EQ(crcStatus.activeSlot, &slot1);
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EXPECT_EQ(crcStatus.activeTask, 0);
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crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
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crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
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ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
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ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
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ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
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expectedDma = DMA2;
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expectedStream = LL_DMA_STREAM_4;
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expectedSrcAddress = (uint32_t)testData;
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expectedLength = (sizeof(testData) + 3) / 4;
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Crc_StartNextTask(&crcStatus);
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EXPECT_EQ(crcStatus.activeSlot, &slot2);
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EXPECT_EQ(crcStatus.activeTask, 0);
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EXPECT_EQ(LL_DMA_SetM2MSrcAddress_mock_callcount, 1);
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EXPECT_EQ(LL_DMA_SetDataLength_mock_callcount, 1);
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EXPECT_EQ(LL_DMA_EnableStream_mock_callcount, 1);
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crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
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crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
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Crc_StartNextTask(&crcStatus);
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EXPECT_EQ(crcStatus.activeSlot, &slot1);
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EXPECT_EQ(crcStatus.activeTask, 1);
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EXPECT_EQ(LL_DMA_SetM2MSrcAddress_mock_callcount, 2);
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EXPECT_EQ(LL_DMA_SetDataLength_mock_callcount, 2);
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EXPECT_EQ(LL_DMA_EnableStream_mock_callcount, 2);
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}
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TEST(CrcScheduler, HandleDmaIrq_callback)
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{
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uint8_t testData[] = "qwerty";
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uint32_t FakeCustomData1, FakeCustomData2;
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memset(tasks1, 0, sizeof(tasks1));
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memset(tasks2, 0, sizeof(tasks2));
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memset(&fakeCrc, 0, sizeof(fakeCrc));
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fakeCrc.DR = 0xa5a55a5a;
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
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Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData1);
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// we need to set this up here to check if HandleDmaIrq calls Crc_StartNextTask or not;
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Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData2);
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ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
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ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
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ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
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ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
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ACTIVATE_MOCK(Crc_StartNextTask, mock);
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expectedDma = DMA2;
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expectedStream = LL_DMA_STREAM_4;
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expectedCustomPtr = &FakeCustomData1;
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expectedCrc = fakeCrc.DR;
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expectedSuccess = 1;
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DMA2->HISR |= DMA_HISR_TCIF4;
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DMA2->HIFCR = 0;
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Crc_HandleDmaIrq(&crcStatus);
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EXPECT_EQ(LL_DMA_DisableStream_mock_callcount, 1);
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EXPECT_EQ(DMA2->HIFCR & DMA_HIFCR_CTCIF4, DMA_HIFCR_CTCIF4);
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expectedCustomPtr = &FakeCustomData2;
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DMA2->HISR |= DMA_HISR_TCIF4 | DMA_HISR_TEIF4;
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DMA2->HIFCR = 0;
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crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
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crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
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Crc_HandleDmaIrq(&crcStatus);
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EXPECT_EQ(DMA2->HIFCR & (DMA_HIFCR_CTCIF4 | DMA_HIFCR_CTEIF4), DMA_HIFCR_CTCIF4 | DMA_HIFCR_CTEIF4);
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EXPECT_EQ(LL_DMA_DisableStream_mock_callcount, 2);
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}
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TEST(CrcScheduler, IsSlotQueued)
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{
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uint8_t testData[] = "qwerty";
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uint32_t FakeCustomData1;
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
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Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
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EXPECT_EQ(Crc_IsSlotQueued(&slot1, 0), 0);
|
||||
EXPECT_NE(Crc_IsSlotQueued(&slot1, 1), 0);
|
||||
|
||||
Crc_StartNextTask(&crcStatus);
|
||||
|
||||
EXPECT_EQ(Crc_IsSlotQueued(&slot1, 1), 0);
|
||||
}
|
||||
|
||||
TEST(CrcScheduler, IsSlotBusy)
|
||||
{
|
||||
uint8_t testData[] = "qwerty";
|
||||
uint32_t FakeCustomData1;
|
||||
|
||||
Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
|
||||
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
|
||||
Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
|
||||
Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
|
||||
|
||||
EXPECT_NE(Crc_IsSlotBusy(&slot1, 0), 0);
|
||||
EXPECT_NE(Crc_IsSlotBusy(&slot1, 1), 0);
|
||||
|
||||
DMA2->HISR |= DMA_HISR_TCIF4;
|
||||
Crc_HandleDmaIrq(&crcStatus);
|
||||
|
||||
EXPECT_EQ(Crc_IsSlotBusy(&slot1, 0), 0);
|
||||
EXPECT_NE(Crc_IsSlotBusy(&slot1, 1), 0);
|
||||
|
||||
DMA2->HISR |= DMA_HISR_TCIF4;
|
||||
Crc_HandleDmaIrq(&crcStatus);
|
||||
|
||||
EXPECT_EQ(Crc_IsSlotBusy(&slot1, 0), 0);
|
||||
EXPECT_EQ(Crc_IsSlotBusy(&slot1, 1), 0);
|
||||
}
|
||||
710
components/f4ll_c/test/packetusart_unittest.cpp
Normal file
710
components/f4ll_c/test/packetusart_unittest.cpp
Normal file
|
|
@ -0,0 +1,710 @@
|
|||
/*
|
||||
* packetusart_unittest.cpp
|
||||
*
|
||||
* Created on: Dec 2, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include <stdlib.h>
|
||||
#include <inttypes.h>
|
||||
#include <platform/usart_ll.h>
|
||||
#include <f4ll_c/packetusart.h>
|
||||
#include <gtest/gtest.h>
|
||||
#include <platform/mockme.h>
|
||||
#include <thread>
|
||||
#include <future>
|
||||
|
||||
static inline uint32_t RoundUpTo4(uint32_t inp)
|
||||
{
|
||||
return (inp + 3) & 0xfffc;
|
||||
}
|
||||
|
||||
DMA_TypeDef* DMA1 __attribute__((weak));
|
||||
DMA_TypeDef* DMA2 __attribute__((weak));
|
||||
|
||||
static DMA_TypeDef fakeDma1, fakeDma2;
|
||||
static CRC_TypeDef fakeCrc;
|
||||
static USART_TypeDef fakeUsart;
|
||||
|
||||
static struct usartstatus_t usartStatus;
|
||||
static struct crcstatus_t crcStatus;
|
||||
|
||||
uint8_t testData[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
|
||||
|
||||
//static uint32_t expected_stream;
|
||||
//static uint32_t expected_srcaddress;
|
||||
//static uint32_t expected_dstaddress;
|
||||
//static uint32_t expected_length;
|
||||
//static void *expected_customptr;
|
||||
//static uint8_t expected_success;
|
||||
//static struct usartstatus_t * expectedUsartStatus;
|
||||
static uint32_t expectedStreams[2] = { 0,7 };
|
||||
struct crcstatus_t *expectedCrcStatus;
|
||||
struct crcslotlistitem_t *expectedCrcSlotListItem;
|
||||
struct crcslottask_t *expectedTasks;
|
||||
uint8_t expectedTaskCount;
|
||||
uint32_t expectedCrcLength;
|
||||
uint32_t expectedLength;
|
||||
void* expectedCrcEnqueueAddress;
|
||||
void *expectedTransmitBuffer;
|
||||
|
||||
static uint32_t expectedStream;
|
||||
uint32_t expectedSrcAddress;
|
||||
uint32_t expectedDstAddress;
|
||||
uint32_t expectedDirection;
|
||||
|
||||
uint32_t fakePacketReceivedCallbackParam;
|
||||
|
||||
|
||||
DEFINE_MOCK(FakePacketReceivedCallback, mock, void* userParam, struct usart_buffer_t *buffer)
|
||||
{
|
||||
EXPECT_EQ((void*)&fakePacketReceivedCallbackParam, userParam);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(Dma_Init, mock, struct dmainfo_t* dmaInfo, DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
Dma_Init__(dmaInfo, dma, stream);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(Crc_AttachTask, mock, struct crcstatus_t *status, struct crcslotlistitem_t *slot, struct crcslottask_t *tasks, uint8_t taskCount)
|
||||
{
|
||||
EXPECT_EQ(status, expectedCrcStatus);
|
||||
EXPECT_EQ(slot, expectedCrcSlotListItem);
|
||||
EXPECT_EQ(tasks, expectedTasks);
|
||||
EXPECT_EQ(taskCount, expectedTaskCount);
|
||||
Crc_AttachTask__(status, slot, tasks, taskCount);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_DMA_EnableIT_TC, init, DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
EXPECT_EQ(dma, &fakeDma1);
|
||||
EXPECT_EQ(stream, expectedStreams[MOCK_VAR(LL_DMA_EnableIT_TC, init, callcount)-1]);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_DMA_EnableIT_TE, init, DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
EXPECT_EQ(dma, &fakeDma1);
|
||||
EXPECT_EQ(stream, expectedStreams[MOCK_VAR(LL_DMA_EnableIT_TE, init, callcount)-1]);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint32_t, LL_USART_DMA_GetRegAddr, mock, USART_TypeDef *usart)
|
||||
{
|
||||
RETURN_MOCK_PREDEF(LL_USART_DMA_GetRegAddr, mock)
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_DMA_ConfigAddresses, mock, DMA_TypeDef* dma, uint32_t stream, uint32_t srcAddress, uint32_t dstAddress, uint32_t direction)
|
||||
{
|
||||
EXPECT_EQ(dma, &fakeDma1);
|
||||
EXPECT_EQ(stream, expectedStream);
|
||||
EXPECT_EQ(srcAddress, expectedSrcAddress);
|
||||
EXPECT_EQ(dstAddress, expectedDstAddress);
|
||||
EXPECT_EQ(direction, expectedDirection);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_DMA_SetDataLength, mock, DMA_TypeDef* dma, uint32_t stream, uint32_t length)
|
||||
{
|
||||
EXPECT_EQ(dma, &fakeDma1);
|
||||
EXPECT_EQ(stream, expectedStream);
|
||||
EXPECT_EQ(length, expectedLength);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint32_t, LL_DMA_GetDataLength, mock, DMA_TypeDef* dma, uint32_t stream)
|
||||
{
|
||||
EXPECT_EQ(dma, &fakeDma1);
|
||||
EXPECT_EQ(stream, expectedStream);
|
||||
RETURN_MOCK_PREDEF(LL_DMA_GetDataLength, mock)
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_DMA_EnableStream, mock, DMA_TypeDef* dma, uint32_t stream)
|
||||
{
|
||||
EXPECT_EQ(dma, &fakeDma1);
|
||||
EXPECT_EQ(stream, expectedStream);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_DMA_DisableStream, mock, DMA_TypeDef* dma, uint32_t stream)
|
||||
{
|
||||
EXPECT_EQ(dma, &fakeDma1);
|
||||
EXPECT_EQ(stream, expectedStream);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_EnableDMAReq_TX, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_EnableDMAReq_RX, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_EnableIT_IDLE, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_EnableIT_TC, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_DisableIT_TC, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint32_t, LL_USART_IsActiveFlag_IDLE, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
RETURN_MOCK_PREDEF(LL_USART_IsActiveFlag_IDLE, mock)
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint32_t, LL_USART_IsActiveFlag_TC, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
RETURN_MOCK_PREDEF(LL_USART_IsActiveFlag_TC, mock)
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_ClearFlag_IDLE, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK;
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint32_t, LL_USART_IsEnabledIT_IDLE, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
RETURN_MOCK_PREDEF(LL_USART_IsEnabledIT_IDLE, mock)
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint32_t, LL_USART_IsEnabledIT_TC, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
RETURN_MOCK_PREDEF(LL_USART_IsEnabledIT_TC, mock)
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_EnableDirectionTx, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_DisableDirectionTx, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK(LL_USART_ClearFlag_ORE, mock, USART_TypeDef *usart)
|
||||
{
|
||||
EXPECT_EQ(usart, &fakeUsart);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint8_t, Crc_Enqueue, mock, struct crcstatus_t *status, struct crcslotlistitem_t *slot, uint8_t task,
|
||||
void *address, uint16_t len, void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
|
||||
{
|
||||
EXPECT_EQ(expectedCrcLength, len);
|
||||
EXPECT_EQ(expectedCrcEnqueueAddress, address);
|
||||
RETURN_MOCK_PREDEF(Crc_Enqueue, mock);
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint8_t, Crc_IsSlotQueued, mock, struct crcslotlistitem_t *slot, uint8_t task)
|
||||
{
|
||||
RETURN_MOCK_PREDEF(Crc_IsSlotQueued, mock);
|
||||
}
|
||||
|
||||
DEFINE_MOCK(Pu_SetupTransmit, mock, USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
|
||||
{
|
||||
EXPECT_EQ(buffer, expectedTransmitBuffer);
|
||||
EXPECT_EQ(length, expectedLength);
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
DEFINE_MOCK_RET(uint8_t, Pu_CheckHeader, proxy, struct usartpacket_t *packet)
|
||||
{
|
||||
RETURN_MOCK(Pu_CheckHeader, proxy, Pu_CheckHeader__(packet));
|
||||
}
|
||||
|
||||
DEFINE_MOCK(Pu_SetupReceive, mock, struct usartstatus_t *status)
|
||||
{
|
||||
LEAVE_MOCK
|
||||
}
|
||||
|
||||
struct PacketUsart : public ::testing::Test {
|
||||
void SetUp()
|
||||
{
|
||||
DMA1 = &fakeDma1;
|
||||
DMA2 = &fakeDma2;
|
||||
|
||||
memset(&usartStatus, 0x5a, sizeof(usartStatus));
|
||||
Crc_InitStatus(&crcStatus, &fakeCrc, &fakeDma2, 4);
|
||||
|
||||
expectedCrcStatus = &crcStatus;
|
||||
expectedCrcSlotListItem = &usartStatus.crcSlot;
|
||||
expectedTasks = usartStatus.crcTasks;
|
||||
expectedTaskCount = 2;
|
||||
}
|
||||
};
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
TEST_F(PacketUsart, Init)
|
||||
{
|
||||
ACTIVATE_MOCK(Dma_Init, mock);
|
||||
ACTIVATE_MOCK(Crc_AttachTask, mock);
|
||||
ACTIVATE_MOCK(LL_DMA_EnableIT_TC, init);
|
||||
ACTIVATE_MOCK(LL_DMA_EnableIT_TE, init);
|
||||
ACTIVATE_MOCK(LL_USART_EnableIT_IDLE, mock);
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
|
||||
EXPECT_EQ(fakeDma1.LIFCR, DMA_LISR_TCIF0 | DMA_LISR_HTIF0 | DMA_LISR_TEIF0 | DMA_LISR_FEIF0 | DMA_LISR_DMEIF0);
|
||||
EXPECT_EQ(fakeDma1.HIFCR, DMA_HISR_TCIF7 | DMA_HISR_HTIF7 | DMA_HISR_TEIF7 | DMA_HISR_FEIF7 | DMA_HISR_DMEIF7);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Dma_Init, mock), 2);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableIT_TC, init), 2);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableIT_TE, init), 2);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_IDLE, mock), 1);
|
||||
EXPECT_EQ(usartStatus.usart, &fakeUsart);
|
||||
EXPECT_EQ(usartStatus.txBuffer.usartStatus, &usartStatus);
|
||||
EXPECT_EQ(usartStatus.txBuffer.busy, 0);
|
||||
EXPECT_EQ(usartStatus.txBuffer.error, 0);
|
||||
EXPECT_EQ(usartStatus.txBuffer.requestedLength, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].requestedLength, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].usartStatus, &usartStatus );
|
||||
EXPECT_EQ(usartStatus.rxBuffers[1].busy, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[1].error, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[1].requestedLength, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[1].usartStatus, &usartStatus );
|
||||
EXPECT_TRUE(usartStatus.packetReceivedCallback == FakePacketReceivedCallback_mock);
|
||||
EXPECT_EQ(usartStatus.packetReceivedCallbackParam, &fakePacketReceivedCallbackParam);
|
||||
EXPECT_EQ(usartStatus.rxSerial, (uint8_t)-1);
|
||||
EXPECT_EQ(usartStatus.txSerial, 0);
|
||||
EXPECT_EQ(usartStatus.activeRxBuf, 0);
|
||||
EXPECT_EQ(usartStatus.crcStatus, &crcStatus);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, GetTxBuffer)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
EXPECT_EQ(Pu_GetTxBuffer(&usartStatus), (unsigned char*)&usartStatus.txBuffer.packet.payload);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, SetupTransmit)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
expectedStream = 7;
|
||||
expectedSrcAddress = (uint32_t)testData;
|
||||
expectedDstAddress = (uint32_t)&fakeUsart.DR;
|
||||
expectedDirection = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
|
||||
expectedLength = sizeof(testData);
|
||||
|
||||
ACTIVATE_MOCK(LL_DMA_ConfigAddresses, mock);
|
||||
ACTIVATE_MOCK(LL_DMA_SetDataLength , mock);
|
||||
ACTIVATE_MOCK(LL_DMA_EnableStream , mock);
|
||||
ACTIVATE_MOCK(LL_USART_EnableDMAReq_TX, mock);
|
||||
ACTIVATE_MOCK_RV(LL_USART_DMA_GetRegAddr, mock, expectedDstAddress);
|
||||
|
||||
Pu_SetupTransmit(&fakeUsart, &fakeDma1, 7, testData, sizeof(testData));
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, Post_copy_nowait)
|
||||
{
|
||||
struct usartpacketheader_t expectedHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
|
||||
expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
|
||||
expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
|
||||
expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
|
||||
expectedTransmitBuffer = &usartStatus.txBuffer.packet;
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
|
||||
ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
|
||||
ACTIVATE_MOCK(Pu_SetupTransmit, mock);
|
||||
ACTIVATE_MOCK_RV(Crc_IsSlotQueued, mock, 1);
|
||||
|
||||
Pu_Post(&usartStatus, testData, sizeof(testData), &crcStatus, false);
|
||||
|
||||
EXPECT_EQ(usartStatus.txBuffer.busy, 1);
|
||||
EXPECT_EQ(usartStatus.txBuffer.requestedLength, expectedLength);
|
||||
EXPECT_EQ(memcmp(&usartStatus.txBuffer.packet.header, &expectedHeader, sizeof(expectedHeader)), 0);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Crc_Enqueue, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Pu_SetupTransmit, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Crc_IsSlotQueued, mock), 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, Post_copy_wait_nodelay)
|
||||
{
|
||||
expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
|
||||
expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
|
||||
expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
|
||||
expectedTransmitBuffer = &usartStatus.txBuffer.packet;
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
|
||||
ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
|
||||
ACTIVATE_MOCK(Pu_SetupTransmit, mock);
|
||||
ACTIVATE_MOCK_RV(Crc_IsSlotQueued, mock, 0);
|
||||
|
||||
Pu_Post(&usartStatus, testData, sizeof(testData), &crcStatus, true);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Crc_IsSlotQueued, mock), 1);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, Post_copy_wait_delay)
|
||||
{
|
||||
expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
|
||||
expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
|
||||
expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
|
||||
expectedTransmitBuffer = &usartStatus.txBuffer.packet;
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
|
||||
ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
|
||||
ACTIVATE_MOCK(Pu_SetupTransmit, mock);
|
||||
ACTIVATE_MOCK_RV(Crc_IsSlotQueued, mock, 1);
|
||||
|
||||
// black magic to test if the function blocks (at least for 100ms)
|
||||
std::promise<bool> promiseFinished;
|
||||
auto futureResult = promiseFinished.get_future();
|
||||
pthread_t th;
|
||||
std::thread t([](std::promise<bool>& finished) {
|
||||
pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS,NULL);
|
||||
Pu_Post(&usartStatus, testData, sizeof(testData), &crcStatus, true);;
|
||||
finished.set_value(true);
|
||||
}, std::ref(promiseFinished));
|
||||
th = t.native_handle();
|
||||
t.detach();
|
||||
EXPECT_EQ(futureResult.wait_for(std::chrono::milliseconds(100)), std::future_status::timeout);
|
||||
Crc_IsSlotQueued_mock_retval = 0;
|
||||
auto waitResult(futureResult.wait_for(std::chrono::milliseconds(100)));
|
||||
EXPECT_NE(waitResult, std::future_status::timeout);
|
||||
if(waitResult == std::future_status::timeout)
|
||||
pthread_cancel(th);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleTxDmaIrq_tc)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_Post(&usartStatus, testData, sizeof(testData), &crcStatus, true);
|
||||
|
||||
memset(&fakeDma1, 0, sizeof(fakeDma1));
|
||||
fakeDma1.HISR = DMA_HISR_TCIF7;
|
||||
expectedStream = 7;
|
||||
|
||||
ACTIVATE_MOCK(LL_USART_EnableIT_TC, mock);
|
||||
ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
|
||||
|
||||
Pu_HandleTxDmaIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_TC, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
|
||||
EXPECT_EQ(fakeDma1.HIFCR, DMA_HIFCR_CTCIF7);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleTxDmaIrq_te)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_Post(&usartStatus, testData, sizeof(testData), &crcStatus, true);
|
||||
|
||||
memset(&fakeDma1, 0, sizeof(fakeDma1));
|
||||
fakeDma1.HISR = DMA_HISR_TEIF7;
|
||||
expectedStream = 7;
|
||||
|
||||
Pu_HandleTxDmaIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_TC, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
|
||||
EXPECT_EQ(fakeDma1.HIFCR, DMA_HIFCR_CTEIF7);
|
||||
EXPECT_EQ(usartStatus.txBuffer.error, 1);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleUsartIrq_tc)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_Post(&usartStatus, testData, sizeof(testData), &crcStatus, true);
|
||||
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 0);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
|
||||
ACTIVATE_MOCK(LL_USART_DisableIT_TC, mock);
|
||||
ACTIVATE_MOCK(LL_USART_EnableDirectionTx, mock);
|
||||
ACTIVATE_MOCK(LL_USART_DisableDirectionTx, mock);
|
||||
|
||||
Pu_HandleUsartIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DisableIT_TC, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DisableDirectionTx, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableDirectionTx, mock), 1);
|
||||
EXPECT_EQ(usartStatus.txBuffer.busy, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, setupReceive)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
expectedStream = 0;
|
||||
expectedDstAddress = (uint32_t)&usartStatus.rxBuffers[usartStatus.activeRxBuf].packet;
|
||||
expectedSrcAddress = (uint32_t)&fakeUsart.DR;
|
||||
expectedDirection = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
|
||||
expectedLength = sizeof(struct usartpacket_t);
|
||||
|
||||
ACTIVATE_MOCK(LL_DMA_ConfigAddresses, mock);
|
||||
ACTIVATE_MOCK(LL_DMA_SetDataLength , mock);
|
||||
ACTIVATE_MOCK(LL_DMA_EnableStream , mock);
|
||||
ACTIVATE_MOCK(LL_USART_EnableDMAReq_RX, mock);
|
||||
ACTIVATE_MOCK(LL_USART_ClearFlag_ORE, mock);
|
||||
|
||||
ACTIVATE_MOCK_RV(LL_USART_DMA_GetRegAddr, mock, expectedSrcAddress);
|
||||
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_ConfigAddresses, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_SetDataLength, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableStream, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableDMAReq_RX, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_ORE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DMA_GetRegAddr, mock), 1);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleUsartIrq_idle_fullpacket_hdr_ok)
|
||||
{
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
expectedStream = 0;
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
|
||||
ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
|
||||
ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t));
|
||||
ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
|
||||
ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
|
||||
|
||||
Pu_HandleUsartIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleUsartIrq_idle_fullpacket_hdr_bad)
|
||||
{
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
expectedStream = 0;
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
|
||||
ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
|
||||
ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t));
|
||||
ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
|
||||
ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
|
||||
|
||||
Pu_HandleUsartIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
|
||||
EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
|
||||
EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleUsartIrq_idle_tooshort)
|
||||
{
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
expectedStream = 0;
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
|
||||
ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
|
||||
ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t) + 1);
|
||||
ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
|
||||
ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
|
||||
|
||||
Pu_HandleUsartIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleUsartIrq_idle_tooshortforheadercheck)
|
||||
{
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
expectedStream = 0;
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
|
||||
ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
|
||||
ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
|
||||
ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - 3);
|
||||
ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
|
||||
ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
|
||||
|
||||
Pu_HandleUsartIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 0);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleRxDmaIrq_tc_hdrok)
|
||||
{
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
memset(&fakeDma1, 0, sizeof(fakeDma1));
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
expectedStream = 0;
|
||||
expectedCrcEnqueueAddress = &usartStatus.rxBuffers[0].packet;
|
||||
expectedCrcLength = RoundUpTo4(usartStatus.rxBuffers[0].packet.header.payloadLength) + sizeof(struct usartpacketheader_t);
|
||||
fakeDma1.LISR = DMA_LISR_TCIF0;
|
||||
|
||||
ACTIVATE_MOCK(Pu_CheckHeader, proxy);
|
||||
ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 0);
|
||||
ACTIVATE_MOCK(Pu_SetupReceive, mock);
|
||||
|
||||
Pu_HandleRxDmaIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(fakeDma1.LIFCR, DMA_LIFCR_CTCIF0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleRxDmaIrq_tc_hdrfail)
|
||||
{
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
|
||||
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
memset(&fakeDma1, 0, sizeof(fakeDma1));
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
expectedStream = 0;
|
||||
expectedCrcEnqueueAddress = &usartStatus.rxBuffers[0].packet;
|
||||
expectedCrcLength = RoundUpTo4(usartStatus.rxBuffers[0].packet.header.payloadLength) + sizeof(struct usartpacketheader_t);
|
||||
fakeDma1.LISR = DMA_LISR_TCIF0;
|
||||
|
||||
ACTIVATE_MOCK(Pu_CheckHeader, proxy);
|
||||
ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 0);
|
||||
ACTIVATE_MOCK(Pu_SetupReceive, mock);
|
||||
|
||||
Pu_HandleRxDmaIrq(&usartStatus);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(Crc_Enqueue, mock), 0);
|
||||
EXPECT_EQ(fakeDma1.LIFCR, DMA_LIFCR_CTCIF0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].error, 1);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleRxCrcComputedCallback_success_match)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
|
||||
*(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa55a;
|
||||
MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
|
||||
|
||||
Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
|
||||
EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
|
||||
EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleRxCrcComputedCallback_success_mismatch)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
|
||||
*(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa5a5;
|
||||
MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
|
||||
|
||||
Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
|
||||
EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
|
||||
EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
|
||||
}
|
||||
|
||||
TEST_F(PacketUsart, HandleRxCrcComputedCallback_failure)
|
||||
{
|
||||
Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
|
||||
Pu_SetupReceive(&usartStatus);
|
||||
|
||||
struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
|
||||
memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
|
||||
memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
|
||||
*(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa5a5;
|
||||
MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
|
||||
|
||||
Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
|
||||
|
||||
EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
|
||||
EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
|
||||
EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
|
||||
}
|
||||
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Add table
Add a link
Reference in a new issue