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Changes requested during the initial review

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This commit is contained in:
Attila Body 2020-01-13 09:47:52 +01:00
parent 53e65e566a
commit c4c6ac8bb3
8 changed files with 186 additions and 89 deletions
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63
components/f4ll_c/test/crcscheduler_unittests.cpp
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@ -25,8 +25,8 @@ DMA_TypeDef * DMA2 __attribute__((weak));
static DMA_TypeDef dma1, dma2;
static crcstatus_t crcStatus;
static crcslotlistitem_t slot1, slot2;
static crcslottask_t tasks1[2], tasks2[2];
static crcslot_t slot1, slot2;
static crctask_t tasks1[2], tasks2[2];
static CRC_TypeDef fakeCrc;
static DMA_TypeDef *expectedDma;
@ -49,7 +49,7 @@ DEFINE_MOCK(__set_PRIMASK, mock, uint32_t primask) {
LEAVE_MOCK;
}
DEFINE_MOCK_VAR(crcslotlistitem_t *, __disable_irq, mock, compare);
DEFINE_MOCK_VAR(crcslot_t *, __disable_irq, mock, compare);
DEFINE_MOCK(__disable_irq, mock) {
if(!MOCK_VAR(__disable_irq, mock, callcount)) {
EXPECT_EQ(crcStatus.firstSlot, MOCK_VAR(__disable_irq, mock, compare));
@ -157,7 +157,7 @@ TEST(CrcScheduler, AttachTask_single)
DMA2 = &dma2;
Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
EXPECT_EQ(MOCK_VAR(__get_PRIMASK, mock, callcount), 1);
EXPECT_EQ(MOCK_VAR(__set_PRIMASK, mock, callcount), 1);
@ -168,6 +168,7 @@ TEST(CrcScheduler, AttachTask_single)
EXPECT_EQ(crcStatus.activeSlot, nullptr);
}
// Are tasks attached in the expected order internally
TEST(CrcScheduler, AttachTask_multiple)
{
ACTIVATE_MOCK_RV(__get_PRIMASK, mock, 1);
@ -178,9 +179,9 @@ TEST(CrcScheduler, AttachTask_multiple)
DMA2 = &dma2;
Crc_InitStatus(&crcStatus, NULL, DMA2, LL_DMA_STREAM_4);
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
MOCK_STORE(__disable_irq, mock, compare, &slot1);
Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
EXPECT_EQ(__get_PRIMASK_mock_callcount, 2);
EXPECT_EQ(__set_PRIMASK_mock_callcount, 2);
@ -192,6 +193,7 @@ TEST(CrcScheduler, AttachTask_multiple)
EXPECT_EQ(crcStatus.activeSlot, nullptr);
}
// No blocking should occur if the the task is not busy
TEST(CrcScheduler, Enqueue_nowait)
{
uint32_t fakeCrcResult;
@ -204,7 +206,7 @@ TEST(CrcScheduler, Enqueue_nowait)
memset(&fakeCrc, 0, sizeof(fakeCrc));
Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
expectedLength = 2;
ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
@ -233,6 +235,9 @@ TEST(CrcScheduler, Enqueue_nowait)
EXPECT_EQ(MOCK_VAR(LL_DMA_EnableStream, mock, callcount), 1);
}
// When trying to enqueue for a busy task it should blok firs
// then when the previously blocked task finishes it should
// enqueue the new one
TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
{
uint8_t testData[] = "qwerty";
@ -242,7 +247,7 @@ TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
memset(&fakeCrc, 0, sizeof(fakeCrc));
Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult);
// black magic to test if the function blocks (at least for 100ms)
@ -265,6 +270,7 @@ TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
pthread_cancel(th);
}
// StartNextTask should start the scheduled tasks in predefined order
TEST(CrcScheduler, Crc_StartNextTask)
{
uint8_t testData[] = "qwerty";
@ -275,8 +281,8 @@ TEST(CrcScheduler, Crc_StartNextTask)
memset(&fakeCrc, 0, sizeof(fakeCrc));
Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult1);
Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_2, &fakeCrcResult2);
Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallback_3, &fakeCrcResult3);
@ -314,6 +320,8 @@ TEST(CrcScheduler, Crc_StartNextTask)
EXPECT_EQ(LL_DMA_EnableStream_mock_callcount, 2);
}
// HandleDmaIrq should start the next scheduled task or
// disable the CRC DMA engine if there is no other task scheduled.
TEST(CrcScheduler, HandleDmaIrq_callback)
{
uint8_t testData[] = "qwerty";
@ -327,8 +335,8 @@ TEST(CrcScheduler, HandleDmaIrq_callback)
fakeCrc.DR = 0xa5a55a5a;
Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData1);
// we need to set this up here to check if HandleDmaIrq calls Crc_StartNextTask or not;
Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData2);
@ -367,46 +375,51 @@ TEST(CrcScheduler, HandleDmaIrq_callback)
EXPECT_EQ(LL_DMA_DisableStream_mock_callcount, 2);
}
TEST(CrcScheduler, IsSlotQueued)
// Crc_StartNextTask starts executing the next task and removes it from the queue
// Test if IsTaskQueued reflects this behaviour correctly
TEST(CrcScheduler, IsTaskQueued)
{
uint8_t testData[] = "qwerty";
uint32_t FakeCustomData1;
Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
EXPECT_EQ(Crc_IsSlotQueued(&slot1, 0), 0);
EXPECT_NE(Crc_IsSlotQueued(&slot1, 1), 0);
EXPECT_EQ(Crc_IsTaskQueued(&slot1, 0), 0);
EXPECT_NE(Crc_IsTaskQueued(&slot1, 1), 0);
Crc_StartNextTask(&crcStatus);
EXPECT_EQ(Crc_IsSlotQueued(&slot1, 1), 0);
EXPECT_EQ(Crc_IsTaskQueued(&slot1, 1), 0);
}
TEST(CrcScheduler, IsSlotBusy)
// Crc_HandleDmaIrq completes the active task and start executing the next (by calling StartNextTask)
// Crc_IsTaskBusy should reflect these changes
TEST(CrcScheduler, IsTaskBusy)
{
uint8_t testData[] = "qwerty";
uint32_t FakeCustomData1;
Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
EXPECT_NE(Crc_IsSlotBusy(&slot1, 0), 0);
EXPECT_NE(Crc_IsSlotBusy(&slot1, 1), 0);
EXPECT_NE(Crc_IsTaskBusy(&slot1, 0), 0);
EXPECT_NE(Crc_IsTaskBusy(&slot1, 1), 0);
DMA2->HISR |= DMA_HISR_TCIF4;
Crc_HandleDmaIrq(&crcStatus);
EXPECT_EQ(Crc_IsSlotBusy(&slot1, 0), 0);
EXPECT_NE(Crc_IsSlotBusy(&slot1, 1), 0);
EXPECT_EQ(Crc_IsTaskBusy(&slot1, 0), 0);
EXPECT_NE(Crc_IsTaskBusy(&slot1, 1), 0);
DMA2->HISR |= DMA_HISR_TCIF4;
Crc_HandleDmaIrq(&crcStatus);
EXPECT_EQ(Crc_IsSlotBusy(&slot1, 0), 0);
EXPECT_EQ(Crc_IsSlotBusy(&slot1, 1), 0);
EXPECT_EQ(Crc_IsTaskBusy(&slot1, 0), 0);
EXPECT_EQ(Crc_IsTaskBusy(&slot1, 1), 0);
}