Changes requested during the initial review
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53e65e566a
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c4c6ac8bb3
8 changed files with 186 additions and 89 deletions
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@ -25,8 +25,8 @@ DMA_TypeDef * DMA2 __attribute__((weak));
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static DMA_TypeDef dma1, dma2;
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static crcstatus_t crcStatus;
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static crcslotlistitem_t slot1, slot2;
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static crcslottask_t tasks1[2], tasks2[2];
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static crcslot_t slot1, slot2;
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static crctask_t tasks1[2], tasks2[2];
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static CRC_TypeDef fakeCrc;
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static DMA_TypeDef *expectedDma;
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@ -49,7 +49,7 @@ DEFINE_MOCK(__set_PRIMASK, mock, uint32_t primask) {
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LEAVE_MOCK;
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}
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DEFINE_MOCK_VAR(crcslotlistitem_t *, __disable_irq, mock, compare);
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DEFINE_MOCK_VAR(crcslot_t *, __disable_irq, mock, compare);
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DEFINE_MOCK(__disable_irq, mock) {
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if(!MOCK_VAR(__disable_irq, mock, callcount)) {
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EXPECT_EQ(crcStatus.firstSlot, MOCK_VAR(__disable_irq, mock, compare));
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@ -157,7 +157,7 @@ TEST(CrcScheduler, AttachTask_single)
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DMA2 = &dma2;
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
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EXPECT_EQ(MOCK_VAR(__get_PRIMASK, mock, callcount), 1);
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EXPECT_EQ(MOCK_VAR(__set_PRIMASK, mock, callcount), 1);
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@ -168,6 +168,7 @@ TEST(CrcScheduler, AttachTask_single)
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EXPECT_EQ(crcStatus.activeSlot, nullptr);
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}
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// Are tasks attached in the expected order internally
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TEST(CrcScheduler, AttachTask_multiple)
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{
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ACTIVATE_MOCK_RV(__get_PRIMASK, mock, 1);
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@ -178,9 +179,9 @@ TEST(CrcScheduler, AttachTask_multiple)
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DMA2 = &dma2;
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Crc_InitStatus(&crcStatus, NULL, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
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MOCK_STORE(__disable_irq, mock, compare, &slot1);
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Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
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Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
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EXPECT_EQ(__get_PRIMASK_mock_callcount, 2);
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EXPECT_EQ(__set_PRIMASK_mock_callcount, 2);
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@ -192,6 +193,7 @@ TEST(CrcScheduler, AttachTask_multiple)
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EXPECT_EQ(crcStatus.activeSlot, nullptr);
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}
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// No blocking should occur if the the task is not busy
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TEST(CrcScheduler, Enqueue_nowait)
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{
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uint32_t fakeCrcResult;
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@ -204,7 +206,7 @@ TEST(CrcScheduler, Enqueue_nowait)
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memset(&fakeCrc, 0, sizeof(fakeCrc));
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
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expectedLength = 2;
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ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
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@ -233,6 +235,9 @@ TEST(CrcScheduler, Enqueue_nowait)
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EXPECT_EQ(MOCK_VAR(LL_DMA_EnableStream, mock, callcount), 1);
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}
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// When trying to enqueue for a busy task it should blok firs
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// then when the previously blocked task finishes it should
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// enqueue the new one
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TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
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{
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uint8_t testData[] = "qwerty";
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@ -242,7 +247,7 @@ TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
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memset(&fakeCrc, 0, sizeof(fakeCrc));
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
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Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult);
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// black magic to test if the function blocks (at least for 100ms)
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@ -265,6 +270,7 @@ TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
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pthread_cancel(th);
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}
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// StartNextTask should start the scheduled tasks in predefined order
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TEST(CrcScheduler, Crc_StartNextTask)
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{
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uint8_t testData[] = "qwerty";
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@ -275,8 +281,8 @@ TEST(CrcScheduler, Crc_StartNextTask)
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memset(&fakeCrc, 0, sizeof(fakeCrc));
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
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Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
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Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult1);
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Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_2, &fakeCrcResult2);
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Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallback_3, &fakeCrcResult3);
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@ -314,6 +320,8 @@ TEST(CrcScheduler, Crc_StartNextTask)
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EXPECT_EQ(LL_DMA_EnableStream_mock_callcount, 2);
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}
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// HandleDmaIrq should start the next scheduled task or
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// disable the CRC DMA engine if there is no other task scheduled.
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TEST(CrcScheduler, HandleDmaIrq_callback)
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{
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uint8_t testData[] = "qwerty";
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@ -327,8 +335,8 @@ TEST(CrcScheduler, HandleDmaIrq_callback)
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fakeCrc.DR = 0xa5a55a5a;
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTask(&crcStatus, &slot2, tasks2, 2);
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Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
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Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData1);
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// we need to set this up here to check if HandleDmaIrq calls Crc_StartNextTask or not;
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Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData2);
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@ -367,46 +375,51 @@ TEST(CrcScheduler, HandleDmaIrq_callback)
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EXPECT_EQ(LL_DMA_DisableStream_mock_callcount, 2);
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}
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TEST(CrcScheduler, IsSlotQueued)
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// Crc_StartNextTask starts executing the next task and removes it from the queue
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// Test if IsTaskQueued reflects this behaviour correctly
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TEST(CrcScheduler, IsTaskQueued)
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{
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uint8_t testData[] = "qwerty";
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uint32_t FakeCustomData1;
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
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Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
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Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
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EXPECT_EQ(Crc_IsSlotQueued(&slot1, 0), 0);
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EXPECT_NE(Crc_IsSlotQueued(&slot1, 1), 0);
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EXPECT_EQ(Crc_IsTaskQueued(&slot1, 0), 0);
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EXPECT_NE(Crc_IsTaskQueued(&slot1, 1), 0);
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Crc_StartNextTask(&crcStatus);
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EXPECT_EQ(Crc_IsSlotQueued(&slot1, 1), 0);
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EXPECT_EQ(Crc_IsTaskQueued(&slot1, 1), 0);
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}
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TEST(CrcScheduler, IsSlotBusy)
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// Crc_HandleDmaIrq completes the active task and start executing the next (by calling StartNextTask)
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// Crc_IsTaskBusy should reflect these changes
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TEST(CrcScheduler, IsTaskBusy)
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{
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uint8_t testData[] = "qwerty";
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uint32_t FakeCustomData1;
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Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
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Crc_AttachTask(&crcStatus, &slot1, tasks1, 2);
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Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
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Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
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Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
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EXPECT_NE(Crc_IsSlotBusy(&slot1, 0), 0);
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EXPECT_NE(Crc_IsSlotBusy(&slot1, 1), 0);
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EXPECT_NE(Crc_IsTaskBusy(&slot1, 0), 0);
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EXPECT_NE(Crc_IsTaskBusy(&slot1, 1), 0);
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DMA2->HISR |= DMA_HISR_TCIF4;
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Crc_HandleDmaIrq(&crcStatus);
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EXPECT_EQ(Crc_IsSlotBusy(&slot1, 0), 0);
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EXPECT_NE(Crc_IsSlotBusy(&slot1, 1), 0);
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EXPECT_EQ(Crc_IsTaskBusy(&slot1, 0), 0);
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EXPECT_NE(Crc_IsTaskBusy(&slot1, 1), 0);
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DMA2->HISR |= DMA_HISR_TCIF4;
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Crc_HandleDmaIrq(&crcStatus);
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EXPECT_EQ(Crc_IsSlotBusy(&slot1, 0), 0);
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EXPECT_EQ(Crc_IsSlotBusy(&slot1, 1), 0);
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EXPECT_EQ(Crc_IsTaskBusy(&slot1, 0), 0);
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EXPECT_EQ(Crc_IsTaskBusy(&slot1, 1), 0);
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}
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