playground-stm32/f407ve_packetusart_c
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replaced gtest + mockme with CPPUtest + subhook

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Part 1
This commit is contained in:
Attila Body 2021-02-25 00:20:15 +01:00
parent 95af4ce0d8
commit 8709bcb465
284 changed files with 87 additions and 113526 deletions
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3
platforms/platform-test-f4-ll/build_dependencies.sh → platforms/platform-test-f4-ll/build_cpputest.sh
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@ -1,8 +1,5 @@
#!/bin/bash
SCRIPTDIR=$(readlink -f $(dirname "$0"))
cd "$SCRIPTDIR"/subhook
cmake -DSUBHOOK_FORCE_32BIT=1 -DSUBHOOK_STATIC=1 -DSUBHOOK_TESTS=0 -DCMAKE_INSTALL_PREFIX:PATH="$SCRIPTDIR/subhook_x86" .
make -j$(nproc) && make install
cd "$SCRIPTDIR"/cpputest/cpputest_build
cmake -DCPPUTEST_C_FLAGS=-m32 -DCPPUTEST_CXX_FLAGS=-m32 -DCPPUTEST_LD_FLAGS=-m32 \
-DC++11=ON -DTESTS=OFF -DCMAKE_INSTALL_PREFIX:PATH="$SCRIPTDIR"/cpputest_x86 ..

5
platforms/platform-test-f4-ll/build_subhook.sh Executable file
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#!/bin/bash
SCRIPTDIR=$(readlink -f $(dirname "$0"))
cd "$SCRIPTDIR"/subhook
cmake -DSUBHOOK_FORCE_32BIT=1 -DSUBHOOK_STATIC=1 -DSUBHOOK_TESTS=0 -DCMAKE_INSTALL_PREFIX:PATH="$SCRIPTDIR/subhook_x86" .
make -j$(nproc) && make install

23
platforms/platform-test-f4-ll/component.mk Normal file
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SELF_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
REL_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
ifeq ($(MKDBG), 1)
$(info >>> $(REL_DIR)/component.mk)
endif
$(eval C_SOURCES += $(wildcard $(REL_DIR)/platform/*.c))
$(eval COMMON_INCLUDES += \
-I$(REL_DIR) \
-I$(REL_DIR)/cpputest_i386/include \
-I$(REL_DIR)/subhook_i386/include)
$(eval LIBDIR += -L$(REL_DIR)/cpputest_i386/lib -L$(REL_DIR)/subhook_i386/lib)
$(eval LIBS += -lCppUTestExt -lCppUTest -lsubhook -lpthread)
$(eval COMPONENT_DEPS += $(REL_DIR)/cpputest_i386 $(REL_DIR)/subhook_i386)
$(REL_DIR)/cpputest_i386:
$(REL_DIR)/build_cpputest.sh
$(REL_DIR)/subhook_i386:
$(REL_DIR)/build_subhook.sh
ifeq ($(MKDBG), 1)
$(info <<<)
endif

12
platforms/platform-test-f4-ll/platform/cmsis.c Normal file
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/*
* cmsis.c
*
* Created on: Nov 22, 2019
* Author: abody
*/
#include "cmsis.h"
#include <stdlib.h>
void __disable_irq)() {}
uint32_t __get_PRIMASK() { return 0; }
void __set_PRIMASK(uint32_t primask) {}

34
platforms/platform-test-f4-ll/platform/cmsis.h Normal file
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/*
* cmsis.h
*
* Created on: Nov 22, 2019
* Author: abody
*/
#ifndef PLATFORM_CMSIS_H_
#define PLATFORM_CMSIS_H_
#include <stddef.h>
#include <inttypes.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __IO volatile
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
void __disable_irq();
uint32_t __get_PRIMASK();
void __set_PRIMASK(uint32_t priMask);
#ifdef __cplusplus
}
#endif
#endif /* PLATFORM_CMSIS_H_ */

33
platforms/platform-test-f4-ll/platform/crc_ll.h Normal file
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/*
* crc_ll.h
*
* Created on: Nov 22, 2019
* Author: abody
*/
#ifndef PLATFORM_CRC_LL_H_
#define PLATFORM_CRC_LL_H_
#include <inttypes.h>
#ifndef __IO
# define __IO volatile
#endif // __IO
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef;
#endif /* PLATFORM_CRC_LL_H_ */

17
platforms/platform-test-f4-ll/platform/dma_ll.c Normal file
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/*
* dma_ll.c
*
* Created on: Nov 22, 2019
* Author: abody
*/
#include "dma_ll.h"
void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) {}
void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) {}
void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) {}
void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) {}
uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) { return 0; }
void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) {}
void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) {}
void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) {}
void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) {}

628
platforms/platform-test-f4-ll/platform/dma_ll.h Normal file
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/*
* dma_ll.h
*
* Created on: Nov 21, 2019
* Author: abody
*/
#ifndef DMA_LL_H_
#define DMA_LL_H_
#include <inttypes.h>
#include <platform/cmsis.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __IO
# define __IO volatile
#endif // __IO
typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;
typedef struct
{
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
#define DMA_SxCR_CHSEL_Pos (25U)
#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
#define DMA_SxCR_CHSEL_0 0x02000000U
#define DMA_SxCR_CHSEL_1 0x04000000U
#define DMA_SxCR_CHSEL_2 0x08000000U
#define DMA_SxCR_MBURST_Pos (23U)
#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
#define DMA_SxCR_PBURST_Pos (21U)
#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk
#define DMA_SxCR_DBM_Pos (18U)
#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
#define DMA_SxCR_PL_Pos (16U)
#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
#define DMA_SxCR_PL DMA_SxCR_PL_Msk
#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
#define DMA_SxCR_PINCOS_Pos (15U)
#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
#define DMA_SxCR_MSIZE_Pos (13U)
#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
#define DMA_SxCR_PSIZE_Pos (11U)
#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
#define DMA_SxCR_MINC_Pos (10U)
#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
#define DMA_SxCR_PINC_Pos (9U)
#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
#define DMA_SxCR_CIRC_Pos (8U)
#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
#define DMA_SxCR_DIR_Pos (6U)
#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
#define DMA_SxCR_PFCTRL_Pos (5U)
#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
#define DMA_SxCR_TCIE_Pos (4U)
#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
#define DMA_SxCR_HTIE_Pos (3U)
#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
#define DMA_SxCR_TEIE_Pos (2U)
#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
#define DMA_SxCR_DMEIE_Pos (1U)
#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
#define DMA_SxCR_EN_Pos (0U)
#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
#define DMA_SxCR_EN DMA_SxCR_EN_Msk
/* Legacy defines */
#define DMA_SxCR_ACK_Pos (20U)
#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
/******************** Bits definition for DMA_SxCNDTR register **************/
#define DMA_SxNDT_Pos (0U)
#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
#define DMA_SxNDT DMA_SxNDT_Msk
#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
/******************** Bits definition for DMA_SxFCR register ****************/
#define DMA_SxFCR_FEIE_Pos (7U)
#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
#define DMA_SxFCR_FS_Pos (3U)
#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
#define DMA_SxFCR_DMDIS_Pos (2U)
#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
#define DMA_SxFCR_FTH_Pos (0U)
#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
/******************** Bits definition for DMA_LISR register *****************/
#define DMA_LISR_TCIF3_Pos (27U)
#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
#define DMA_LISR_HTIF3_Pos (26U)
#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
#define DMA_LISR_TEIF3_Pos (25U)
#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
#define DMA_LISR_DMEIF3_Pos (24U)
#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
#define DMA_LISR_FEIF3_Pos (22U)
#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
#define DMA_LISR_TCIF2_Pos (21U)
#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
#define DMA_LISR_HTIF2_Pos (20U)
#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
#define DMA_LISR_TEIF2_Pos (19U)
#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
#define DMA_LISR_DMEIF2_Pos (18U)
#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
#define DMA_LISR_FEIF2_Pos (16U)
#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
#define DMA_LISR_TCIF1_Pos (11U)
#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
#define DMA_LISR_HTIF1_Pos (10U)
#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
#define DMA_LISR_TEIF1_Pos (9U)
#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
#define DMA_LISR_DMEIF1_Pos (8U)
#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
#define DMA_LISR_FEIF1_Pos (6U)
#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
#define DMA_LISR_TCIF0_Pos (5U)
#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
#define DMA_LISR_HTIF0_Pos (4U)
#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
#define DMA_LISR_TEIF0_Pos (3U)
#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
#define DMA_LISR_DMEIF0_Pos (2U)
#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
#define DMA_LISR_FEIF0_Pos (0U)
#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
/******************** Bits definition for DMA_HISR register *****************/
#define DMA_HISR_TCIF7_Pos (27U)
#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
#define DMA_HISR_HTIF7_Pos (26U)
#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
#define DMA_HISR_TEIF7_Pos (25U)
#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
#define DMA_HISR_DMEIF7_Pos (24U)
#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
#define DMA_HISR_FEIF7_Pos (22U)
#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
#define DMA_HISR_TCIF6_Pos (21U)
#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
#define DMA_HISR_HTIF6_Pos (20U)
#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
#define DMA_HISR_TEIF6_Pos (19U)
#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
#define DMA_HISR_DMEIF6_Pos (18U)
#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
#define DMA_HISR_FEIF6_Pos (16U)
#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
#define DMA_HISR_TCIF5_Pos (11U)
#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
#define DMA_HISR_HTIF5_Pos (10U)
#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
#define DMA_HISR_TEIF5_Pos (9U)
#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
#define DMA_HISR_DMEIF5_Pos (8U)
#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
#define DMA_HISR_FEIF5_Pos (6U)
#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
#define DMA_HISR_TCIF4_Pos (5U)
#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
#define DMA_HISR_HTIF4_Pos (4U)
#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
#define DMA_HISR_TEIF4_Pos (3U)
#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
#define DMA_HISR_DMEIF4_Pos (2U)
#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
#define DMA_HISR_FEIF4_Pos (0U)
#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
/******************** Bits definition for DMA_LIFCR register ****************/
#define DMA_LIFCR_CTCIF3_Pos (27U)
#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
#define DMA_LIFCR_CHTIF3_Pos (26U)
#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
#define DMA_LIFCR_CTEIF3_Pos (25U)
#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
#define DMA_LIFCR_CDMEIF3_Pos (24U)
#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
#define DMA_LIFCR_CFEIF3_Pos (22U)
#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
#define DMA_LIFCR_CTCIF2_Pos (21U)
#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
#define DMA_LIFCR_CHTIF2_Pos (20U)
#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
#define DMA_LIFCR_CTEIF2_Pos (19U)
#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
#define DMA_LIFCR_CDMEIF2_Pos (18U)
#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
#define DMA_LIFCR_CFEIF2_Pos (16U)
#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
#define DMA_LIFCR_CTCIF1_Pos (11U)
#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
#define DMA_LIFCR_CHTIF1_Pos (10U)
#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
#define DMA_LIFCR_CTEIF1_Pos (9U)
#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
#define DMA_LIFCR_CDMEIF1_Pos (8U)
#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
#define DMA_LIFCR_CFEIF1_Pos (6U)
#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
#define DMA_LIFCR_CTCIF0_Pos (5U)
#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
#define DMA_LIFCR_CHTIF0_Pos (4U)
#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
#define DMA_LIFCR_CTEIF0_Pos (3U)
#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
#define DMA_LIFCR_CDMEIF0_Pos (2U)
#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
#define DMA_LIFCR_CFEIF0_Pos (0U)
#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
/******************** Bits definition for DMA_HIFCR register ****************/
#define DMA_HIFCR_CTCIF7_Pos (27U)
#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
#define DMA_HIFCR_CHTIF7_Pos (26U)
#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
#define DMA_HIFCR_CTEIF7_Pos (25U)
#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
#define DMA_HIFCR_CDMEIF7_Pos (24U)
#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
#define DMA_HIFCR_CFEIF7_Pos (22U)
#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
#define DMA_HIFCR_CTCIF6_Pos (21U)
#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
#define DMA_HIFCR_CHTIF6_Pos (20U)
#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
#define DMA_HIFCR_CTEIF6_Pos (19U)
#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
#define DMA_HIFCR_CDMEIF6_Pos (18U)
#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
#define DMA_HIFCR_CFEIF6_Pos (16U)
#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
#define DMA_HIFCR_CTCIF5_Pos (11U)
#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
#define DMA_HIFCR_CHTIF5_Pos (10U)
#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
#define DMA_HIFCR_CTEIF5_Pos (9U)
#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
#define DMA_HIFCR_CDMEIF5_Pos (8U)
#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
#define DMA_HIFCR_CFEIF5_Pos (6U)
#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
#define DMA_HIFCR_CTCIF4_Pos (5U)
#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
#define DMA_HIFCR_CHTIF4_Pos (4U)
#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
#define DMA_HIFCR_CTEIF4_Pos (3U)
#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
#define DMA_HIFCR_CDMEIF4_Pos (2U)
#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
#define DMA_HIFCR_CFEIF4_Pos (0U)
#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
/****************** Bit definition for DMA_SxPAR register ********************/
#define DMA_SxPAR_PA_Pos (0U)
#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_SxM0AR register ********************/
#define DMA_SxM0AR_M0A_Pos (0U)
#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
/****************** Bit definition for DMA_SxM1AR register ********************/
#define DMA_SxM1AR_M1A_Pos (0U)
#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
/*----------- cut here -----------*/
#define LL_DMA_STREAM_0 0x00000000U
#define LL_DMA_STREAM_1 0x00000001U
#define LL_DMA_STREAM_2 0x00000002U
#define LL_DMA_STREAM_3 0x00000003U
#define LL_DMA_STREAM_4 0x00000004U
#define LL_DMA_STREAM_5 0x00000005U
#define LL_DMA_STREAM_6 0x00000006U
#define LL_DMA_STREAM_7 0x00000007U
#define LL_DMA_STREAM_ALL 0xFFFF0000U
/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
* @{
*/
#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_LL_EC_MODE MODE
* @{
*/
#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
* @{
*/
#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
/**
* @}
*/
/** @defgroup DMA_LL_EC_PERIPH PERIPH
* @{
*/
#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
/**
* @}
*/
/** @defgroup DMA_LL_EC_MEMORY MEMORY
* @{
*/
#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
/**
* @}
*/
/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
* @{
*/
#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
* @{
*/
#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
* @{
*/
#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
/**
* @}
*/
/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
* @{
*/
#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
/**
* @}
*/
/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
* @{
*/
#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
/**
* @}
*/
/** @defgroup DMA_LL_EC_MBURST MBURST
* @{
*/
#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
/**
* @}
*/
/** @defgroup DMA_LL_EC_PBURST PBURST
* @{
*/
#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
/**
* @}
*/
/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
* @{
*/
#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
* @{
*/
#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
/**
* @}
*/
/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
* @{
*/
#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
/**
* @}
*/
/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
* @{
*/
#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
/*----------- cut here -----------*/
extern DMA_TypeDef *DMA1;
extern DMA_TypeDef *DMA2;
void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream);
void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream);
void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress);
void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress);
void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData);
uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream);
void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream);
void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream);
void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction);
#ifdef __cplusplus
}
#endif
#endif /* DMA_LL_H_ */

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/*
* usart_ll.c
*
* Created on: Dec 2, 2019
* Author: abody
*/
#include "usart_ll.h"
void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) {}
void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) {}
void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) {}
uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) { return 1; }
uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) { return 1; }
void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) {}
void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) {}
uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) { return 0; }
uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) { return 1; }
uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) { return 1; }
void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) {}
void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) {}
void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) {}
void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) {}

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#ifndef __PLATFORM_USART_LL_H_INCLUDED
#define __PLATFORM_USART_LL_H_INCLUDED
#include <platform/cmsis.h>
typedef struct
{
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;
/*----------- cut here -----------*/
/******************* Bit definition for USART_SR register *******************/
#define USART_SR_PE_Pos (0U)
#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
#define USART_SR_FE_Pos (1U)
#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
#define USART_SR_NE_Pos (2U)
#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
#define USART_SR_ORE_Pos (3U)
#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
#define USART_SR_IDLE_Pos (4U)
#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
#define USART_SR_RXNE_Pos (5U)
#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
#define USART_SR_TC_Pos (6U)
#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
#define USART_SR_TXE_Pos (7U)
#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
#define USART_SR_LBD_Pos (8U)
#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
#define USART_SR_CTS_Pos (9U)
#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
/******************* Bit definition for USART_DR register *******************/
#define USART_DR_DR_Pos (0U)
#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */
#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_Fraction_Pos (0U)
#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
#define USART_BRR_DIV_Mantissa_Pos (4U)
#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */
#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
#define USART_CR1_RWU_Pos (1U)
#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */
#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
#define USART_CR1_UE_Pos (13U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_ADD_Pos (0U)
#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x1000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x2000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x0001 */
#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x0002 */
#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x0004 */
#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x0008 */
#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x0010 */
#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x0020 */
#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x0040 */
#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x0080 */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
/*----------- cut here -----------*/
extern USART_TypeDef *USART1;
extern USART_TypeDef *USART2;
extern USART_TypeDef *USART3;
extern USART_TypeDef *USART6;
void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx);
void LL_USART_EnableIT_TC(USART_TypeDef *USARTx);
void LL_USART_DisableIT_TC(USART_TypeDef *USARTx);
uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx);
uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx);
void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx);
void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx);
uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx);
uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx);
uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx);
void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx);
void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx);
void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx);
void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx);
#endif // __PLATFORM_USART_LL_H_INCLUDED