playground-stm32/f407ve_packetusart_c
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Re-generate most of the sources to make it work again

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This commit is contained in:
Attila Body 2025-05-30 00:09:44 +02:00
parent 7093d6835f
commit 5bc2a9a48b
Signed by: abody
GPG key ID: BD0C6214E68FB5CF
11 changed files with 822 additions and 1632 deletions
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56
Src/stm32f4xx_it.c
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@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -23,12 +22,6 @@
#include "stm32f4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "f4ll_c/packetusart.h"
#include "f4ll_c/crcscheduler.h"
#include "f4ll_c/consolehandler.h"
#include "f4ll_c/memcpydma.h"
#include "globals.h"
#include "diag.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -38,7 +31,7 @@
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
@ -79,7 +72,9 @@ void NMI_Handler(void)
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
@ -209,7 +204,6 @@ void SysTick_Handler(void)
void DMA1_Stream1_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
Pu_HandleRxDmaIrq(&g_uartStatuses[USART3_OFFSET]);
/* USER CODE END DMA1_Stream1_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
@ -223,7 +217,7 @@ void DMA1_Stream1_IRQHandler(void)
void DMA1_Stream2_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
// console rx
/* USER CODE END DMA1_Stream2_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
@ -236,7 +230,7 @@ void DMA1_Stream2_IRQHandler(void)
void DMA1_Stream3_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
Pu_HandleTxDmaIrq(&g_uartStatuses[USART3_OFFSET]);
/* USER CODE END DMA1_Stream3_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
@ -249,7 +243,7 @@ void DMA1_Stream3_IRQHandler(void)
void DMA1_Stream4_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
Con_HandleTxDmaIrq(&g_ConsoleTxDmaInfo, UART4);
/* USER CODE END DMA1_Stream4_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
@ -262,7 +256,7 @@ void DMA1_Stream4_IRQHandler(void)
void DMA1_Stream5_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
Pu_HandleRxDmaIrq(&g_uartStatuses[USART2_OFFSET]);
/* USER CODE END DMA1_Stream5_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
@ -275,7 +269,7 @@ void DMA1_Stream5_IRQHandler(void)
void DMA1_Stream6_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
Pu_HandleTxDmaIrq(&g_uartStatuses[USART2_OFFSET]);
/* USER CODE END DMA1_Stream6_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
@ -288,7 +282,7 @@ void DMA1_Stream6_IRQHandler(void)
void USART1_IRQHandler(void)
{
/* USER CODE BEGIN USART1_IRQn 0 */
Pu_HandleUsartIrq(&g_uartStatuses[USART1_OFFSET]);
/* USER CODE END USART1_IRQn 0 */
/* USER CODE BEGIN USART1_IRQn 1 */
@ -301,7 +295,7 @@ void USART1_IRQHandler(void)
void USART2_IRQHandler(void)
{
/* USER CODE BEGIN USART2_IRQn 0 */
Pu_HandleUsartIrq(&g_uartStatuses[USART2_OFFSET]);
/* USER CODE END USART2_IRQn 0 */
/* USER CODE BEGIN USART2_IRQn 1 */
@ -314,7 +308,7 @@ void USART2_IRQHandler(void)
void USART3_IRQHandler(void)
{
/* USER CODE BEGIN USART3_IRQn 0 */
Pu_HandleUsartIrq(&g_uartStatuses[USART3_OFFSET]);
/* USER CODE END USART3_IRQn 0 */
/* USER CODE BEGIN USART3_IRQn 1 */
@ -327,7 +321,7 @@ void USART3_IRQHandler(void)
void UART4_IRQHandler(void)
{
/* USER CODE BEGIN UART4_IRQn 0 */
Con_HandleUsartIrq(UART4);
/* USER CODE END UART4_IRQn 0 */
/* USER CODE BEGIN UART4_IRQn 1 */
@ -340,7 +334,7 @@ void UART4_IRQHandler(void)
void DMA2_Stream1_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream1_IRQn 0 */
Pu_HandleRxDmaIrq(&g_uartStatuses[USART6_OFFSET]);
/* USER CODE END DMA2_Stream1_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream1_IRQn 1 */
@ -353,7 +347,7 @@ void DMA2_Stream1_IRQHandler(void)
void DMA2_Stream2_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
Pu_HandleRxDmaIrq(&g_uartStatuses[USART1_OFFSET]);
/* USER CODE END DMA2_Stream2_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream2_IRQn 1 */
@ -366,7 +360,7 @@ void DMA2_Stream2_IRQHandler(void)
void DMA2_Stream3_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream3_IRQn 0 */
Mcd_HandleDmaIrq();
/* USER CODE END DMA2_Stream3_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream3_IRQn 1 */
@ -379,7 +373,7 @@ void DMA2_Stream3_IRQHandler(void)
void DMA2_Stream4_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream4_IRQn 0 */
Crc_HandleDmaIrq(&g_crcStatus);
/* USER CODE END DMA2_Stream4_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream4_IRQn 1 */
@ -392,7 +386,7 @@ void DMA2_Stream4_IRQHandler(void)
void DMA2_Stream6_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream6_IRQn 0 */
Pu_HandleTxDmaIrq(&g_uartStatuses[USART6_OFFSET]);
/* USER CODE END DMA2_Stream6_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream6_IRQn 1 */
@ -405,7 +399,7 @@ void DMA2_Stream6_IRQHandler(void)
void DMA2_Stream7_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
Pu_HandleTxDmaIrq(&g_uartStatuses[USART1_OFFSET]);
/* USER CODE END DMA2_Stream7_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
@ -418,7 +412,7 @@ void DMA2_Stream7_IRQHandler(void)
void USART6_IRQHandler(void)
{
/* USER CODE BEGIN USART6_IRQn 0 */
Pu_HandleUsartIrq(&g_uartStatuses[USART6_OFFSET]);
/* USER CODE END USART6_IRQn 0 */
/* USER CODE BEGIN USART6_IRQn 1 */