diff --git a/.cproject b/.cproject
index 3d0f2c9..141eab7 100644
--- a/.cproject
+++ b/.cproject
@@ -124,7 +124,7 @@
-
+
@@ -252,7 +252,7 @@
-
+
@@ -271,7 +271,7 @@
-
+
@@ -284,8 +284,9 @@
@@ -302,14 +303,15 @@
-
+
@@ -333,11 +335,13 @@
@@ -353,6 +357,7 @@
+
@@ -375,6 +380,7 @@
+
@@ -382,4 +388,4 @@
-
+
\ No newline at end of file
diff --git a/components/f4ll_c/inc/f4ll_c/memcpydma.h b/components/f4ll_c/inc/f4ll_c/memcpydma.h
index fb39134..637520b 100644
--- a/components/f4ll_c/inc/f4ll_c/memcpydma.h
+++ b/components/f4ll_c/inc/f4ll_c/memcpydma.h
@@ -19,12 +19,6 @@ void Mcd_Init(DMA_TypeDef *dma, uint32_t stream);
void * Mcd_Copy(void *dst, void const *src, size_t length);
void Mcd_HandleDmaIrq(void);
-#ifdef UNITTEST
-DECLARE_MOCK(Mcd_Init);
-DECLARE_MOCK(Mcd_Copy);
-DECLARE_MOCK(Mcd_HandleDmaIrq);
-#endif // UNITTEST
-
#ifdef __cplusplus
}
#endif
diff --git a/components/f4ll_c/src/crcscheduler.c b/components/f4ll_c/src/crcscheduler.c
index 1ae6be7..e79d82e 100644
--- a/components/f4ll_c/src/crcscheduler.c
+++ b/components/f4ll_c/src/crcscheduler.c
@@ -27,14 +27,10 @@
# define DIAG_INTERRUPT_OUT()
#endif
-#ifndef MOCKABLE
-#define MOCKABLE(x) x
-#endif
-
void Crc_StartNextTask(struct crcstatus_t *status);
-void MOCKABLE(Crc_InitStatus)(struct crcstatus_t *st, CRC_TypeDef *crcUnit, DMA_TypeDef *dma, uint32_t stream)
+void Crc_InitStatus(struct crcstatus_t *st, CRC_TypeDef *crcUnit, DMA_TypeDef *dma, uint32_t stream)
{
st->crcUnit = crcUnit;
Dma_Init(&st->dmaInfo, dma, stream);
@@ -46,7 +42,7 @@ void MOCKABLE(Crc_InitStatus)(struct crcstatus_t *st, CRC_TypeDef *crcUnit, DMA_
}
-void MOCKABLE(Crc_AttachTasks)(struct crcstatus_t *status, struct crcslot_t *slot, struct crctask_t *tasks, uint8_t taskCount)
+void Crc_AttachTasks(struct crcstatus_t *status, struct crcslot_t *slot, struct crctask_t *tasks, uint8_t taskCount)
{
slot->count = taskCount;
slot->tasks = tasks;
@@ -60,7 +56,7 @@ void MOCKABLE(Crc_AttachTasks)(struct crcstatus_t *status, struct crcslot_t *slo
}
-uint8_t MOCKABLE(Crc_GetActiveTask)(struct crcslot_t **slot_out, struct crcstatus_t volatile *status)
+uint8_t Crc_GetActiveTask(struct crcslot_t **slot_out, struct crcstatus_t volatile *status)
{
uint8_t ret;
@@ -75,23 +71,23 @@ uint8_t MOCKABLE(Crc_GetActiveTask)(struct crcslot_t **slot_out, struct crcstatu
}
-uint8_t MOCKABLE(Crc_IsTaskQueued)(struct crcslot_t *slot, uint8_t task) {
+uint8_t Crc_IsTaskQueued(struct crcslot_t *slot, uint8_t task) {
return ((struct crctask_t volatile)slot->tasks[task]).address != NULL;
}
-uint8_t MOCKABLE(Crc_IsTaskBusy)(struct crcslot_t *slot, uint8_t task) {
+uint8_t Crc_IsTaskBusy(struct crcslot_t *slot, uint8_t task) {
struct crctask_t volatile *taskPtr = &slot->tasks[task];
return taskPtr->callback != NULL || taskPtr->callbackParam != NULL;
}
-void MOCKABLE(Crc_WaitResults)(struct crcstatus_t *status, struct crcslot_t *slot, uint8_t task) {
+void Crc_WaitResults(struct crcstatus_t *status, struct crcslot_t *slot, uint8_t task) {
while(Crc_IsTaskBusy(slot, task));
}
-uint8_t MOCKABLE(Crc_Enqueue)(struct crcstatus_t *status, struct crcslot_t *slot, uint8_t task,
+uint8_t Crc_Enqueue(struct crcstatus_t *status, struct crcslot_t *slot, uint8_t task,
void *address, uint16_t len, void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
{
uint32_t prim = __get_PRIMASK();
@@ -123,7 +119,7 @@ uint8_t MOCKABLE(Crc_Enqueue)(struct crcstatus_t *status, struct crcslot_t *slot
}
-uint32_t MOCKABLE(Crc_Compute)(struct crcstatus_t *status, struct crcslot_t *slot, uint8_t task, void *address, uint16_t len)
+uint32_t Crc_Compute(struct crcstatus_t *status, struct crcslot_t *slot, uint8_t task, void *address, uint16_t len)
{
uint32_t result;
Crc_Enqueue(status, slot, task, address, len, NULL, &result);
@@ -133,7 +129,7 @@ uint32_t MOCKABLE(Crc_Compute)(struct crcstatus_t *status, struct crcslot_t *slo
// only called from ISR context
-void MOCKABLE(Crc_StartNextTask)(struct crcstatus_t *status)
+void Crc_StartNextTask(struct crcstatus_t *status)
{
char moreTasks;
uint8_t index = 0;
@@ -166,7 +162,7 @@ void MOCKABLE(Crc_StartNextTask)(struct crcstatus_t *status)
// !!!PORTABILITY WARNING!!! using registers and bits directly. should be reviewed extremely when porting to a different MCU
-void MOCKABLE(Crc_HandleDmaIrq)(struct crcstatus_t *status)
+void Crc_HandleDmaIrq(struct crcstatus_t *status)
{
uint8_t success = 1;
diff --git a/components/f4ll_c/src/dmahelper.c b/components/f4ll_c/src/dmahelper.c
index 961d496..ad56df5 100644
--- a/components/f4ll_c/src/dmahelper.c
+++ b/components/f4ll_c/src/dmahelper.c
@@ -5,11 +5,8 @@
* Author: abody
*/
#include
-#ifndef MOCKABLE
-#define MOCKABLE(x) x
-#endif
-volatile uint32_t* MOCKABLE(Dma_GetIsReg)(DMA_TypeDef *dma, uint32_t stream)
+volatile uint32_t* Dma_GetIsReg(DMA_TypeDef *dma, uint32_t stream)
{
if(dma == DMA1)
return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR;
@@ -18,7 +15,7 @@ volatile uint32_t* MOCKABLE(Dma_GetIsReg)(DMA_TypeDef *dma, uint32_t stream)
}
-volatile uint32_t* MOCKABLE(Dma_GetIfcReg)(DMA_TypeDef *dma, uint32_t stream)
+volatile uint32_t* Dma_GetIfcReg(DMA_TypeDef *dma, uint32_t stream)
{
if(dma == DMA1)
return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR;
@@ -26,7 +23,7 @@ volatile uint32_t* MOCKABLE(Dma_GetIfcReg)(DMA_TypeDef *dma, uint32_t stream)
return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR;
}
-uint32_t MOCKABLE(Dma_GetFeMask)(uint32_t stream)
+uint32_t Dma_GetFeMask(uint32_t stream)
{
static const uint32_t feMasks[8] = {
DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7
@@ -34,7 +31,7 @@ uint32_t MOCKABLE(Dma_GetFeMask)(uint32_t stream)
return feMasks[stream];
}
-uint32_t MOCKABLE(Dma_GetDmeMask)(uint32_t stream)
+uint32_t Dma_GetDmeMask(uint32_t stream)
{
static const uint32_t dmeMasks[8] = {
DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7
@@ -42,7 +39,7 @@ uint32_t MOCKABLE(Dma_GetDmeMask)(uint32_t stream)
return dmeMasks[stream];
}
-uint32_t MOCKABLE(Dma_GetTeMask)(uint32_t stream)
+uint32_t Dma_GetTeMask(uint32_t stream)
{
static const uint32_t teMasks[8] = {
DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7
@@ -50,7 +47,7 @@ uint32_t MOCKABLE(Dma_GetTeMask)(uint32_t stream)
return teMasks[stream];
}
-uint32_t MOCKABLE(Dma_GetHtMask)(uint32_t stream)
+uint32_t Dma_GetHtMask(uint32_t stream)
{
static const uint32_t htMasks[8] = {
DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7
@@ -58,7 +55,7 @@ uint32_t MOCKABLE(Dma_GetHtMask)(uint32_t stream)
return htMasks[stream];
}
-uint32_t MOCKABLE(Dma_GetTcMask)(uint32_t stream)
+uint32_t Dma_GetTcMask(uint32_t stream)
{
static const uint32_t tcMasks[8] = {
DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7
@@ -67,7 +64,7 @@ uint32_t MOCKABLE(Dma_GetTcMask)(uint32_t stream)
return tcMasks[stream];
}
-void MOCKABLE(Dma_Init)(struct dmainfo_t *info, DMA_TypeDef *dma, uint32_t stream)
+void Dma_Init(struct dmainfo_t *info, DMA_TypeDef *dma, uint32_t stream)
{
info->dma = dma;
info->stream = stream;
diff --git a/components/f4ll_c/src/memcpydma.c b/components/f4ll_c/src/memcpydma.c
index a6f5285..953e452 100644
--- a/components/f4ll_c/src/memcpydma.c
+++ b/components/f4ll_c/src/memcpydma.c
@@ -15,21 +15,17 @@
# define DIAG_INTERRUPT_OUT()
#endif
-#ifndef MOCKABLE
-#define MOCKABLE(x) x
-#endif // MOCKABLE
-
volatile uint8_t g_memcpyDmaBusy = 0;
static struct dmainfo_t g_memcpyDmaInfo;
-void MOCKABLE(Mcd_Init)(DMA_TypeDef *dma, uint32_t stream)
+void Mcd_Init(DMA_TypeDef *dma, uint32_t stream)
{
Dma_Init(&g_memcpyDmaInfo, dma, stream);
LL_DMA_EnableIT_TC(dma, stream);
}
-void * MOCKABLE(Mcd_Copy)(void *dst, void const *src, size_t length)
+void * Mcd_Copy(void *dst, void const *src, size_t length)
{
LL_DMA_SetM2MSrcAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)src);
LL_DMA_SetM2MDstAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)dst);
@@ -40,7 +36,7 @@ void * MOCKABLE(Mcd_Copy)(void *dst, void const *src, size_t length)
return dst;
}
-void MOCKABLE(Mcd_HandleDmaIrq)(void)
+void Mcd_HandleDmaIrq(void)
{
DIAG_INTERRUPT_IN();
if(*g_memcpyDmaInfo.isReg & g_memcpyDmaInfo.tcMask) { // DMA transfer complete
diff --git a/components/f4ll_c/src/packetusart.c b/components/f4ll_c/src/packetusart.c
index 1f316af..14ac451 100644
--- a/components/f4ll_c/src/packetusart.c
+++ b/components/f4ll_c/src/packetusart.c
@@ -15,10 +15,6 @@
#include "f4ll_c/dmahelper.h"
#include "f4ll_c/crcscheduler.h"
-#ifndef MOCKABLE
-#define MOCKABLE(x) x
-#endif
-
#ifndef DIAG_RX_BUFFER_SWITCH
# define DIAG_RX_BUFFER_SWITCH(x)
#endif
@@ -80,7 +76,7 @@ static inline void StatsAddSkiped(struct usart_stats *s, uint8_t cnt) {
#define StatsAddSkiped(x)
#endif // USART_STATS_DISABLED
-void MOCKABLE(Pu_Init)(
+void Pu_Init(
struct usartstatus_t *st, USART_TypeDef *usart, DMA_TypeDef *dma,
uint32_t stream_rx, uint32_t stream_tx,
struct crcstatus_t *crcStatus,
@@ -130,19 +126,19 @@ void MOCKABLE(Pu_Init)(
}
-uint8_t* MOCKABLE(Pu_GetTxBuffer)(struct usartstatus_t *status)
+uint8_t* Pu_GetTxBuffer(struct usartstatus_t *status)
{
return status->txBuffer.packet.payload;
}
-uint8_t MOCKABLE(Pu_CheckHeader)(struct usartpacket_t *packet)
+uint8_t Pu_CheckHeader(struct usartpacket_t *packet)
{
return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
}
-uint8_t MOCKABLE(Pu_Post)(struct usartstatus_t *status, uint8_t const *payload, uint8_t length, uint8_t waitForCrcQueue)
+uint8_t Pu_Post(struct usartstatus_t *status, uint8_t const *payload, uint8_t length, uint8_t waitForCrcQueue)
{
struct usart_buffer_t *buffer = &status->txBuffer;
uint8_t hash = STARTMARKER;
@@ -169,7 +165,7 @@ uint8_t MOCKABLE(Pu_Post)(struct usartstatus_t *status, uint8_t const *payload,
}
-void MOCKABLE(Pu_SetupReceive)(struct usartstatus_t *status)
+void Pu_SetupReceive(struct usartstatus_t *status)
{
uint8_t packetIndex = status->activeRxBuf;
@@ -183,7 +179,7 @@ void MOCKABLE(Pu_SetupReceive)(struct usartstatus_t *status)
}
-void MOCKABLE(Pu_SetupTransmit)(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
+void Pu_SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
{
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
LL_DMA_SetDataLength(dma, stream, length);
@@ -192,7 +188,7 @@ void MOCKABLE(Pu_SetupTransmit)(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t
}
-void MOCKABLE(Pu_ConsumePacket)(struct usartstatus_t *status, uint8_t packetIndex)
+void Pu_ConsumePacket(struct usartstatus_t *status, uint8_t packetIndex)
{
struct usart_buffer_t *buffer = &status->rxBuffers[packetIndex];
if(buffer->busy) {
@@ -210,7 +206,7 @@ void MOCKABLE(Pu_ConsumePacket)(struct usartstatus_t *status, uint8_t packetInde
}
-void MOCKABLE(Pu_HandleRxDmaIrq)(struct usartstatus_t *status)
+void Pu_HandleRxDmaIrq(struct usartstatus_t *status)
{
DIAG_INTERRUPT_IN();
StatsIncRcvd(&status->stats);
@@ -242,7 +238,7 @@ void MOCKABLE(Pu_HandleRxDmaIrq)(struct usartstatus_t *status)
}
-void MOCKABLE(Pu_RxCrcComputedCallback)(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
+void Pu_RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
{
struct usart_buffer_t *ub = (struct usart_buffer_t*) callbackParm;
if(!success)
@@ -258,7 +254,7 @@ void MOCKABLE(Pu_RxCrcComputedCallback)(void *callbackParm, uint32_t calculatedC
}
-void MOCKABLE(Pu_HandleTxDmaIrq)(struct usartstatus_t *status)
+void Pu_HandleTxDmaIrq(struct usartstatus_t *status)
{
DIAG_INTERRUPT_IN();
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
@@ -283,7 +279,7 @@ void MOCKABLE(Pu_HandleTxDmaIrq)(struct usartstatus_t *status)
}
-void MOCKABLE(Pu_HandleUsartIrq)(struct usartstatus_t *status)
+void Pu_HandleUsartIrq(struct usartstatus_t *status)
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
diff --git a/components/f4ll_c/test/crcscheduler_unittests.cpp b/components/f4ll_c/test/crcscheduler_unittests.cpp
index 243fac6..be11006 100644
--- a/components/f4ll_c/test/crcscheduler_unittests.cpp
+++ b/components/f4ll_c/test/crcscheduler_unittests.cpp
@@ -11,415 +11,421 @@
#include
#include
#include
-#include
-#include
-#include
-#include
#include
#include
+#include
+#include
+
+#include
+#include
+#include
+
+
extern "C" void Crc_StartNextTask(struct crcstatus_t *status);
-DMA_TypeDef * DMA1 __attribute__((weak));
-DMA_TypeDef * DMA2 __attribute__((weak));
-
-static DMA_TypeDef dma1, dma2;
-static crcstatus_t crcStatus;
-static crcslot_t slot1, slot2;
-static crctask_t tasks1[2], tasks2[2];
-static CRC_TypeDef fakeCrc;
-
-static DMA_TypeDef *expectedDma;
-static uint32_t expectedStream;
-static uint32_t expectedSrcAddress;
-static uint32_t expectedDstAddress;
-static uint32_t expectedLength;
-static void *expectedCustomPtr;
-static uint8_t expectedSuccess;
-static uint32_t expectedCrc;
-
-//////////////////////////////////////////////////////////////////////////////
-uint32_t effective_primask = 0;
-
-DEFINE_MOCK(__set_PRIMASK, mock, uint32_t primask) {
- effective_primask = primask;
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK_RET(uint32_t, __get_PRIMASK, mock) {
- RETURN_MOCK(__get_PRIMASK, mock, effective_primask);
-}
-
-DEFINE_MOCK_VAR(crcslot_t *, __disable_irq, mock, firstslot_required);
-DEFINE_MOCK(__disable_irq, mock) {
- if(MOCK_CALLCOUNT(__disable_irq, mock) < 2) {
- EXPECT_EQ(crcStatus.firstSlot, MOCK_VAR(__disable_irq, mock, firstslot_required));
- }
- effective_primask = 1;
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK(LL_DMA_EnableIT_TC, mock, DMA_TypeDef *dma, uint32_t stream) {
- EXPECT_EQ(expectedDma, dma);
- EXPECT_EQ(expectedStream, stream);
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK(LL_DMA_EnableIT_TE, mock, DMA_TypeDef *dma, uint32_t stream) {
- EXPECT_EQ(expectedDma, dma);
- EXPECT_EQ(expectedStream, stream);
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK(LL_DMA_SetM2MDstAddress, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t address) {
- EXPECT_EQ(expectedDma, dma);
- EXPECT_EQ(expectedStream, stream);
- EXPECT_EQ(expectedDstAddress, address);
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK(LL_DMA_SetM2MSrcAddress, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t address) {
- EXPECT_EQ(expectedDma, dma);
- EXPECT_EQ(expectedStream, stream);
- EXPECT_EQ(expectedSrcAddress, address);
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK(LL_DMA_SetDataLength, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t length) {
- EXPECT_EQ(expectedDma, dma);
- EXPECT_EQ(expectedStream, stream);
- EXPECT_EQ(expectedLength, length);
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK(LL_DMA_EnableStream, mock, DMA_TypeDef *dma, uint32_t stream) {
- EXPECT_EQ(expectedDma, dma);
- EXPECT_EQ(expectedStream, stream);
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK(LL_DMA_DisableStream, mock, DMA_TypeDef *dma, uint32_t stream) {
- EXPECT_EQ(expectedDma, dma);
- EXPECT_EQ(expectedStream, stream);
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK(Crc_StartNextTask, mock, struct crcstatus_t *status) {
- EXPECT_EQ(status, &crcStatus);
- LEAVE_MOCK
-}
-
-void FakeCallback_1(void*, uint32_t, uint8_t) {}
-void FakeCallback_2(void*, uint32_t, uint8_t) {}
-void FakeCallback_3(void*, uint32_t, uint8_t) {}
-
-void FakeCallbackCheck(void* ptr, uint32_t crc, uint8_t success)
-{
- EXPECT_EQ(ptr, expectedCustomPtr);
- EXPECT_EQ(crc, expectedCrc);
- EXPECT_EQ(success, expectedSuccess);
-}
-
-DEFINE_MOCK(Dma_Init, mock, struct dmainfo_t * info, DMA_TypeDef *dma, uint32_t stream)
-{
- LEAVE_MOCK;
-}
-
-//////////////////////////////////////////////////////////////////////////////
-TEST(CrcScheduler, InitStatus)
-{
- expectedDma = DMA2;
- expectedStream = LL_DMA_STREAM_4;
- expectedDstAddress = (uint32_t)&fakeCrc;
- memset(&crcStatus, 0xff, sizeof(crcStatus));
-
- ACTIVATE_MOCK(LL_DMA_EnableIT_TC, mock);
- ACTIVATE_MOCK(LL_DMA_EnableIT_TE, mock);
- ACTIVATE_MOCK(LL_DMA_SetM2MDstAddress, mock);
- ACTIVATE_MOCK(Dma_Init, mock);
-
- Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
- EXPECT_EQ(crcStatus.crcUnit, &fakeCrc);
- EXPECT_EQ(crcStatus.activeSlot, nullptr);
- EXPECT_EQ(crcStatus.firstSlot, nullptr);
- EXPECT_EQ(MOCK_VAR(Dma_Init, mock, callcount), 1);
-}
-
-
-TEST(CrcScheduler, AttachTask_single)
-{
- DMA1 = &dma1;
- DMA2 = &dma2;
- effective_primask = 0;
- Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
- ACTIVATE_MOCK_RV(__get_PRIMASK, mock, 0);
- ACTIVATE_MOCK(__set_PRIMASK, mock);
- ACTIVATE_MOCK(__disable_irq, mock);
- MOCK_STORE(__disable_irq, mock, firstslot_required, nullptr);
-
- Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
-
- EXPECT_EQ(MOCK_CALLCOUNT(__get_PRIMASK, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(__set_PRIMASK, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(__disable_irq, mock), 1);
- EXPECT_EQ(crcStatus.firstSlot, &slot1);
- EXPECT_EQ(slot1.next, nullptr);
- EXPECT_EQ(slot1.count, 2);
- EXPECT_EQ(crcStatus.activeSlot, nullptr);
-}
-
-// Are tasks attached in the expected order internally
-TEST(CrcScheduler, AttachTask_multiple)
-{
- ACTIVATE_MOCK_RV(__get_PRIMASK, mock, 1);
- ACTIVATE_MOCK(__set_PRIMASK, mock);
- ACTIVATE_MOCK(__disable_irq, mock);
- MOCK_STORE(__disable_irq, mock, firstslot_required, nullptr);
- DMA1 = &dma1;
- DMA2 = &dma2;
- Crc_InitStatus(&crcStatus, NULL, DMA2, LL_DMA_STREAM_4);
-
- Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
- MOCK_STORE(__disable_irq, mock, firstslot_required, &slot1);
- Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
-
- EXPECT_EQ(MOCK_CALLCOUNT(__get_PRIMASK, mock), 2);
- EXPECT_EQ(MOCK_CALLCOUNT(__set_PRIMASK, mock), 2);
- EXPECT_EQ(MOCK_CALLCOUNT(__disable_irq, mock), 2);
- EXPECT_EQ(crcStatus.firstSlot, &slot2);
- EXPECT_EQ(slot2.next, &slot1);
- EXPECT_EQ(slot1.next, nullptr);
- EXPECT_EQ(slot2.count, 2);
- EXPECT_EQ(crcStatus.activeSlot, nullptr);
-}
-
-// No blocking should occur if the the task is not busy
-TEST(CrcScheduler, Enqueue_nowait)
-{
- uint32_t fakeCrcResult;
- uint8_t testData[] = "qwerty";
- expectedDma = DMA2;
- expectedStream = LL_DMA_STREAM_4;
- expectedSrcAddress = (uint32_t)testData;
-
- memset(tasks1, 0, sizeof(tasks1));
- memset(&fakeCrc, 0, sizeof(fakeCrc));
-
- Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
- Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
- expectedLength = 2;
-
- ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
- ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
- ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
-
- EXPECT_TRUE(Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult));
-
- //first task should be picked up before return;
- EXPECT_EQ(slot1.tasks[0].address, nullptr);
- EXPECT_EQ((uintptr_t)slot1.tasks[0].callback, (uintptr_t)FakeCallback_1);
- EXPECT_EQ(MOCK_VAR(LL_DMA_SetM2MSrcAddress, mock, callcount), 1);
- EXPECT_EQ(MOCK_VAR(LL_DMA_SetDataLength, mock, callcount), 1);
- EXPECT_EQ(MOCK_VAR(LL_DMA_EnableStream, mock, callcount), 1);
-
- EXPECT_FALSE(Crc_Enqueue(&crcStatus, &slot1, 1, testData, 4, FakeCallback_1, &fakeCrcResult));
-
- // second task should be queued
- EXPECT_EQ(slot1.tasks[1].address, testData);
- EXPECT_EQ((uintptr_t)slot1.tasks[1].callback, (uintptr_t)FakeCallback_1);
- EXPECT_EQ(slot1.tasks[1].wordCount, 1);
-
- // should be no new calls to hardware handling functions
- EXPECT_EQ(MOCK_VAR(LL_DMA_SetM2MSrcAddress, mock, callcount), 1);
- EXPECT_EQ(MOCK_VAR(LL_DMA_SetDataLength, mock, callcount), 1);
- EXPECT_EQ(MOCK_VAR(LL_DMA_EnableStream, mock, callcount), 1);
-}
-
-// When trying to enqueue for a busy task it should blok firs
-// then when the previously blocked task finishes it should
-// enqueue the new one
-TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
-{
- uint8_t testData[] = "qwerty";
- uint32_t fakeCrcResult;
-
- memset(tasks1, 0, sizeof(tasks1));
- memset(&fakeCrc, 0, sizeof(fakeCrc));
-
- Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
- Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
- Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult);
-
- // black magic to test if the function blocks (at least for 100ms)
- std::promise promisedFinished;
- auto futureResult = promisedFinished.get_future();
- pthread_t th;
- std::thread t([&testData](std::promise& finished) {
- pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS,NULL);
- Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, nullptr);
- finished.set_value(true);
- }, std::ref(promisedFinished));
- th = t.native_handle();
- t.detach();
- EXPECT_EQ(futureResult.wait_for(std::chrono::milliseconds(100)), std::future_status::timeout);
- tasks1[0].callback = nullptr;
- tasks1[0].callbackParam = nullptr;
- auto waitResult(futureResult.wait_for(std::chrono::milliseconds(100)));
- EXPECT_NE(waitResult, std::future_status::timeout);
- if(waitResult == std::future_status::timeout)
- pthread_cancel(th);
-}
-
-// StartNextTask should start the scheduled tasks in predefined order
-TEST(CrcScheduler, Crc_StartNextTask)
-{
- uint8_t testData[] = "qwerty";
- uint32_t fakeCrcResult1, fakeCrcResult2, fakeCrcResult3;
-
- memset(tasks1, 0, sizeof(tasks1));
- memset(tasks2, 0, sizeof(tasks2));
- memset(&fakeCrc, 0, sizeof(fakeCrc));
-
- Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
- Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
- Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
- Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult1);
- Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_2, &fakeCrcResult2);
- Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallback_3, &fakeCrcResult3);
-
- EXPECT_EQ(crcStatus.activeSlot, &slot1);
- EXPECT_EQ(crcStatus.activeTask, 0);
- crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
- crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
-
- ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
- ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
- ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
-
- expectedDma = DMA2;
- expectedStream = LL_DMA_STREAM_4;
- expectedSrcAddress = (uint32_t)testData;
- expectedLength = (sizeof(testData) + 3) / 4;
-
- Crc_StartNextTask(&crcStatus);
-
- EXPECT_EQ(crcStatus.activeSlot, &slot2);
- EXPECT_EQ(crcStatus.activeTask, 0);
- EXPECT_EQ(LL_DMA_SetM2MSrcAddress_mock_callcount, 1);
- EXPECT_EQ(LL_DMA_SetDataLength_mock_callcount, 1);
- EXPECT_EQ(LL_DMA_EnableStream_mock_callcount, 1);
- crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
- crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
-
- Crc_StartNextTask(&crcStatus);
-
- EXPECT_EQ(crcStatus.activeSlot, &slot1);
- EXPECT_EQ(crcStatus.activeTask, 1);
- EXPECT_EQ(LL_DMA_SetM2MSrcAddress_mock_callcount, 2);
- EXPECT_EQ(LL_DMA_SetDataLength_mock_callcount, 2);
- EXPECT_EQ(LL_DMA_EnableStream_mock_callcount, 2);
-}
-
-// HandleDmaIrq should start the next scheduled task or
-// disable the CRC DMA engine if there is no other task scheduled.
-TEST(CrcScheduler, HandleDmaIrq_callback)
-{
- uint8_t testData[] = "qwerty";
- uint32_t FakeCustomData1, FakeCustomData2;
-
-
- memset(tasks1, 0, sizeof(tasks1));
- memset(tasks2, 0, sizeof(tasks2));
- memset(&fakeCrc, 0, sizeof(fakeCrc));
-
- fakeCrc.DR = 0xa5a55a5a;
-
- Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
- Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
- Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
- Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData1);
- // we need to set this up here to check if HandleDmaIrq calls Crc_StartNextTask or not;
- Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData2);
-
- ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
- ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
- ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
- ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
- ACTIVATE_MOCK(Crc_StartNextTask, mock);
-
- expectedDma = DMA2;
- expectedStream = LL_DMA_STREAM_4;
-
- expectedCustomPtr = &FakeCustomData1;
- expectedCrc = fakeCrc.DR;
- expectedSuccess = 1;
-
- DMA2->HISR |= DMA_HISR_TCIF4;
- DMA2->HIFCR = 0;
-
- Crc_HandleDmaIrq(&crcStatus);
-
- EXPECT_EQ(LL_DMA_DisableStream_mock_callcount, 1);
-
- EXPECT_EQ(DMA2->HIFCR & DMA_HIFCR_CTCIF4, DMA_HIFCR_CTCIF4);
-
- expectedCustomPtr = &FakeCustomData2;
- DMA2->HISR |= DMA_HISR_TCIF4 | DMA_HISR_TEIF4;
- DMA2->HIFCR = 0;
- crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
- crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
-
- Crc_HandleDmaIrq(&crcStatus);
-
- EXPECT_EQ(DMA2->HIFCR & (DMA_HIFCR_CTCIF4 | DMA_HIFCR_CTEIF4), DMA_HIFCR_CTCIF4 | DMA_HIFCR_CTEIF4);
- EXPECT_EQ(LL_DMA_DisableStream_mock_callcount, 2);
-}
-
-// Crc_StartNextTask starts executing the next task and removes it from the queue
-// Test if IsTaskQueued reflects this behaviour correctly
-TEST(CrcScheduler, IsTaskQueued)
-{
- uint8_t testData[] = "qwerty";
- uint32_t FakeCustomData1;
-
- Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
- Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
- Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
- Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
-
- EXPECT_EQ(Crc_IsTaskQueued(&slot1, 0), 0);
- EXPECT_NE(Crc_IsTaskQueued(&slot1, 1), 0);
-
- Crc_StartNextTask(&crcStatus);
-
- EXPECT_EQ(Crc_IsTaskQueued(&slot1, 1), 0);
-}
-
-// Crc_HandleDmaIrq completes the active task and start executing the next (by calling StartNextTask)
-// Crc_IsTaskBusy should reflect these changes
-TEST(CrcScheduler, IsTaskBusy)
-{
- uint8_t testData[] = "qwerty";
- uint32_t FakeCustomData1;
-
- Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
- Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
- Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
- Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
-
- EXPECT_NE(Crc_IsTaskBusy(&slot1, 0), 0);
- EXPECT_NE(Crc_IsTaskBusy(&slot1, 1), 0);
-
- DMA2->HISR |= DMA_HISR_TCIF4;
- Crc_HandleDmaIrq(&crcStatus);
-
- EXPECT_EQ(Crc_IsTaskBusy(&slot1, 0), 0);
- EXPECT_NE(Crc_IsTaskBusy(&slot1, 1), 0);
-
- DMA2->HISR |= DMA_HISR_TCIF4;
- Crc_HandleDmaIrq(&crcStatus);
-
- EXPECT_EQ(Crc_IsTaskBusy(&slot1, 0), 0);
- EXPECT_EQ(Crc_IsTaskBusy(&slot1, 1), 0);
-}
+//
+//DMA_TypeDef * DMA1 __attribute__((weak));
+//DMA_TypeDef * DMA2 __attribute__((weak));
+//
+//static DMA_TypeDef dma1, dma2;
+//static crcstatus_t crcStatus;
+//static crcslot_t slot1, slot2;
+//static crctask_t tasks1[2], tasks2[2];
+//static CRC_TypeDef fakeCrc;
+//
+//static DMA_TypeDef *expectedDma;
+//static uint32_t expectedStream;
+//static uint32_t expectedSrcAddress;
+//static uint32_t expectedDstAddress;
+//static uint32_t expectedLength;
+//static void *expectedCustomPtr;
+//static uint8_t expectedSuccess;
+//static uint32_t expectedCrc;
+//
+////////////////////////////////////////////////////////////////////////////////
+//uint32_t effective_primask = 0;
+//
+//DEFINE_MOCK(__set_PRIMASK, mock, uint32_t primask) {
+// effective_primask = primask;
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK_RET(uint32_t, __get_PRIMASK, mock) {
+// RETURN_MOCK(__get_PRIMASK, mock, effective_primask);
+//}
+//
+//DEFINE_MOCK_VAR(crcslot_t *, __disable_irq, mock, firstslot_required);
+//DEFINE_MOCK(__disable_irq, mock) {
+// if(MOCK_CALLCOUNT(__disable_irq, mock) < 2) {
+// EXPECT_EQ(crcStatus.firstSlot, MOCK_VAR(__disable_irq, mock, firstslot_required));
+// }
+// effective_primask = 1;
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK(LL_DMA_EnableIT_TC, mock, DMA_TypeDef *dma, uint32_t stream) {
+// EXPECT_EQ(expectedDma, dma);
+// EXPECT_EQ(expectedStream, stream);
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK(LL_DMA_EnableIT_TE, mock, DMA_TypeDef *dma, uint32_t stream) {
+// EXPECT_EQ(expectedDma, dma);
+// EXPECT_EQ(expectedStream, stream);
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK(LL_DMA_SetM2MDstAddress, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t address) {
+// EXPECT_EQ(expectedDma, dma);
+// EXPECT_EQ(expectedStream, stream);
+// EXPECT_EQ(expectedDstAddress, address);
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK(LL_DMA_SetM2MSrcAddress, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t address) {
+// EXPECT_EQ(expectedDma, dma);
+// EXPECT_EQ(expectedStream, stream);
+// EXPECT_EQ(expectedSrcAddress, address);
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK(LL_DMA_SetDataLength, mock, DMA_TypeDef *dma, uint32_t stream, uint32_t length) {
+// EXPECT_EQ(expectedDma, dma);
+// EXPECT_EQ(expectedStream, stream);
+// EXPECT_EQ(expectedLength, length);
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK(LL_DMA_EnableStream, mock, DMA_TypeDef *dma, uint32_t stream) {
+// EXPECT_EQ(expectedDma, dma);
+// EXPECT_EQ(expectedStream, stream);
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK(LL_DMA_DisableStream, mock, DMA_TypeDef *dma, uint32_t stream) {
+// EXPECT_EQ(expectedDma, dma);
+// EXPECT_EQ(expectedStream, stream);
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK(Crc_StartNextTask, mock, struct crcstatus_t *status) {
+// EXPECT_EQ(status, &crcStatus);
+// LEAVE_MOCK
+//}
+//
+//void FakeCallback_1(void*, uint32_t, uint8_t) {}
+//void FakeCallback_2(void*, uint32_t, uint8_t) {}
+//void FakeCallback_3(void*, uint32_t, uint8_t) {}
+//
+//void FakeCallbackCheck(void* ptr, uint32_t crc, uint8_t success)
+//{
+// EXPECT_EQ(ptr, expectedCustomPtr);
+// EXPECT_EQ(crc, expectedCrc);
+// EXPECT_EQ(success, expectedSuccess);
+//}
+//
+//DEFINE_MOCK(Dma_Init, mock, struct dmainfo_t * info, DMA_TypeDef *dma, uint32_t stream)
+//{
+// LEAVE_MOCK;
+//}
+//
+////////////////////////////////////////////////////////////////////////////////
+//TEST(CrcScheduler, InitStatus)
+//{
+// expectedDma = DMA2;
+// expectedStream = LL_DMA_STREAM_4;
+// expectedDstAddress = (uint32_t)&fakeCrc;
+// memset(&crcStatus, 0xff, sizeof(crcStatus));
+//
+// ACTIVATE_MOCK(LL_DMA_EnableIT_TC, mock);
+// ACTIVATE_MOCK(LL_DMA_EnableIT_TE, mock);
+// ACTIVATE_MOCK(LL_DMA_SetM2MDstAddress, mock);
+// ACTIVATE_MOCK(Dma_Init, mock);
+//
+// Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
+// EXPECT_EQ(crcStatus.crcUnit, &fakeCrc);
+// EXPECT_EQ(crcStatus.activeSlot, nullptr);
+// EXPECT_EQ(crcStatus.firstSlot, nullptr);
+// EXPECT_EQ(MOCK_VAR(Dma_Init, mock, callcount), 1);
+//}
+//
+//
+//TEST(CrcScheduler, AttachTask_single)
+//{
+// DMA1 = &dma1;
+// DMA2 = &dma2;
+// effective_primask = 0;
+// Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
+// ACTIVATE_MOCK_RV(__get_PRIMASK, mock, 0);
+// ACTIVATE_MOCK(__set_PRIMASK, mock);
+// ACTIVATE_MOCK(__disable_irq, mock);
+// MOCK_STORE(__disable_irq, mock, firstslot_required, nullptr);
+//
+// Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(__get_PRIMASK, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(__set_PRIMASK, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(__disable_irq, mock), 1);
+// EXPECT_EQ(crcStatus.firstSlot, &slot1);
+// EXPECT_EQ(slot1.next, nullptr);
+// EXPECT_EQ(slot1.count, 2);
+// EXPECT_EQ(crcStatus.activeSlot, nullptr);
+//}
+//
+//// Are tasks attached in the expected order internally
+//TEST(CrcScheduler, AttachTask_multiple)
+//{
+// ACTIVATE_MOCK_RV(__get_PRIMASK, mock, 1);
+// ACTIVATE_MOCK(__set_PRIMASK, mock);
+// ACTIVATE_MOCK(__disable_irq, mock);
+// MOCK_STORE(__disable_irq, mock, firstslot_required, nullptr);
+// DMA1 = &dma1;
+// DMA2 = &dma2;
+// Crc_InitStatus(&crcStatus, NULL, DMA2, LL_DMA_STREAM_4);
+//
+// Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
+// MOCK_STORE(__disable_irq, mock, firstslot_required, &slot1);
+// Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(__get_PRIMASK, mock), 2);
+// EXPECT_EQ(MOCK_CALLCOUNT(__set_PRIMASK, mock), 2);
+// EXPECT_EQ(MOCK_CALLCOUNT(__disable_irq, mock), 2);
+// EXPECT_EQ(crcStatus.firstSlot, &slot2);
+// EXPECT_EQ(slot2.next, &slot1);
+// EXPECT_EQ(slot1.next, nullptr);
+// EXPECT_EQ(slot2.count, 2);
+// EXPECT_EQ(crcStatus.activeSlot, nullptr);
+//}
+//
+//// No blocking should occur if the the task is not busy
+//TEST(CrcScheduler, Enqueue_nowait)
+//{
+// uint32_t fakeCrcResult;
+// uint8_t testData[] = "qwerty";
+// expectedDma = DMA2;
+// expectedStream = LL_DMA_STREAM_4;
+// expectedSrcAddress = (uint32_t)testData;
+//
+// memset(tasks1, 0, sizeof(tasks1));
+// memset(&fakeCrc, 0, sizeof(fakeCrc));
+//
+// Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
+// Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
+// expectedLength = 2;
+//
+// ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
+// ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
+// ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
+//
+// EXPECT_TRUE(Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult));
+//
+// //first task should be picked up before return;
+// EXPECT_EQ(slot1.tasks[0].address, nullptr);
+// EXPECT_EQ((uintptr_t)slot1.tasks[0].callback, (uintptr_t)FakeCallback_1);
+// EXPECT_EQ(MOCK_VAR(LL_DMA_SetM2MSrcAddress, mock, callcount), 1);
+// EXPECT_EQ(MOCK_VAR(LL_DMA_SetDataLength, mock, callcount), 1);
+// EXPECT_EQ(MOCK_VAR(LL_DMA_EnableStream, mock, callcount), 1);
+//
+// EXPECT_FALSE(Crc_Enqueue(&crcStatus, &slot1, 1, testData, 4, FakeCallback_1, &fakeCrcResult));
+//
+// // second task should be queued
+// EXPECT_EQ(slot1.tasks[1].address, testData);
+// EXPECT_EQ((uintptr_t)slot1.tasks[1].callback, (uintptr_t)FakeCallback_1);
+// EXPECT_EQ(slot1.tasks[1].wordCount, 1);
+//
+// // should be no new calls to hardware handling functions
+// EXPECT_EQ(MOCK_VAR(LL_DMA_SetM2MSrcAddress, mock, callcount), 1);
+// EXPECT_EQ(MOCK_VAR(LL_DMA_SetDataLength, mock, callcount), 1);
+// EXPECT_EQ(MOCK_VAR(LL_DMA_EnableStream, mock, callcount), 1);
+//}
+//
+//// When trying to enqueue for a busy task it should blok firs
+//// then when the previously blocked task finishes it should
+//// enqueue the new one
+//TEST(CrcScheduler, Enqueue_shouldblockthencontinue)
+//{
+// uint8_t testData[] = "qwerty";
+// uint32_t fakeCrcResult;
+//
+// memset(tasks1, 0, sizeof(tasks1));
+// memset(&fakeCrc, 0, sizeof(fakeCrc));
+//
+// Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
+// Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
+// Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult);
+//
+// // black magic to test if the function blocks (at least for 100ms)
+// std::promise promisedFinished;
+// auto futureResult = promisedFinished.get_future();
+// pthread_t th;
+// std::thread t([&testData](std::promise& finished) {
+// pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS,NULL);
+// Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, nullptr);
+// finished.set_value(true);
+// }, std::ref(promisedFinished));
+// th = t.native_handle();
+// t.detach();
+// EXPECT_EQ(futureResult.wait_for(std::chrono::milliseconds(100)), std::future_status::timeout);
+// tasks1[0].callback = nullptr;
+// tasks1[0].callbackParam = nullptr;
+// auto waitResult(futureResult.wait_for(std::chrono::milliseconds(100)));
+// EXPECT_NE(waitResult, std::future_status::timeout);
+// if(waitResult == std::future_status::timeout)
+// pthread_cancel(th);
+//}
+//
+//// StartNextTask should start the scheduled tasks in predefined order
+//TEST(CrcScheduler, Crc_StartNextTask)
+//{
+// uint8_t testData[] = "qwerty";
+// uint32_t fakeCrcResult1, fakeCrcResult2, fakeCrcResult3;
+//
+// memset(tasks1, 0, sizeof(tasks1));
+// memset(tasks2, 0, sizeof(tasks2));
+// memset(&fakeCrc, 0, sizeof(fakeCrc));
+//
+// Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
+// Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
+// Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
+// Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &fakeCrcResult1);
+// Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_2, &fakeCrcResult2);
+// Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallback_3, &fakeCrcResult3);
+//
+// EXPECT_EQ(crcStatus.activeSlot, &slot1);
+// EXPECT_EQ(crcStatus.activeTask, 0);
+// crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
+// crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
+//
+// ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
+// ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
+// ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
+//
+// expectedDma = DMA2;
+// expectedStream = LL_DMA_STREAM_4;
+// expectedSrcAddress = (uint32_t)testData;
+// expectedLength = (sizeof(testData) + 3) / 4;
+//
+// Crc_StartNextTask(&crcStatus);
+//
+// EXPECT_EQ(crcStatus.activeSlot, &slot2);
+// EXPECT_EQ(crcStatus.activeTask, 0);
+// EXPECT_EQ(LL_DMA_SetM2MSrcAddress_mock_callcount, 1);
+// EXPECT_EQ(LL_DMA_SetDataLength_mock_callcount, 1);
+// EXPECT_EQ(LL_DMA_EnableStream_mock_callcount, 1);
+// crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
+// crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
+//
+// Crc_StartNextTask(&crcStatus);
+//
+// EXPECT_EQ(crcStatus.activeSlot, &slot1);
+// EXPECT_EQ(crcStatus.activeTask, 1);
+// EXPECT_EQ(LL_DMA_SetM2MSrcAddress_mock_callcount, 2);
+// EXPECT_EQ(LL_DMA_SetDataLength_mock_callcount, 2);
+// EXPECT_EQ(LL_DMA_EnableStream_mock_callcount, 2);
+//}
+//
+//// HandleDmaIrq should start the next scheduled task or
+//// disable the CRC DMA engine if there is no other task scheduled.
+//TEST(CrcScheduler, HandleDmaIrq_callback)
+//{
+// uint8_t testData[] = "qwerty";
+// uint32_t FakeCustomData1, FakeCustomData2;
+//
+//
+// memset(tasks1, 0, sizeof(tasks1));
+// memset(tasks2, 0, sizeof(tasks2));
+// memset(&fakeCrc, 0, sizeof(fakeCrc));
+//
+// fakeCrc.DR = 0xa5a55a5a;
+//
+// Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
+// Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
+// Crc_AttachTasks(&crcStatus, &slot2, tasks2, 2);
+// Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData1);
+// // we need to set this up here to check if HandleDmaIrq calls Crc_StartNextTask or not;
+// Crc_Enqueue(&crcStatus, &slot2, 0, testData, sizeof(testData), FakeCallbackCheck, &FakeCustomData2);
+//
+// ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
+// ACTIVATE_MOCK(LL_DMA_SetM2MSrcAddress, mock);
+// ACTIVATE_MOCK(LL_DMA_SetDataLength, mock);
+// ACTIVATE_MOCK(LL_DMA_EnableStream, mock);
+// ACTIVATE_MOCK(Crc_StartNextTask, mock);
+//
+// expectedDma = DMA2;
+// expectedStream = LL_DMA_STREAM_4;
+//
+// expectedCustomPtr = &FakeCustomData1;
+// expectedCrc = fakeCrc.DR;
+// expectedSuccess = 1;
+//
+// DMA2->HISR |= DMA_HISR_TCIF4;
+// DMA2->HIFCR = 0;
+//
+// Crc_HandleDmaIrq(&crcStatus);
+//
+// EXPECT_EQ(LL_DMA_DisableStream_mock_callcount, 1);
+//
+// EXPECT_EQ(DMA2->HIFCR & DMA_HIFCR_CTCIF4, DMA_HIFCR_CTCIF4);
+//
+// expectedCustomPtr = &FakeCustomData2;
+// DMA2->HISR |= DMA_HISR_TCIF4 | DMA_HISR_TEIF4;
+// DMA2->HIFCR = 0;
+// crcStatus.activeSlot->tasks[crcStatus.activeTask].callback = nullptr;
+// crcStatus.activeSlot->tasks[crcStatus.activeTask].callbackParam = nullptr;
+//
+// Crc_HandleDmaIrq(&crcStatus);
+//
+// EXPECT_EQ(DMA2->HIFCR & (DMA_HIFCR_CTCIF4 | DMA_HIFCR_CTEIF4), DMA_HIFCR_CTCIF4 | DMA_HIFCR_CTEIF4);
+// EXPECT_EQ(LL_DMA_DisableStream_mock_callcount, 2);
+//}
+//
+//// Crc_StartNextTask starts executing the next task and removes it from the queue
+//// Test if IsTaskQueued reflects this behaviour correctly
+//TEST(CrcScheduler, IsTaskQueued)
+//{
+// uint8_t testData[] = "qwerty";
+// uint32_t FakeCustomData1;
+//
+// Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
+// Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
+// Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
+// Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
+//
+// EXPECT_EQ(Crc_IsTaskQueued(&slot1, 0), 0);
+// EXPECT_NE(Crc_IsTaskQueued(&slot1, 1), 0);
+//
+// Crc_StartNextTask(&crcStatus);
+//
+// EXPECT_EQ(Crc_IsTaskQueued(&slot1, 1), 0);
+//}
+//
+//// Crc_HandleDmaIrq completes the active task and start executing the next (by calling StartNextTask)
+//// Crc_IsTaskBusy should reflect these changes
+//TEST(CrcScheduler, IsTaskBusy)
+//{
+// uint8_t testData[] = "qwerty";
+// uint32_t FakeCustomData1;
+//
+// Crc_InitStatus(&crcStatus, &fakeCrc, DMA2, LL_DMA_STREAM_4);
+// Crc_AttachTasks(&crcStatus, &slot1, tasks1, 2);
+// Crc_Enqueue(&crcStatus, &slot1, 0, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
+// Crc_Enqueue(&crcStatus, &slot1, 1, testData, sizeof(testData), FakeCallback_1, &FakeCustomData1);
+//
+// EXPECT_NE(Crc_IsTaskBusy(&slot1, 0), 0);
+// EXPECT_NE(Crc_IsTaskBusy(&slot1, 1), 0);
+//
+// DMA2->HISR |= DMA_HISR_TCIF4;
+// Crc_HandleDmaIrq(&crcStatus);
+//
+// EXPECT_EQ(Crc_IsTaskBusy(&slot1, 0), 0);
+// EXPECT_NE(Crc_IsTaskBusy(&slot1, 1), 0);
+//
+// DMA2->HISR |= DMA_HISR_TCIF4;
+// Crc_HandleDmaIrq(&crcStatus);
+//
+// EXPECT_EQ(Crc_IsTaskBusy(&slot1, 0), 0);
+// EXPECT_EQ(Crc_IsTaskBusy(&slot1, 1), 0);
+//}
+//
diff --git a/components/f4ll_c/test/packetusart_unittest.cpp b/components/f4ll_c/test/packetusart_unittest.cpp
index 225f4ee..790cccd 100644
--- a/components/f4ll_c/test/packetusart_unittest.cpp
+++ b/components/f4ll_c/test/packetusart_unittest.cpp
@@ -6,737 +6,741 @@
*/
#include
#include
-#include
-#include
-#include
-#include
#include
#include
-static inline uint32_t RoundUpTo4(uint32_t inp)
-{
- return (inp + 3) & 0xfffc;
-}
-
-DMA_TypeDef* DMA1 __attribute__((weak));
-DMA_TypeDef* DMA2 __attribute__((weak));
-
-static DMA_TypeDef fakeDma1, fakeDma2;
-static CRC_TypeDef fakeCrc;
-static USART_TypeDef fakeUsart;
-
-static struct usartstatus_t usartStatus;
-static struct crcstatus_t crcStatus;
-
-uint8_t testData[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
-
-//static uint32_t expected_stream;
-//static uint32_t expected_srcaddress;
-//static uint32_t expected_dstaddress;
-//static uint32_t expected_length;
-//static void *expected_customptr;
-//static uint8_t expected_success;
-//static struct usartstatus_t * expectedUsartStatus;
-static uint32_t expectedStreams[2] = { 0,7 };
-struct crcstatus_t *expectedCrcStatus;
-struct crcslot_t *expectedCrcSlotListItem;
-struct crctask_t *expectedTasks;
-uint8_t expectedTaskCount;
-uint32_t expectedCrcLength;
-uint32_t expectedLength;
-void* expectedCrcEnqueueAddress;
-void *expectedTransmitBuffer;
-
-static uint32_t expectedStream;
-uint32_t expectedSrcAddress;
-uint32_t expectedDstAddress;
-uint32_t expectedDirection;
-
-uint32_t fakePacketReceivedCallbackParam;
-
-
-// this isn't a real mov but we use the mockinginfrastructure
-// to automate administration (call count, etc)
-DEFINE_MOCK(FakePacketReceivedCallback, mock, void* userParam, struct usart_buffer_t *buffer)
-{
- EXPECT_EQ((void*)&fakePacketReceivedCallbackParam, userParam);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(Dma_Init, mock, struct dmainfo_t* dmaInfo, DMA_TypeDef *dma, uint32_t stream)
-{
- Dma_Init__(dmaInfo, dma, stream);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(Crc_AttachTasks, mock, struct crcstatus_t *status, struct crcslot_t *slot, struct crctask_t *tasks, uint8_t taskCount)
-{
- EXPECT_EQ(status, expectedCrcStatus);
- EXPECT_EQ(slot, expectedCrcSlotListItem);
- EXPECT_EQ(tasks, expectedTasks);
- EXPECT_EQ(taskCount, expectedTaskCount);
- Crc_AttachTasks__(status, slot, tasks, taskCount);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_DMA_EnableIT_TC, init, DMA_TypeDef *dma, uint32_t stream)
-{
- EXPECT_EQ(dma, &fakeDma1);
- EXPECT_EQ(stream, expectedStreams[MOCK_VAR(LL_DMA_EnableIT_TC, init, callcount)-1]);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_DMA_EnableIT_TE, init, DMA_TypeDef *dma, uint32_t stream)
-{
- EXPECT_EQ(dma, &fakeDma1);
- EXPECT_EQ(stream, expectedStreams[MOCK_VAR(LL_DMA_EnableIT_TE, init, callcount)-1]);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK_RET(uint32_t, LL_USART_DMA_GetRegAddr, mock, USART_TypeDef *usart)
-{
- RETURN_MOCK_PREDEF(LL_USART_DMA_GetRegAddr, mock)
-}
-
-DEFINE_MOCK(LL_DMA_ConfigAddresses, mock, DMA_TypeDef* dma, uint32_t stream, uint32_t srcAddress, uint32_t dstAddress, uint32_t direction)
-{
- EXPECT_EQ(dma, &fakeDma1);
- EXPECT_EQ(stream, expectedStream);
- EXPECT_EQ(srcAddress, expectedSrcAddress);
- EXPECT_EQ(dstAddress, expectedDstAddress);
- EXPECT_EQ(direction, expectedDirection);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_DMA_SetDataLength, mock, DMA_TypeDef* dma, uint32_t stream, uint32_t length)
-{
- EXPECT_EQ(dma, &fakeDma1);
- EXPECT_EQ(stream, expectedStream);
- EXPECT_EQ(length, expectedLength);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK_RET(uint32_t, LL_DMA_GetDataLength, mock, DMA_TypeDef* dma, uint32_t stream)
-{
- EXPECT_EQ(dma, &fakeDma1);
- EXPECT_EQ(stream, expectedStream);
- RETURN_MOCK_PREDEF(LL_DMA_GetDataLength, mock)
-}
-
-DEFINE_MOCK(LL_DMA_EnableStream, mock, DMA_TypeDef* dma, uint32_t stream)
-{
- EXPECT_EQ(dma, &fakeDma1);
- EXPECT_EQ(stream, expectedStream);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_DMA_DisableStream, mock, DMA_TypeDef* dma, uint32_t stream)
-{
- EXPECT_EQ(dma, &fakeDma1);
- EXPECT_EQ(stream, expectedStream);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_USART_EnableDMAReq_TX, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_USART_EnableDMAReq_RX, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_USART_EnableIT_IDLE, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_USART_EnableIT_TC, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_USART_DisableIT_TC, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK_RET(uint32_t, LL_USART_IsActiveFlag_IDLE, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- RETURN_MOCK_PREDEF(LL_USART_IsActiveFlag_IDLE, mock)
-}
-
-DEFINE_MOCK_RET(uint32_t, LL_USART_IsActiveFlag_TC, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- RETURN_MOCK_PREDEF(LL_USART_IsActiveFlag_TC, mock)
-}
-
-DEFINE_MOCK(LL_USART_ClearFlag_IDLE, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK;
-}
-
-DEFINE_MOCK_RET(uint32_t, LL_USART_IsEnabledIT_IDLE, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- RETURN_MOCK_PREDEF(LL_USART_IsEnabledIT_IDLE, mock)
-}
-
-DEFINE_MOCK_RET(uint32_t, LL_USART_IsEnabledIT_TC, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- RETURN_MOCK_PREDEF(LL_USART_IsEnabledIT_TC, mock)
-}
-
-DEFINE_MOCK(LL_USART_EnableDirectionTx, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_USART_DisableDirectionTx, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK(LL_USART_ClearFlag_ORE, mock, USART_TypeDef *usart)
-{
- EXPECT_EQ(usart, &fakeUsart);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK_RET(uint8_t, Crc_Enqueue, mock, struct crcstatus_t *status, struct crcslot_t *slot, uint8_t task,
- void *address, uint16_t len, void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
-{
- EXPECT_EQ(expectedCrcLength, len);
- EXPECT_EQ(expectedCrcEnqueueAddress, address);
- RETURN_MOCK_PREDEF(Crc_Enqueue, mock);
-}
-
-DEFINE_MOCK_RET(uint8_t, Crc_IsTaskQueued, mock, struct crcslot_t *slot, uint8_t task)
-{
- RETURN_MOCK_PREDEF(Crc_IsTaskQueued, mock);
-}
-
-DEFINE_MOCK(Pu_SetupTransmit, mock, USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
-{
- EXPECT_EQ(buffer, expectedTransmitBuffer);
- EXPECT_EQ(length, expectedLength);
- LEAVE_MOCK
-}
-
-DEFINE_MOCK_RET(uint8_t, Pu_CheckHeader, proxy, struct usartpacket_t *packet)
-{
- RETURN_MOCK(Pu_CheckHeader, proxy, Pu_CheckHeader__(packet));
-}
-
-DEFINE_MOCK(Pu_SetupReceive, mock, struct usartstatus_t *status)
-{
- LEAVE_MOCK
-}
-
-struct PacketUsart : public ::testing::Test {
- void SetUp()
- {
- DMA1 = &fakeDma1;
- DMA2 = &fakeDma2;
-
- memset(&usartStatus, 0x5a, sizeof(usartStatus));
- Crc_InitStatus(&crcStatus, &fakeCrc, &fakeDma2, 4);
-
- expectedCrcStatus = &crcStatus;
- expectedCrcSlotListItem = &usartStatus.crcSlot;
- expectedTasks = usartStatus.crcTasks;
- expectedTaskCount = 2;
- }
-};
-
-//////////////////////////////////////////////////////////////////////////////
-TEST_F(PacketUsart, Init)
-{
- ACTIVATE_MOCK(Dma_Init, mock);
- ACTIVATE_MOCK(Crc_AttachTasks, mock);
- ACTIVATE_MOCK(LL_DMA_EnableIT_TC, init);
- ACTIVATE_MOCK(LL_DMA_EnableIT_TE, init);
- ACTIVATE_MOCK(LL_USART_EnableIT_IDLE, mock);
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
-
- EXPECT_EQ(fakeDma1.LIFCR, DMA_LISR_TCIF0 | DMA_LISR_HTIF0 | DMA_LISR_TEIF0 | DMA_LISR_FEIF0 | DMA_LISR_DMEIF0);
- EXPECT_EQ(fakeDma1.HIFCR, DMA_HISR_TCIF7 | DMA_HISR_HTIF7 | DMA_HISR_TEIF7 | DMA_HISR_FEIF7 | DMA_HISR_DMEIF7);
- EXPECT_EQ(MOCK_CALLCOUNT(Dma_Init, mock), 2);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableIT_TC, init), 2);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableIT_TE, init), 2);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_IDLE, mock), 1);
- EXPECT_EQ(usartStatus.usart, &fakeUsart);
- EXPECT_EQ(usartStatus.txBuffer.usartStatus, &usartStatus);
- EXPECT_EQ(usartStatus.txBuffer.busy, 0);
- EXPECT_EQ(usartStatus.txBuffer.error, 0);
- EXPECT_EQ(usartStatus.txBuffer.requestedLength, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].requestedLength, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].usartStatus, &usartStatus );
- EXPECT_EQ(usartStatus.rxBuffers[1].busy, 0);
- EXPECT_EQ(usartStatus.rxBuffers[1].error, 0);
- EXPECT_EQ(usartStatus.rxBuffers[1].requestedLength, 0);
- EXPECT_EQ(usartStatus.rxBuffers[1].usartStatus, &usartStatus );
- EXPECT_TRUE(usartStatus.packetReceivedCallback == FakePacketReceivedCallback_mock);
- EXPECT_EQ(usartStatus.packetReceivedCallbackParam, &fakePacketReceivedCallbackParam);
- EXPECT_EQ(usartStatus.rxSerial, (uint8_t)-1);
- EXPECT_EQ(usartStatus.txSerial, 0);
- EXPECT_EQ(usartStatus.activeRxBuf, 0);
- EXPECT_EQ(usartStatus.crcStatus, &crcStatus);
-}
-
-TEST_F(PacketUsart, GetTxBuffer)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- EXPECT_EQ(Pu_GetTxBuffer(&usartStatus), (unsigned char*)&usartStatus.txBuffer.packet.payload);
-}
-
-// SetupTransmit should set all engines (DMA, USART) up properly for starting the transmission
-TEST_F(PacketUsart, SetupTransmit)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- expectedStream = 7;
- expectedSrcAddress = (uint32_t)testData;
- expectedDstAddress = (uint32_t)&fakeUsart.DR;
- expectedDirection = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
- expectedLength = sizeof(testData);
-
- ACTIVATE_MOCK(LL_DMA_ConfigAddresses, mock);
- ACTIVATE_MOCK(LL_DMA_SetDataLength , mock);
- ACTIVATE_MOCK(LL_DMA_EnableStream , mock);
- ACTIVATE_MOCK(LL_USART_EnableDMAReq_TX, mock);
- ACTIVATE_MOCK_RV(LL_USART_DMA_GetRegAddr, mock, expectedDstAddress);
-
- Pu_SetupTransmit(&fakeUsart, &fakeDma1, 7, testData, sizeof(testData));
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_ConfigAddresses, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_SetDataLength, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableStream, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableDMAReq_TX, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DMA_GetRegAddr, mock), 1);
-}
-
-// Testing Pu_Post, not waiting for the crc scheduler to start processing our block
-TEST_F(PacketUsart, Post_copy_nowait)
-{
- struct usartpacketheader_t expectedHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
- expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
- expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
- expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
- expectedTransmitBuffer = &usartStatus.txBuffer.packet;
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
-
- ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
- ACTIVATE_MOCK(Pu_SetupTransmit, mock);
- ACTIVATE_MOCK_RV(Crc_IsTaskQueued, mock, 1);
-
- Pu_Post(&usartStatus, testData, sizeof(testData), false);
-
- EXPECT_EQ(usartStatus.txBuffer.busy, 1);
- EXPECT_EQ(usartStatus.txBuffer.requestedLength, expectedLength);
- EXPECT_EQ(memcmp(&usartStatus.txBuffer.packet.header, &expectedHeader, sizeof(expectedHeader)), 0);
- EXPECT_EQ(MOCK_CALLCOUNT(Crc_Enqueue, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Pu_SetupTransmit, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Crc_IsTaskQueued, mock), 0);
-}
-
-// Posting with free CRC engine (will execute our block immediately)
-TEST_F(PacketUsart, Post_copy_wait_nodelay)
-{
- expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
- expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
- expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
- expectedTransmitBuffer = &usartStatus.txBuffer.packet;
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
-
- ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
- ACTIVATE_MOCK(Pu_SetupTransmit, mock);
- ACTIVATE_MOCK_RV(Crc_IsTaskQueued, mock, 0);
-
- Pu_Post(&usartStatus, testData, sizeof(testData), true);
-
- EXPECT_EQ(MOCK_CALLCOUNT(Crc_IsTaskQueued, mock), 1);
-}
-
-// Posting with with busy CRC engine should block our call
-TEST_F(PacketUsart, Post_copy_wait_delay)
-{
- expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
- expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
- expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
- expectedTransmitBuffer = &usartStatus.txBuffer.packet;
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
-
- ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
- ACTIVATE_MOCK(Pu_SetupTransmit, mock);
- ACTIVATE_MOCK_RV(Crc_IsTaskQueued, mock, 1);
-
- // black magic to test if the function blocks (at least for 100ms)
- std::promise promiseFinished;
- auto futureResult = promiseFinished.get_future();
- pthread_t th;
- std::thread t([](std::promise& finished) {
- pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS,NULL);
- Pu_Post(&usartStatus, testData, sizeof(testData), true);;
- finished.set_value(true);
- }, std::ref(promiseFinished));
- th = t.native_handle();
- t.detach();
- EXPECT_EQ(futureResult.wait_for(std::chrono::milliseconds(100)), std::future_status::timeout);
- Crc_IsTaskQueued_mock_retval = 0;
- auto waitResult(futureResult.wait_for(std::chrono::milliseconds(100)));
- EXPECT_NE(waitResult, std::future_status::timeout);
- if(waitResult == std::future_status::timeout)
- pthread_cancel(th);
-}
-
-// HandleTxDmaIrq_tc should enable USART TC interrupt and disable DMA stream
-TEST_F(PacketUsart, HandleTxDmaIrq_tc)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_Post(&usartStatus, testData, sizeof(testData), true);
-
- memset(&fakeDma1, 0, sizeof(fakeDma1));
- fakeDma1.HISR = DMA_HISR_TCIF7;
- expectedStream = 7;
-
- ACTIVATE_MOCK(LL_USART_EnableIT_TC, mock);
- ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
-
- Pu_HandleTxDmaIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_TC, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
- EXPECT_EQ(fakeDma1.HIFCR, DMA_HIFCR_CTCIF7);
-}
-
-// HandleTxDmaIrq_te should enable USART TC interrupt disable DMA stream and set the error flag
-TEST_F(PacketUsart, HandleTxDmaIrq_te)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_Post(&usartStatus, testData, sizeof(testData), true);
-
- memset(&fakeDma1, 0, sizeof(fakeDma1));
- fakeDma1.HISR = DMA_HISR_TEIF7;
- expectedStream = 7;
-
- Pu_HandleTxDmaIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_TC, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
- EXPECT_EQ(fakeDma1.HIFCR, DMA_HIFCR_CTEIF7);
- EXPECT_EQ(usartStatus.txBuffer.error, 1);
-}
-
-// HandleUsartIrq_tc should disable USART TC interrupt, pulse TX direction enabled to enforce an idle frame
-// and mark the tx buffer as free
-TEST_F(PacketUsart, HandleUsartIrq_tc)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_Post(&usartStatus, testData, sizeof(testData), true);
-
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 0);
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
- ACTIVATE_MOCK(LL_USART_DisableIT_TC, mock);
- ACTIVATE_MOCK(LL_USART_EnableDirectionTx, mock);
- ACTIVATE_MOCK(LL_USART_DisableDirectionTx, mock);
-
- Pu_HandleUsartIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DisableIT_TC, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DisableDirectionTx, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableDirectionTx, mock), 1);
- EXPECT_EQ(usartStatus.txBuffer.busy, 0);
-}
-
-// SetupReceive must set USART and DMA engine up for reception
-TEST_F(PacketUsart, SetupReceive)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- expectedStream = 0;
- expectedDstAddress = (uint32_t)&usartStatus.rxBuffers[usartStatus.activeRxBuf].packet;
- expectedSrcAddress = (uint32_t)&fakeUsart.DR;
- expectedDirection = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
- expectedLength = sizeof(struct usartpacket_t);
-
- ACTIVATE_MOCK(LL_DMA_ConfigAddresses, mock);
- ACTIVATE_MOCK(LL_DMA_SetDataLength , mock);
- ACTIVATE_MOCK(LL_DMA_EnableStream , mock);
- ACTIVATE_MOCK(LL_USART_EnableDMAReq_RX, mock);
- ACTIVATE_MOCK(LL_USART_ClearFlag_ORE, mock);
-
- ACTIVATE_MOCK_RV(LL_USART_DMA_GetRegAddr, mock, expectedSrcAddress);
-
- Pu_SetupReceive(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_ConfigAddresses, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_SetDataLength, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableStream, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableDMAReq_RX, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_ORE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DMA_GetRegAddr, mock), 1);
-}
-
-// Test HandleUsartIrq with a received packet having a correct header checksum
-TEST_F(PacketUsart, HandleUsartIrq_idle_fullpacket_hdr_ok)
-{
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- expectedStream = 0;
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
-
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
- ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
- ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t));
- ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
- ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
-
- Pu_HandleUsartIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
- EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
-}
-
-// Test HandleUsartIrq with a received packet having a incorrect header checksum
-TEST_F(PacketUsart, HandleUsartIrq_idle_fullpacket_hdr_bad)
-{
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- expectedStream = 0;
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
-
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
- ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
- ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t));
- ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
- ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
-
- Pu_HandleUsartIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
- EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
- EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
-}
-
-// Packet reception should continue if the packet is not fully received yet
-TEST_F(PacketUsart, HandleUsartIrq_idle_tooshort)
-{
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- expectedStream = 0;
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
-
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
- ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
- ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t) + 1);
- ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
- ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
-
- Pu_HandleUsartIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
-}
-
-// Packet reception should continue if the packet is shorter than the packet header
-TEST_F(PacketUsart, HandleUsartIrq_idle_tooshortforheadercheck)
-{
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- expectedStream = 0;
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
-
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
- ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
- ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
- ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - 3);
- ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
- ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
-
- Pu_HandleUsartIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 0);
- EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
-}
-
-// Reception DMA engine transfer complete interrupt is the real verification point of the packet
-// verify that the packet is really checked
-TEST_F(PacketUsart, HandleRxDmaIrq_tc_hdrok)
-{
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- memset(&fakeDma1, 0, sizeof(fakeDma1));
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
- expectedStream = 0;
- expectedCrcEnqueueAddress = &usartStatus.rxBuffers[0].packet;
- expectedCrcLength = RoundUpTo4(usartStatus.rxBuffers[0].packet.header.payloadLength) + sizeof(struct usartpacketheader_t);
- fakeDma1.LISR = DMA_LISR_TCIF0;
-
- ACTIVATE_MOCK(Pu_CheckHeader, proxy);
- ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 0);
- ACTIVATE_MOCK(Pu_SetupReceive, mock);
-
- Pu_HandleRxDmaIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Crc_Enqueue, mock), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Pu_SetupReceive, mock), 1);
- EXPECT_EQ(fakeDma1.LIFCR, DMA_LIFCR_CTCIF0);
- EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
-}
-
-// In case of the header fails on the end of packet reception error flag should be set
-TEST_F(PacketUsart, HandleRxDmaIrq_tc_hdrfail)
-{
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
-
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- memset(&fakeDma1, 0, sizeof(fakeDma1));
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
- expectedStream = 0;
- expectedCrcEnqueueAddress = &usartStatus.rxBuffers[0].packet;
- expectedCrcLength = RoundUpTo4(usartStatus.rxBuffers[0].packet.header.payloadLength) + sizeof(struct usartpacketheader_t);
- fakeDma1.LISR = DMA_LISR_TCIF0;
-
- ACTIVATE_MOCK(Pu_CheckHeader, proxy);
- ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 0);
- ACTIVATE_MOCK(Pu_SetupReceive, mock);
-
- Pu_HandleRxDmaIrq(&usartStatus);
-
- EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
- EXPECT_EQ(MOCK_CALLCOUNT(Crc_Enqueue, mock), 0);
- EXPECT_EQ(fakeDma1.LIFCR, DMA_LIFCR_CTCIF0);
- EXPECT_EQ(usartStatus.rxBuffers[0].error, 1);
- EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
-}
-
-// successfull CRC32 check, CRC32 match, callback should be called, busy flag should be set
-TEST_F(PacketUsart, HandleRxCrcComputedCallback_success_match)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
- memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
- *(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa55a;
- MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
-
- Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
-
- EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
- EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
- EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
-}
-
-// successfull CRC32 check, CRC32 mismatch, callback should be called,
-// both busy and error flag should be set
-TEST_F(PacketUsart, HandleRxCrcComputedCallback_success_mismatch)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
- memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
- *(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa5a5;
- MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
-
- Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
-
- EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
- EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
- EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
-}
-
-//failed CRC32 check, callback should be called,
-// both busy and error flag should be set
-TEST_F(PacketUsart, HandleRxCrcComputedCallback_failure)
-{
- Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
- Pu_SetupReceive(&usartStatus);
-
- struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
- memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
- memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
- *(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa5a5;
- MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
-
- Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
-
- EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
- EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
- EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
-}
+#include
+#include
+
+#include
+#include
+#include
+
+
+//static inline uint32_t RoundUpTo4(uint32_t inp)
+//{
+// return (inp + 3) & 0xfffc;
+//}
+//
+//DMA_TypeDef* DMA1 __attribute__((weak));
+//DMA_TypeDef* DMA2 __attribute__((weak));
+//
+//static DMA_TypeDef fakeDma1, fakeDma2;
+//static CRC_TypeDef fakeCrc;
+//static USART_TypeDef fakeUsart;
+//
+//static struct usartstatus_t usartStatus;
+//static struct crcstatus_t crcStatus;
+//
+//uint8_t testData[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
+//
+////static uint32_t expected_stream;
+////static uint32_t expected_srcaddress;
+////static uint32_t expected_dstaddress;
+////static uint32_t expected_length;
+////static void *expected_customptr;
+////static uint8_t expected_success;
+////static struct usartstatus_t * expectedUsartStatus;
+//static uint32_t expectedStreams[2] = { 0,7 };
+//struct crcstatus_t *expectedCrcStatus;
+//struct crcslot_t *expectedCrcSlotListItem;
+//struct crctask_t *expectedTasks;
+//uint8_t expectedTaskCount;
+//uint32_t expectedCrcLength;
+//uint32_t expectedLength;
+//void* expectedCrcEnqueueAddress;
+//void *expectedTransmitBuffer;
+//
+//static uint32_t expectedStream;
+//uint32_t expectedSrcAddress;
+//uint32_t expectedDstAddress;
+//uint32_t expectedDirection;
+//
+//uint32_t fakePacketReceivedCallbackParam;
+//
+//
+//// this isn't a real mov but we use the mockinginfrastructure
+//// to automate administration (call count, etc)
+//DEFINE_MOCK(FakePacketReceivedCallback, mock, void* userParam, struct usart_buffer_t *buffer)
+//{
+// EXPECT_EQ((void*)&fakePacketReceivedCallbackParam, userParam);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(Dma_Init, mock, struct dmainfo_t* dmaInfo, DMA_TypeDef *dma, uint32_t stream)
+//{
+// Dma_Init__(dmaInfo, dma, stream);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(Crc_AttachTasks, mock, struct crcstatus_t *status, struct crcslot_t *slot, struct crctask_t *tasks, uint8_t taskCount)
+//{
+// EXPECT_EQ(status, expectedCrcStatus);
+// EXPECT_EQ(slot, expectedCrcSlotListItem);
+// EXPECT_EQ(tasks, expectedTasks);
+// EXPECT_EQ(taskCount, expectedTaskCount);
+// Crc_AttachTasks__(status, slot, tasks, taskCount);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_DMA_EnableIT_TC, init, DMA_TypeDef *dma, uint32_t stream)
+//{
+// EXPECT_EQ(dma, &fakeDma1);
+// EXPECT_EQ(stream, expectedStreams[MOCK_VAR(LL_DMA_EnableIT_TC, init, callcount)-1]);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_DMA_EnableIT_TE, init, DMA_TypeDef *dma, uint32_t stream)
+//{
+// EXPECT_EQ(dma, &fakeDma1);
+// EXPECT_EQ(stream, expectedStreams[MOCK_VAR(LL_DMA_EnableIT_TE, init, callcount)-1]);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK_RET(uint32_t, LL_USART_DMA_GetRegAddr, mock, USART_TypeDef *usart)
+//{
+// RETURN_MOCK_PREDEF(LL_USART_DMA_GetRegAddr, mock)
+//}
+//
+//DEFINE_MOCK(LL_DMA_ConfigAddresses, mock, DMA_TypeDef* dma, uint32_t stream, uint32_t srcAddress, uint32_t dstAddress, uint32_t direction)
+//{
+// EXPECT_EQ(dma, &fakeDma1);
+// EXPECT_EQ(stream, expectedStream);
+// EXPECT_EQ(srcAddress, expectedSrcAddress);
+// EXPECT_EQ(dstAddress, expectedDstAddress);
+// EXPECT_EQ(direction, expectedDirection);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_DMA_SetDataLength, mock, DMA_TypeDef* dma, uint32_t stream, uint32_t length)
+//{
+// EXPECT_EQ(dma, &fakeDma1);
+// EXPECT_EQ(stream, expectedStream);
+// EXPECT_EQ(length, expectedLength);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK_RET(uint32_t, LL_DMA_GetDataLength, mock, DMA_TypeDef* dma, uint32_t stream)
+//{
+// EXPECT_EQ(dma, &fakeDma1);
+// EXPECT_EQ(stream, expectedStream);
+// RETURN_MOCK_PREDEF(LL_DMA_GetDataLength, mock)
+//}
+//
+//DEFINE_MOCK(LL_DMA_EnableStream, mock, DMA_TypeDef* dma, uint32_t stream)
+//{
+// EXPECT_EQ(dma, &fakeDma1);
+// EXPECT_EQ(stream, expectedStream);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_DMA_DisableStream, mock, DMA_TypeDef* dma, uint32_t stream)
+//{
+// EXPECT_EQ(dma, &fakeDma1);
+// EXPECT_EQ(stream, expectedStream);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_USART_EnableDMAReq_TX, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_USART_EnableDMAReq_RX, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_USART_EnableIT_IDLE, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_USART_EnableIT_TC, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_USART_DisableIT_TC, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK_RET(uint32_t, LL_USART_IsActiveFlag_IDLE, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// RETURN_MOCK_PREDEF(LL_USART_IsActiveFlag_IDLE, mock)
+//}
+//
+//DEFINE_MOCK_RET(uint32_t, LL_USART_IsActiveFlag_TC, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// RETURN_MOCK_PREDEF(LL_USART_IsActiveFlag_TC, mock)
+//}
+//
+//DEFINE_MOCK(LL_USART_ClearFlag_IDLE, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK;
+//}
+//
+//DEFINE_MOCK_RET(uint32_t, LL_USART_IsEnabledIT_IDLE, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// RETURN_MOCK_PREDEF(LL_USART_IsEnabledIT_IDLE, mock)
+//}
+//
+//DEFINE_MOCK_RET(uint32_t, LL_USART_IsEnabledIT_TC, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// RETURN_MOCK_PREDEF(LL_USART_IsEnabledIT_TC, mock)
+//}
+//
+//DEFINE_MOCK(LL_USART_EnableDirectionTx, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_USART_DisableDirectionTx, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK(LL_USART_ClearFlag_ORE, mock, USART_TypeDef *usart)
+//{
+// EXPECT_EQ(usart, &fakeUsart);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK_RET(uint8_t, Crc_Enqueue, mock, struct crcstatus_t *status, struct crcslot_t *slot, uint8_t task,
+// void *address, uint16_t len, void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
+//{
+// EXPECT_EQ(expectedCrcLength, len);
+// EXPECT_EQ(expectedCrcEnqueueAddress, address);
+// RETURN_MOCK_PREDEF(Crc_Enqueue, mock);
+//}
+//
+//DEFINE_MOCK_RET(uint8_t, Crc_IsTaskQueued, mock, struct crcslot_t *slot, uint8_t task)
+//{
+// RETURN_MOCK_PREDEF(Crc_IsTaskQueued, mock);
+//}
+//
+//DEFINE_MOCK(Pu_SetupTransmit, mock, USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
+//{
+// EXPECT_EQ(buffer, expectedTransmitBuffer);
+// EXPECT_EQ(length, expectedLength);
+// LEAVE_MOCK
+//}
+//
+//DEFINE_MOCK_RET(uint8_t, Pu_CheckHeader, proxy, struct usartpacket_t *packet)
+//{
+// RETURN_MOCK(Pu_CheckHeader, proxy, Pu_CheckHeader__(packet));
+//}
+//
+//DEFINE_MOCK(Pu_SetupReceive, mock, struct usartstatus_t *status)
+//{
+// LEAVE_MOCK
+//}
+//
+//struct PacketUsart : public ::testing::Test {
+// void SetUp()
+// {
+// DMA1 = &fakeDma1;
+// DMA2 = &fakeDma2;
+//
+// memset(&usartStatus, 0x5a, sizeof(usartStatus));
+// Crc_InitStatus(&crcStatus, &fakeCrc, &fakeDma2, 4);
+//
+// expectedCrcStatus = &crcStatus;
+// expectedCrcSlotListItem = &usartStatus.crcSlot;
+// expectedTasks = usartStatus.crcTasks;
+// expectedTaskCount = 2;
+// }
+//};
+//
+////////////////////////////////////////////////////////////////////////////////
+//TEST_F(PacketUsart, Init)
+//{
+// ACTIVATE_MOCK(Dma_Init, mock);
+// ACTIVATE_MOCK(Crc_AttachTasks, mock);
+// ACTIVATE_MOCK(LL_DMA_EnableIT_TC, init);
+// ACTIVATE_MOCK(LL_DMA_EnableIT_TE, init);
+// ACTIVATE_MOCK(LL_USART_EnableIT_IDLE, mock);
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+//
+// EXPECT_EQ(fakeDma1.LIFCR, DMA_LISR_TCIF0 | DMA_LISR_HTIF0 | DMA_LISR_TEIF0 | DMA_LISR_FEIF0 | DMA_LISR_DMEIF0);
+// EXPECT_EQ(fakeDma1.HIFCR, DMA_HISR_TCIF7 | DMA_HISR_HTIF7 | DMA_HISR_TEIF7 | DMA_HISR_FEIF7 | DMA_HISR_DMEIF7);
+// EXPECT_EQ(MOCK_CALLCOUNT(Dma_Init, mock), 2);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableIT_TC, init), 2);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableIT_TE, init), 2);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_IDLE, mock), 1);
+// EXPECT_EQ(usartStatus.usart, &fakeUsart);
+// EXPECT_EQ(usartStatus.txBuffer.usartStatus, &usartStatus);
+// EXPECT_EQ(usartStatus.txBuffer.busy, 0);
+// EXPECT_EQ(usartStatus.txBuffer.error, 0);
+// EXPECT_EQ(usartStatus.txBuffer.requestedLength, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].requestedLength, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].usartStatus, &usartStatus );
+// EXPECT_EQ(usartStatus.rxBuffers[1].busy, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[1].error, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[1].requestedLength, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[1].usartStatus, &usartStatus );
+// EXPECT_TRUE(usartStatus.packetReceivedCallback == FakePacketReceivedCallback_mock);
+// EXPECT_EQ(usartStatus.packetReceivedCallbackParam, &fakePacketReceivedCallbackParam);
+// EXPECT_EQ(usartStatus.rxSerial, (uint8_t)-1);
+// EXPECT_EQ(usartStatus.txSerial, 0);
+// EXPECT_EQ(usartStatus.activeRxBuf, 0);
+// EXPECT_EQ(usartStatus.crcStatus, &crcStatus);
+//}
+//
+//TEST_F(PacketUsart, GetTxBuffer)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// EXPECT_EQ(Pu_GetTxBuffer(&usartStatus), (unsigned char*)&usartStatus.txBuffer.packet.payload);
+//}
+//
+//// SetupTransmit should set all engines (DMA, USART) up properly for starting the transmission
+//TEST_F(PacketUsart, SetupTransmit)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// expectedStream = 7;
+// expectedSrcAddress = (uint32_t)testData;
+// expectedDstAddress = (uint32_t)&fakeUsart.DR;
+// expectedDirection = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
+// expectedLength = sizeof(testData);
+//
+// ACTIVATE_MOCK(LL_DMA_ConfigAddresses, mock);
+// ACTIVATE_MOCK(LL_DMA_SetDataLength , mock);
+// ACTIVATE_MOCK(LL_DMA_EnableStream , mock);
+// ACTIVATE_MOCK(LL_USART_EnableDMAReq_TX, mock);
+// ACTIVATE_MOCK_RV(LL_USART_DMA_GetRegAddr, mock, expectedDstAddress);
+//
+// Pu_SetupTransmit(&fakeUsart, &fakeDma1, 7, testData, sizeof(testData));
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_ConfigAddresses, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_SetDataLength, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableStream, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableDMAReq_TX, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DMA_GetRegAddr, mock), 1);
+//}
+//
+//// Testing Pu_Post, not waiting for the crc scheduler to start processing our block
+//TEST_F(PacketUsart, Post_copy_nowait)
+//{
+// struct usartpacketheader_t expectedHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
+// expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
+// expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
+// expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
+// expectedTransmitBuffer = &usartStatus.txBuffer.packet;
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+//
+// ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
+// ACTIVATE_MOCK(Pu_SetupTransmit, mock);
+// ACTIVATE_MOCK_RV(Crc_IsTaskQueued, mock, 1);
+//
+// Pu_Post(&usartStatus, testData, sizeof(testData), false);
+//
+// EXPECT_EQ(usartStatus.txBuffer.busy, 1);
+// EXPECT_EQ(usartStatus.txBuffer.requestedLength, expectedLength);
+// EXPECT_EQ(memcmp(&usartStatus.txBuffer.packet.header, &expectedHeader, sizeof(expectedHeader)), 0);
+// EXPECT_EQ(MOCK_CALLCOUNT(Crc_Enqueue, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Pu_SetupTransmit, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Crc_IsTaskQueued, mock), 0);
+//}
+//
+//// Posting with free CRC engine (will execute our block immediately)
+//TEST_F(PacketUsart, Post_copy_wait_nodelay)
+//{
+// expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
+// expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
+// expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
+// expectedTransmitBuffer = &usartStatus.txBuffer.packet;
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+//
+// ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
+// ACTIVATE_MOCK(Pu_SetupTransmit, mock);
+// ACTIVATE_MOCK_RV(Crc_IsTaskQueued, mock, 0);
+//
+// Pu_Post(&usartStatus, testData, sizeof(testData), true);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(Crc_IsTaskQueued, mock), 1);
+//}
+//
+//// Posting with with busy CRC engine should block our call
+//TEST_F(PacketUsart, Post_copy_wait_delay)
+//{
+// expectedCrcLength = sizeof(usartStatus.txBuffer.packet.header) + 12;
+// expectedCrcEnqueueAddress = &usartStatus.txBuffer.packet;
+// expectedLength = sizeof(usartStatus.txBuffer.packet.header) + 12 + sizeof(uint32_t);
+// expectedTransmitBuffer = &usartStatus.txBuffer.packet;
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+//
+// ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 1);
+// ACTIVATE_MOCK(Pu_SetupTransmit, mock);
+// ACTIVATE_MOCK_RV(Crc_IsTaskQueued, mock, 1);
+//
+// // black magic to test if the function blocks (at least for 100ms)
+// std::promise promiseFinished;
+// auto futureResult = promiseFinished.get_future();
+// pthread_t th;
+// std::thread t([](std::promise& finished) {
+// pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS,NULL);
+// Pu_Post(&usartStatus, testData, sizeof(testData), true);;
+// finished.set_value(true);
+// }, std::ref(promiseFinished));
+// th = t.native_handle();
+// t.detach();
+// EXPECT_EQ(futureResult.wait_for(std::chrono::milliseconds(100)), std::future_status::timeout);
+// Crc_IsTaskQueued_mock_retval = 0;
+// auto waitResult(futureResult.wait_for(std::chrono::milliseconds(100)));
+// EXPECT_NE(waitResult, std::future_status::timeout);
+// if(waitResult == std::future_status::timeout)
+// pthread_cancel(th);
+//}
+//
+//// HandleTxDmaIrq_tc should enable USART TC interrupt and disable DMA stream
+//TEST_F(PacketUsart, HandleTxDmaIrq_tc)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_Post(&usartStatus, testData, sizeof(testData), true);
+//
+// memset(&fakeDma1, 0, sizeof(fakeDma1));
+// fakeDma1.HISR = DMA_HISR_TCIF7;
+// expectedStream = 7;
+//
+// ACTIVATE_MOCK(LL_USART_EnableIT_TC, mock);
+// ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
+//
+// Pu_HandleTxDmaIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_TC, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
+// EXPECT_EQ(fakeDma1.HIFCR, DMA_HIFCR_CTCIF7);
+//}
+//
+//// HandleTxDmaIrq_te should enable USART TC interrupt disable DMA stream and set the error flag
+//TEST_F(PacketUsart, HandleTxDmaIrq_te)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_Post(&usartStatus, testData, sizeof(testData), true);
+//
+// memset(&fakeDma1, 0, sizeof(fakeDma1));
+// fakeDma1.HISR = DMA_HISR_TEIF7;
+// expectedStream = 7;
+//
+// Pu_HandleTxDmaIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableIT_TC, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
+// EXPECT_EQ(fakeDma1.HIFCR, DMA_HIFCR_CTEIF7);
+// EXPECT_EQ(usartStatus.txBuffer.error, 1);
+//}
+//
+//// HandleUsartIrq_tc should disable USART TC interrupt, pulse TX direction enabled to enforce an idle frame
+//// and mark the tx buffer as free
+//TEST_F(PacketUsart, HandleUsartIrq_tc)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_Post(&usartStatus, testData, sizeof(testData), true);
+//
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 0);
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
+// ACTIVATE_MOCK(LL_USART_DisableIT_TC, mock);
+// ACTIVATE_MOCK(LL_USART_EnableDirectionTx, mock);
+// ACTIVATE_MOCK(LL_USART_DisableDirectionTx, mock);
+//
+// Pu_HandleUsartIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DisableIT_TC, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DisableDirectionTx, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableDirectionTx, mock), 1);
+// EXPECT_EQ(usartStatus.txBuffer.busy, 0);
+//}
+//
+//// SetupReceive must set USART and DMA engine up for reception
+//TEST_F(PacketUsart, SetupReceive)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// expectedStream = 0;
+// expectedDstAddress = (uint32_t)&usartStatus.rxBuffers[usartStatus.activeRxBuf].packet;
+// expectedSrcAddress = (uint32_t)&fakeUsart.DR;
+// expectedDirection = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+// expectedLength = sizeof(struct usartpacket_t);
+//
+// ACTIVATE_MOCK(LL_DMA_ConfigAddresses, mock);
+// ACTIVATE_MOCK(LL_DMA_SetDataLength , mock);
+// ACTIVATE_MOCK(LL_DMA_EnableStream , mock);
+// ACTIVATE_MOCK(LL_USART_EnableDMAReq_RX, mock);
+// ACTIVATE_MOCK(LL_USART_ClearFlag_ORE, mock);
+//
+// ACTIVATE_MOCK_RV(LL_USART_DMA_GetRegAddr, mock, expectedSrcAddress);
+//
+// Pu_SetupReceive(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_ConfigAddresses, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_SetDataLength, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_EnableStream, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_EnableDMAReq_RX, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_ORE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_DMA_GetRegAddr, mock), 1);
+//}
+//
+//// Test HandleUsartIrq with a received packet having a correct header checksum
+//TEST_F(PacketUsart, HandleUsartIrq_idle_fullpacket_hdr_ok)
+//{
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// expectedStream = 0;
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+//
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
+// ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
+// ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t));
+// ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
+// ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
+//
+// Pu_HandleUsartIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
+// EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
+//}
+//
+//// Test HandleUsartIrq with a received packet having a incorrect header checksum
+//TEST_F(PacketUsart, HandleUsartIrq_idle_fullpacket_hdr_bad)
+//{
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// expectedStream = 0;
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+//
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
+// ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
+// ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t));
+// ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
+// ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
+//
+// Pu_HandleUsartIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 1);
+// EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
+// EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
+//}
+//
+//// Packet reception should continue if the packet is not fully received yet
+//TEST_F(PacketUsart, HandleUsartIrq_idle_tooshort)
+//{
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// expectedStream = 0;
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+//
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
+// ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
+// ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - sizeof(struct usartpacketheader_t) - RoundUpTo4(sizeof(testData)) - sizeof(uint32_t) + 1);
+// ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
+// ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
+//
+// Pu_HandleUsartIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
+//}
+//
+//// Packet reception should continue if the packet is shorter than the packet header
+//TEST_F(PacketUsart, HandleUsartIrq_idle_tooshortforheadercheck)
+//{
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// expectedStream = 0;
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+//
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsActiveFlag_TC, mock, 0);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_IDLE, mock, 1);
+// ACTIVATE_MOCK_RV(LL_USART_IsEnabledIT_TC, mock, 1);
+// ACTIVATE_MOCK(LL_USART_ClearFlag_IDLE, mock);
+// ACTIVATE_MOCK_RV(LL_DMA_GetDataLength, mock, sizeof(struct usartpacket_t) - 3);
+// ACTIVATE_MOCK_RV(Pu_CheckHeader, proxy, 1);
+// ACTIVATE_MOCK(LL_DMA_DisableStream, mock);
+//
+// Pu_HandleUsartIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsActiveFlag_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_IsEnabledIT_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_USART_ClearFlag_IDLE, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_GetDataLength, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 0);
+// EXPECT_EQ(MOCK_CALLCOUNT(LL_DMA_DisableStream, mock), 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
+//}
+//
+//// Reception DMA engine transfer complete interrupt is the real verification point of the packet
+//// verify that the packet is really checked
+//TEST_F(PacketUsart, HandleRxDmaIrq_tc_hdrok)
+//{
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0x95 ^ 0 ^ sizeof(testData) };
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// memset(&fakeDma1, 0, sizeof(fakeDma1));
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+// expectedStream = 0;
+// expectedCrcEnqueueAddress = &usartStatus.rxBuffers[0].packet;
+// expectedCrcLength = RoundUpTo4(usartStatus.rxBuffers[0].packet.header.payloadLength) + sizeof(struct usartpacketheader_t);
+// fakeDma1.LISR = DMA_LISR_TCIF0;
+//
+// ACTIVATE_MOCK(Pu_CheckHeader, proxy);
+// ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 0);
+// ACTIVATE_MOCK(Pu_SetupReceive, mock);
+//
+// Pu_HandleRxDmaIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Crc_Enqueue, mock), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Pu_SetupReceive, mock), 1);
+// EXPECT_EQ(fakeDma1.LIFCR, DMA_LIFCR_CTCIF0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
+//}
+//
+//// In case of the header fails on the end of packet reception error flag should be set
+//TEST_F(PacketUsart, HandleRxDmaIrq_tc_hdrfail)
+//{
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
+//
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// memset(&fakeDma1, 0, sizeof(fakeDma1));
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+// expectedStream = 0;
+// expectedCrcEnqueueAddress = &usartStatus.rxBuffers[0].packet;
+// expectedCrcLength = RoundUpTo4(usartStatus.rxBuffers[0].packet.header.payloadLength) + sizeof(struct usartpacketheader_t);
+// fakeDma1.LISR = DMA_LISR_TCIF0;
+//
+// ACTIVATE_MOCK(Pu_CheckHeader, proxy);
+// ACTIVATE_MOCK_RV(Crc_Enqueue, mock, 0);
+// ACTIVATE_MOCK(Pu_SetupReceive, mock);
+//
+// Pu_HandleRxDmaIrq(&usartStatus);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(Pu_CheckHeader, proxy), 1);
+// EXPECT_EQ(MOCK_CALLCOUNT(Crc_Enqueue, mock), 0);
+// EXPECT_EQ(fakeDma1.LIFCR, DMA_LIFCR_CTCIF0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].error, 1);
+// EXPECT_EQ(usartStatus.rxBuffers[0].busy, 0);
+//}
+//
+//// successfull CRC32 check, CRC32 match, callback should be called, busy flag should be set
+//TEST_F(PacketUsart, HandleRxCrcComputedCallback_success_match)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+// memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
+// *(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa55a;
+// MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
+//
+// Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
+// EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
+// EXPECT_EQ(usartStatus.rxBuffers[0].error, 0);
+//}
+//
+//// successfull CRC32 check, CRC32 mismatch, callback should be called,
+//// both busy and error flag should be set
+//TEST_F(PacketUsart, HandleRxCrcComputedCallback_success_mismatch)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+// memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
+// *(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa5a5;
+// MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
+//
+// Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
+// EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
+// EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
+//}
+//
+////failed CRC32 check, callback should be called,
+//// both busy and error flag should be set
+//TEST_F(PacketUsart, HandleRxCrcComputedCallback_failure)
+//{
+// Pu_Init(&usartStatus, &fakeUsart, DMA1, 0, 7, &crcStatus, FakePacketReceivedCallback_mock, &fakePacketReceivedCallbackParam);
+// Pu_SetupReceive(&usartStatus);
+//
+// struct usartpacketheader_t fakeHeader = { 0x95, 0, sizeof(testData), 0xff ^ 0 ^ sizeof(testData) };
+// memcpy(&usartStatus.rxBuffers[0].packet.header, &fakeHeader, sizeof(fakeHeader));
+// memcpy(usartStatus.rxBuffers[0].packet.payload, &testData, sizeof(testData));
+// *(uint32_t*)(usartStatus.rxBuffers[0].packet.payload + RoundUpTo4(sizeof(testData))) = 0xa5a5;
+// MOCK_CALLCOUNT(FakePacketReceivedCallback, mock) = 0;
+//
+// Pu_RxCrcComputedCallback(&usartStatus.rxBuffers[0], 0xa55a, 1);
+//
+// EXPECT_EQ(MOCK_CALLCOUNT(FakePacketReceivedCallback, mock), 1);
+// EXPECT_NE(usartStatus.rxBuffers[0].busy, 0);
+// EXPECT_NE(usartStatus.rxBuffers[0].error, 0);
+//}
diff --git a/platforms/platform-test-f4-ll/cpputest/examples/.cproject b/platforms/platform-test-f4-ll/cpputest/examples/.cproject
new file mode 100644
index 0000000..35a4b9a
--- /dev/null
+++ b/platforms/platform-test-f4-ll/cpputest/examples/.cproject
@@ -0,0 +1,62 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/platforms/platform-test-f4-ll/platform/cmsis.c b/platforms/platform-test-f4-ll/platform/cmsis.c
index 2ac319d..b2648c4 100644
--- a/platforms/platform-test-f4-ll/platform/cmsis.c
+++ b/platforms/platform-test-f4-ll/platform/cmsis.c
@@ -6,7 +6,29 @@
*/
#include "cmsis.h"
#include
+#include
+#include
-void __disable_irq)() {}
-uint32_t __get_PRIMASK() { return 0; }
-void __set_PRIMASK(uint32_t primask) {}
+uint32_t g_effective_primask = 0;
+
+void __disable_irq() {
+ g_effective_primask = 1;
+ mock_c()->actualCall(__FUNCTION__);
+}
+
+void __enable_irq() {
+ g_effective_primask = 0;
+ mock_c()->actualCall(__FUNCTION__);
+}
+
+uint32_t __get_PRIMASK() {
+ return mock_c()->actualCall(__FUNCTION__)->
+ returnUnsignedIntValueOrDefault(g_effective_primask);
+}
+
+
+void __set_PRIMASK(uint32_t primask) {
+ g_effective_primask = primask;
+ mock_c()->actualCall(__FUNCTION__)->
+ withUnsignedIntParameters(TOSTR(primask), primask);
+}
diff --git a/platforms/platform-test-f4-ll/platform/cmsis.h b/platforms/platform-test-f4-ll/platform/cmsis.h
index 82bdaff..ace5a1b 100644
--- a/platforms/platform-test-f4-ll/platform/cmsis.h
+++ b/platforms/platform-test-f4-ll/platform/cmsis.h
@@ -23,7 +23,9 @@ extern "C" {
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+extern uint32_t g_effective_primask;
void __disable_irq();
+void __enable_irq();
uint32_t __get_PRIMASK();
void __set_PRIMASK(uint32_t priMask);
diff --git a/platforms/platform-test-f4-ll/platform/dma_ll.c b/platforms/platform-test-f4-ll/platform/dma_ll.c
index 8d52b92..2039922 100644
--- a/platforms/platform-test-f4-ll/platform/dma_ll.c
+++ b/platforms/platform-test-f4-ll/platform/dma_ll.c
@@ -5,13 +5,90 @@
* Author: abody
*/
#include "dma_ll.h"
+#include
+#include
+
+__attribute__((weak)) DMA_TypeDef _DMA1;
+__attribute__((weak)) DMA_TypeDef _DMA2;
+
+
+void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream);
+}
+
+
+void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream);
+}
+
+
+void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream)->
+ withUnsignedIntParameters(TOSTR(MemoryAddress), MemoryAddress);
+}
+
+
+void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream)->
+ withUnsignedIntParameters(TOSTR(MemoryAddress), MemoryAddress);
+}
+
+
+uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+ return mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream)->
+ returnUnsignedIntValueOrDefault(0);
+}
+
+
+void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream)->
+ withUnsignedIntParameters(TOSTR(NbData), NbData);
+}
+
+
+void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream);
+}
+
+
+void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream);
+}
+
+
+void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(DMAx), DMAx)->
+ withUnsignedIntParameters(TOSTR(Stream), Stream)->
+ withUnsignedIntParameters(TOSTR(SrcAddress), SrcAddress)->
+ withUnsignedIntParameters(TOSTR(DstAddress), DstAddress)->
+ withUnsignedIntParameters(TOSTR(Direction), Direction);
+}
+
+
-void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) {}
-void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) {}
-void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) {}
-void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) {}
-uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) { return 0; }
-void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) {}
-void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) {}
-void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) {}
-void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) {}
diff --git a/platforms/platform-test-f4-ll/platform/dma_ll.h b/platforms/platform-test-f4-ll/platform/dma_ll.h
index 50f2d2a..656aa71 100644
--- a/platforms/platform-test-f4-ll/platform/dma_ll.h
+++ b/platforms/platform-test-f4-ll/platform/dma_ll.h
@@ -608,8 +608,11 @@ typedef struct
-extern DMA_TypeDef *DMA1;
-extern DMA_TypeDef *DMA2;
+extern DMA_TypeDef _DMA1;
+extern DMA_TypeDef _DMA2;
+
+#define DMA1 (&_DMA1)
+#define DMA2 (&_DMA2)
void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream);
void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream);
diff --git a/platforms/platform-test-f4-ll/platform/helpers.h b/platforms/platform-test-f4-ll/platform/helpers.h
new file mode 100644
index 0000000..c0ffa8f
--- /dev/null
+++ b/platforms/platform-test-f4-ll/platform/helpers.h
@@ -0,0 +1,13 @@
+/*
+ * helpers.h
+ *
+ * Created on: Feb 25, 2021
+ * Author: compi
+ */
+
+#ifndef PLATFORM_HELPERS_H_
+#define PLATFORM_HELPERS_H_
+
+#define TOSTR(x) #x
+
+#endif /* PLATFORM_HELPERS_H_ */
diff --git a/platforms/platform-test-f4-ll/platform/test_main.cpp b/platforms/platform-test-f4-ll/platform/test_main.cpp
new file mode 100644
index 0000000..f38b938
--- /dev/null
+++ b/platforms/platform-test-f4-ll/platform/test_main.cpp
@@ -0,0 +1,7 @@
+#include
+#include
+
+int main(int ac, char** av)
+{
+ return CommandLineTestRunner::RunAllTests(ac, av);
+}
diff --git a/platforms/platform-test-f4-ll/platform/usart_ll.c b/platforms/platform-test-f4-ll/platform/usart_ll.c
index 83b0bc9..202bbf3 100644
--- a/platforms/platform-test-f4-ll/platform/usart_ll.c
+++ b/platforms/platform-test-f4-ll/platform/usart_ll.c
@@ -6,22 +6,115 @@
*/
#include "usart_ll.h"
+#include
+#include
-void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) {}
-void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) {}
-void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) {}
-uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) { return 1; }
-uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) { return 1; }
+__attribute__((weak)) USART_TypeDef _USART1;
+__attribute__((weak)) USART_TypeDef _USART2;
+__attribute__((weak)) USART_TypeDef _USART3;
+__attribute__((weak)) USART_TypeDef _USART6;
-void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) {}
-void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) {}
+void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
-uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) { return 0; }
-uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) { return 1; }
-uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) { return 1; }
-void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) {}
-void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) {}
+void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
+
+
+void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
+
+
+uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+ return mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx)->
+ returnUnsignedIntValueOrDefault(1);
+}
+
+
+uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+ return mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx)->
+ returnUnsignedIntValueOrDefault(1);
+}
+
+
+void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
+
+
+void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
+
+
+
+uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
+{
+ return mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx)->
+ returnUnsignedIntValueOrDefault(0);
+}
+
+
+uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+ return mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx)->
+ returnUnsignedIntValueOrDefault(1);
+}
+
+
+uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+ return mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx)->
+ returnUnsignedIntValueOrDefault(1);
+}
+
+
+void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
+
+
+void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
+
+
+void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
+
+
+void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+ mock_c()->actualCall(__FUNCTION__)->
+ withPointerParameters(TOSTR(USARTx), USARTx);
+}
+
-void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) {}
-void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) {}
diff --git a/platforms/platform-test-f4-ll/platform/usart_ll.h b/platforms/platform-test-f4-ll/platform/usart_ll.h
index 3c335bf..5e3fb4a 100644
--- a/platforms/platform-test-f4-ll/platform/usart_ll.h
+++ b/platforms/platform-test-f4-ll/platform/usart_ll.h
@@ -198,10 +198,15 @@ typedef struct
/*----------- cut here -----------*/
-extern USART_TypeDef *USART1;
-extern USART_TypeDef *USART2;
-extern USART_TypeDef *USART3;
-extern USART_TypeDef *USART6;
+extern USART_TypeDef _USART1;
+extern USART_TypeDef _USART2;
+extern USART_TypeDef _USART3;
+extern USART_TypeDef _USART6;
+
+#define USART1 (&_USART1)
+#define USART2 (&_USART2)
+#define USART3 (&_USART3)
+#define USART6 (&_USART6)
void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx);
void LL_USART_EnableIT_TC(USART_TypeDef *USARTx);