playground-stm32/f407ve_packetusart_c
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git subrepo pull components/f4ll_c

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subrepo:
  subdir:   "components/f4ll_c"
  merged:   "4754b65"
upstream:
  origin:   "git@git.pcmuhely.hu:compi/f4ll_c.git"
  branch:   "master"
  commit:   "4754b65"
git-subrepo:
  version:  "0.4.0"
  origin:   "https://github.com/ingydotnet/git-subrepo"
  commit:   "5d6aba9"
This commit is contained in:
Attila Body 2019-11-28 11:41:10 +01:00
parent 6f89e70a2a
commit 357b30b344
11 changed files with 140 additions and 72 deletions
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6
components/f4ll_c/packetusart.c
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@ -9,7 +9,9 @@
#include <f4ll_c/packetusart.h>
#include <string.h>
#include <platform/usart_ll.h>
#if defined(HAVE_DIAG)
#include "diag.h"
#endif
#include "f4ll_c/dmahelper.h"
#include "f4ll_c/crcscheduler.h"
@ -105,13 +107,9 @@ static inline uint8_t CheckHeader(struct usartpacket_t *packet)
uint8_t Pku_Post(struct usartstatus_t *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue)
{
// static uint32_t count = 0;
// ITM->PORT[1].u32 = count++;
if(length > 256)
return 1;
BuildHeader(&status->txBuffer, status->txSerial++, length);
uint16_t payloadLength = RoundUpTo4(length);
if(payload)