f407ve_hs_uart/lib/usart_handler.c
2019-11-08 14:11:08 +01:00

258 lines
8.8 KiB
C

/*
* usart_handler.c
*
* Created on: Sep 16, 2019
* Author: abody
*/
#include <string.h>
#include <platform/usart_ll.h>
#include "diag.h"
#include "usart_handler.h"
#include "dma_helper.h"
#include "crc_handler.h"
#include "memcpy_dma.h"
#ifndef DIAG_RX_BUFFER_SWITCH
# define DIAG_RX_BUFFER_SWITCH(x)
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
#define STARTMARKER 0x95
static inline uint32_t RoundUpTo4(uint32_t inp)
{
return (inp + 3) & 0xfffc;
}
void InitUartStatus(
USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
uint32_t stream_rx, uint32_t stream_tx,
CRCSTATUS *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot,
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
{
st->usart = usart;
InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
st->txBuffer.busy = 0;
st->txBuffer.error = 0;
st->txBuffer.requestedLength = 0;
st->rxBuffers[0].busy = 0;
st->rxBuffers[1].busy = 0;
st->rxBuffers[0].error = 0;
st->rxBuffers[1].error = 0;
st->rxBuffers[0].requestedLength = 0;
st->rxBuffers[1].requestedLength = 0;
st->txBuffer.usartStatus = st;
st->rxBuffers[0].usartStatus = st;
st->rxBuffers[1].usartStatus = st;
st->packetReceivedCallback = packetReceivedCallback;
st->packetReceivedCallbacParam = packetReceivedCallbackParam;
st->rxSerial = -1;
st->txSerial = 0;
st->activeRxBuf = 0;
st->crcStatus = crcStatus;
st->txCrcSlot = txCrcSlot;
st->rxCrcSlot = rxCrcSlot;
memset(&st->stats, 0, sizeof(st->stats));
LL_DMA_EnableIT_TC(dma, stream_rx);
LL_DMA_EnableIT_TE(dma, stream_rx);
LL_DMA_EnableIT_TC(dma, stream_tx);
LL_DMA_EnableIT_TE(dma, stream_tx);
LL_USART_EnableIT_IDLE(usart);
}
uint8_t* GetTxBuffer(USARTSTATUS *status)
{
return status->txBuffer.packet.payload;
}
static inline void BuildHeader(struct usart_buffer *buffer, uint8_t serial, uint8_t length)
{
uint8_t hash = STARTMARKER;
buffer->packet.header.startByte = STARTMARKER;
buffer->packet.header.serial = serial;
hash ^= serial;
buffer->packet.header.payloadLength = length - 1;
hash ^= length - 1;
buffer->packet.header.hash = hash;
}
static inline uint8_t CheckHeader(USARTPACKET *packet)
{
return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
}
uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, CRCSTATUS *crcStatus)
{
if(length > 256)
return 1;
BuildHeader(&status->txBuffer, status->txSerial++, length);
uint16_t payloadLength = RoundUpTo4(length);
if(payload) {
#ifdef USART_USE_MEMCPY_DMA
if((uint32_t)payload & 3)
memcpy(status->txBuffer.packet.payload, payload, length);
else
MemcpyDma(status->txBuffer.packet.payload, payload, length);
#else
memcpy(status->txBuffer.packet.payload, payload, length);
#endif
}
status->txBuffer.requestedLength = sizeof(USARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
status->txBuffer.busy = 1;
status->txBuffer.error = 0;
EnqueueCrcTask(crcStatus, status->txCrcSlot, status->txBuffer.packet.payload, length,
NULL, (uint32_t*)(status->txBuffer.packet.payload + payloadLength));
while(IsSlotQueued(crcStatus, status->txCrcSlot));
SetupTransmit(status->usart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
StatsIncSent(&status->stats);
return 0;
}
void SetupReceive(USARTSTATUS *status)
{
uint8_t packetIndex = status->activeRxBuf;
LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->usart), (uint32_t)&status->rxBuffers[packetIndex],
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
status->rxBuffers[packetIndex].requestedLength = sizeof(status->rxBuffers[packetIndex].packet);
LL_DMA_SetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream, status->rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
LL_USART_EnableDMAReq_RX(status->usart);
LL_USART_ClearFlag_ORE(status->usart);
LL_DMA_EnableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
}
void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex, CRCSTATUS *crcStatus)
{
struct usart_buffer *buffer = &status->rxBuffers[packetIndex];
if(buffer->busy) {
if(buffer->error)
StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + RoundUpTo4(buffer->packet.header.payloadLength + 1)));
else {
uint8_t diff = buffer->packet.header.serial - status->rxSerial;
if(diff > 1)
StatsAddSkiped(&status->stats, diff - 1);
status->rxSerial = buffer->packet.header.serial;
}
}
buffer->busy = buffer->error = 0;
}
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
{
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
LL_DMA_SetDataLength(dma, stream, length);
LL_USART_EnableDMAReq_TX(usart);
LL_DMA_EnableStream(dma, stream);
}
void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
{
struct usart_buffer *ub = (struct usart_buffer*) callbackParm;
if(!success)
ub->error = 1;
else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength + 1)) == calculatedCrc)
ub->busy = 1;
else {
ub->error = ub->busy = 1;
ub->errorInfo = calculatedCrc;
}
if(ub->usartStatus->packetReceivedCallback)
ub->usartStatus->packetReceivedCallback(ub->usartStatus->packetReceivedCallbacParam, ub);
}
void HandleUsartRxDmaIrq(USARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
StatsIncRcvd(&status->stats);
if(*status->rxDmaInfo.isReg & status->rxDmaInfo.tcMask) {
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.tcMask;
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet))
EnqueueCrcTask(status->crcStatus, status->rxCrcSlot,
status->rxBuffers[status->activeRxBuf].packet.payload,
status->rxBuffers[status->activeRxBuf].packet.header.payloadLength +1,
RxCrcComputedCallback, &status->rxBuffers[status->activeRxBuf]);
else {
StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
status->rxBuffers[status->activeRxBuf].error = 1;
}
} else if(*status->rxDmaInfo.isReg & status->rxDmaInfo.teMask) {
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.teMask;
status->rxBuffers[status->activeRxBuf].error = 1;
}
status->activeRxBuf ^= 1;
DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
if(status->rxBuffers[status->activeRxBuf].busy)
StatsIncOverrun(&status->stats);
SetupReceive(status);
DIAG_INTERRUPT_OUT();
}
void HandleUsartTxDmaIrq(USARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
LL_USART_EnableIT_TC(status->usart);
LL_DMA_DisableStream(status->txDmaInfo.dma, status->txDmaInfo.stream);
}
else if(*status->txDmaInfo.isReg & status->txDmaInfo.teMask) {
*status->txDmaInfo.ifcReg = status->txDmaInfo.teMask;
status->txBuffer.error = 1;
StatsIncDmaError(&status->stats);
}
if(*status->txDmaInfo.isReg & status->txDmaInfo.feMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.feMask;
if(*status->txDmaInfo.isReg & status->txDmaInfo.htMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.htMask;
if(*status->txDmaInfo.isReg & status->txDmaInfo.dmeMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.dmeMask;
DIAG_INTERRUPT_OUT();
}
void HandleUsartIrq(USARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
LL_USART_ClearFlag_IDLE(status->usart);
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
if(rcvdLen >= sizeof(USARTPACKETHEADER)) {
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
if(rcvdLen >= sizeof(USARTPACKETHEADER) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
else
StatsIncPremature_payload(&status->stats);
} else {
status->rxBuffers[status->activeRxBuf].error = 1;
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
}
} else
StatsIncPremature_hdr(&status->stats);
}
else if(LL_USART_IsActiveFlag_TC(status->usart) && LL_USART_IsEnabledIT_TC(status->usart)) { // transmission complete
LL_USART_DisableIT_TC(status->usart);
LL_USART_DisableDirectionTx(status->usart); // enforcing an idle frame
LL_USART_EnableDirectionTx(status->usart);
status->txBuffer.busy = 0;
}
DIAG_INTERRUPT_OUT();
}