258 lines
8.8 KiB
C
258 lines
8.8 KiB
C
/*
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* usart_handler.c
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*
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* Created on: Sep 16, 2019
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* Author: abody
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*/
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#include <string.h>
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#include <platform/usart_ll.h>
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#include "diag.h"
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#include "usart_handler.h"
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#include "dma_helper.h"
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#include "crc_handler.h"
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#include "memcpy_dma.h"
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#ifndef DIAG_RX_BUFFER_SWITCH
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# define DIAG_RX_BUFFER_SWITCH(x)
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#endif
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#ifndef DIAG_INTERRUPT_IN
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# define DIAG_INTERRUPT_IN()
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#endif
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#ifndef DIAG_INTERRUPT_OUT
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# define DIAG_INTERRUPT_OUT()
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#endif
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#define STARTMARKER 0x95
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static inline uint32_t RoundUpTo4(uint32_t inp)
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{
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return (inp + 3) & 0xfffc;
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}
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void InitUartStatus(
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USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
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uint32_t stream_rx, uint32_t stream_tx,
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CRCSTATUS *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot,
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PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
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{
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st->usart = usart;
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InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
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InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
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st->txBuffer.busy = 0;
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st->txBuffer.error = 0;
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st->txBuffer.requestedLength = 0;
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st->rxBuffers[0].busy = 0;
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st->rxBuffers[1].busy = 0;
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st->rxBuffers[0].error = 0;
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st->rxBuffers[1].error = 0;
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st->rxBuffers[0].requestedLength = 0;
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st->rxBuffers[1].requestedLength = 0;
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st->txBuffer.usartStatus = st;
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st->rxBuffers[0].usartStatus = st;
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st->rxBuffers[1].usartStatus = st;
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st->packetReceivedCallback = packetReceivedCallback;
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st->packetReceivedCallbacParam = packetReceivedCallbackParam;
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st->rxSerial = -1;
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st->txSerial = 0;
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st->activeRxBuf = 0;
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st->crcStatus = crcStatus;
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st->txCrcSlot = txCrcSlot;
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st->rxCrcSlot = rxCrcSlot;
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memset(&st->stats, 0, sizeof(st->stats));
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LL_DMA_EnableIT_TC(dma, stream_rx);
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LL_DMA_EnableIT_TE(dma, stream_rx);
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LL_DMA_EnableIT_TC(dma, stream_tx);
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LL_DMA_EnableIT_TE(dma, stream_tx);
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LL_USART_EnableIT_IDLE(usart);
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}
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uint8_t* GetTxBuffer(USARTSTATUS *status)
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{
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return status->txBuffer.packet.payload;
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}
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static inline void BuildHeader(struct usart_buffer *buffer, uint8_t serial, uint8_t length)
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{
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uint8_t hash = STARTMARKER;
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buffer->packet.header.startByte = STARTMARKER;
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buffer->packet.header.serial = serial;
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hash ^= serial;
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buffer->packet.header.payloadLength = length - 1;
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hash ^= length - 1;
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buffer->packet.header.hash = hash;
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}
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static inline uint8_t CheckHeader(USARTPACKET *packet)
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{
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return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
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}
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uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, CRCSTATUS *crcStatus)
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{
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if(length > 256)
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return 1;
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BuildHeader(&status->txBuffer, status->txSerial++, length);
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uint16_t payloadLength = RoundUpTo4(length);
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if(payload) {
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#ifdef USART_USE_MEMCPY_DMA
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if((uint32_t)payload & 3)
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memcpy(status->txBuffer.packet.payload, payload, length);
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else
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MemcpyDma(status->txBuffer.packet.payload, payload, length);
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#else
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memcpy(status->txBuffer.packet.payload, payload, length);
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#endif
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}
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status->txBuffer.requestedLength = sizeof(USARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
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status->txBuffer.busy = 1;
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status->txBuffer.error = 0;
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EnqueueCrcTask(crcStatus, status->txCrcSlot, status->txBuffer.packet.payload, length,
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NULL, (uint32_t*)(status->txBuffer.packet.payload + payloadLength));
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while(IsSlotQueued(crcStatus, status->txCrcSlot));
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SetupTransmit(status->usart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
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StatsIncSent(&status->stats);
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return 0;
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}
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void SetupReceive(USARTSTATUS *status)
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{
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uint8_t packetIndex = status->activeRxBuf;
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LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->usart), (uint32_t)&status->rxBuffers[packetIndex],
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LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
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status->rxBuffers[packetIndex].requestedLength = sizeof(status->rxBuffers[packetIndex].packet);
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LL_DMA_SetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream, status->rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
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LL_USART_EnableDMAReq_RX(status->usart);
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LL_USART_ClearFlag_ORE(status->usart);
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LL_DMA_EnableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
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}
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void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex, CRCSTATUS *crcStatus)
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{
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struct usart_buffer *buffer = &status->rxBuffers[packetIndex];
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if(buffer->busy) {
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if(buffer->error)
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StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + RoundUpTo4(buffer->packet.header.payloadLength + 1)));
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else {
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uint8_t diff = buffer->packet.header.serial - status->rxSerial;
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if(diff > 1)
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StatsAddSkiped(&status->stats, diff - 1);
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status->rxSerial = buffer->packet.header.serial;
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}
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}
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buffer->busy = buffer->error = 0;
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}
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void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
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{
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LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
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LL_DMA_SetDataLength(dma, stream, length);
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LL_USART_EnableDMAReq_TX(usart);
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LL_DMA_EnableStream(dma, stream);
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}
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void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
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{
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struct usart_buffer *ub = (struct usart_buffer*) callbackParm;
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if(!success)
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ub->error = 1;
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else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength + 1)) == calculatedCrc)
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ub->busy = 1;
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else {
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ub->error = ub->busy = 1;
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ub->errorInfo = calculatedCrc;
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}
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if(ub->usartStatus->packetReceivedCallback)
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ub->usartStatus->packetReceivedCallback(ub->usartStatus->packetReceivedCallbacParam, ub);
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}
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void HandleUsartRxDmaIrq(USARTSTATUS *status)
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{
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DIAG_INTERRUPT_IN();
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StatsIncRcvd(&status->stats);
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if(*status->rxDmaInfo.isReg & status->rxDmaInfo.tcMask) {
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*status->rxDmaInfo.ifcReg = status->rxDmaInfo.tcMask;
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if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet))
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EnqueueCrcTask(status->crcStatus, status->rxCrcSlot,
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status->rxBuffers[status->activeRxBuf].packet.payload,
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status->rxBuffers[status->activeRxBuf].packet.header.payloadLength +1,
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RxCrcComputedCallback, &status->rxBuffers[status->activeRxBuf]);
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else {
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StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
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status->rxBuffers[status->activeRxBuf].error = 1;
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}
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} else if(*status->rxDmaInfo.isReg & status->rxDmaInfo.teMask) {
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*status->rxDmaInfo.ifcReg = status->rxDmaInfo.teMask;
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status->rxBuffers[status->activeRxBuf].error = 1;
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}
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status->activeRxBuf ^= 1;
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DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
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if(status->rxBuffers[status->activeRxBuf].busy)
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StatsIncOverrun(&status->stats);
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SetupReceive(status);
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DIAG_INTERRUPT_OUT();
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}
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void HandleUsartTxDmaIrq(USARTSTATUS *status)
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{
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DIAG_INTERRUPT_IN();
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if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
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*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
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LL_USART_EnableIT_TC(status->usart);
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LL_DMA_DisableStream(status->txDmaInfo.dma, status->txDmaInfo.stream);
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}
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else if(*status->txDmaInfo.isReg & status->txDmaInfo.teMask) {
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*status->txDmaInfo.ifcReg = status->txDmaInfo.teMask;
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status->txBuffer.error = 1;
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StatsIncDmaError(&status->stats);
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}
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if(*status->txDmaInfo.isReg & status->txDmaInfo.feMask)
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*status->txDmaInfo.ifcReg = status->txDmaInfo.feMask;
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if(*status->txDmaInfo.isReg & status->txDmaInfo.htMask)
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*status->txDmaInfo.ifcReg = status->txDmaInfo.htMask;
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if(*status->txDmaInfo.isReg & status->txDmaInfo.dmeMask)
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*status->txDmaInfo.ifcReg = status->txDmaInfo.dmeMask;
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DIAG_INTERRUPT_OUT();
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}
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void HandleUsartIrq(USARTSTATUS *status)
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{
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DIAG_INTERRUPT_IN();
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if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
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LL_USART_ClearFlag_IDLE(status->usart);
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uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
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if(rcvdLen >= sizeof(USARTPACKETHEADER)) {
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if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
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if(rcvdLen >= sizeof(USARTPACKETHEADER) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
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LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
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else
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StatsIncPremature_payload(&status->stats);
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} else {
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status->rxBuffers[status->activeRxBuf].error = 1;
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LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
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}
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} else
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StatsIncPremature_hdr(&status->stats);
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}
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else if(LL_USART_IsActiveFlag_TC(status->usart) && LL_USART_IsEnabledIT_TC(status->usart)) { // transmission complete
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LL_USART_DisableIT_TC(status->usart);
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LL_USART_DisableDirectionTx(status->usart); // enforcing an idle frame
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LL_USART_EnableDirectionTx(status->usart);
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status->txBuffer.busy = 0;
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}
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DIAG_INTERRUPT_OUT();
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}
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