Divided USART communication into core and protocol classes
This commit is contained in:
parent
9ff4e76623
commit
f0c2ad69c9
7 changed files with 287 additions and 121 deletions
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@ -223,7 +223,7 @@ void SysTick_Handler(void)
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void DMA1_Stream1_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
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f4ll::LL_HsUsart::HandleRxDmaIrq(g_usarts[USART3_OFFSET]);
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f4ll::LL_UsartCore::HandleRxDmaIrq(g_usarts[USART3_OFFSET]);
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/* USER CODE END DMA1_Stream1_IRQn 0 */
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/* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
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@ -46,7 +46,8 @@ void _PrintStats(char *buffer, uint8_t id, f4ll::LL_HsUsart &handler, USART_Type
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buffer += uitohex(buffer, stats.pep1, 8);
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buffer += strcpy_ex(buffer,",0x");
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buffer += uitohex(buffer, stats.pep2, 8);
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ADDINFO(buffer, " de: ", stats.dmaError);
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ADDINFO(buffer, " rde: ", stats.rxDmaError);
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ADDINFO(buffer, " tde: ", stats.txDmaError);
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ADDINFO(buffer, " pmh: ", stats.premature_hdr);
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ADDINFO(buffer, " pmp: ", stats.premature_payload);
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buffer += strcpy_ex(buffer, "\r\n");
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@ -69,7 +70,7 @@ extern "C" void MainLoop()
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f4ll::LL_HsUsart u3{ USART3, DMA1, LL_DMA_STREAM_1, LL_DMA_STREAM_3 };
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f4ll::LL_HsUsart u6{ USART6, DMA2, LL_DMA_STREAM_1, LL_DMA_STREAM_6 };
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f4ll::LL_HsUsart * usarts[] = { & u1, &u2, &u3, &u6 };
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f4ll::LL_HsUsart * usarts[] = { &u1, &u2, &u3, &u6 };
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for(unsigned int i=0; i < sizeof(usarts) / sizeof(usarts[0]); ++i)
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g_usarts[i] = usarts[i];
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@ -28,9 +28,21 @@ public:
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inline uint32_t GetHtMask() const { return m_HTMasks[m_stream]; }
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inline uint32_t GetTcMask() const { return m_TCMasks[m_stream]; }
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inline bool IsEnabledIt_HT() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TE() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TC() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_DME() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_FE() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
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enum class DmaErrorType {
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Transfer,
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DirectMode,
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Fifo
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};
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private:
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DMA_TypeDef *m_dma;
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uint32_t m_stream;
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uint32_t m_stream;
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volatile uint32_t *m_isReg;
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volatile uint32_t *m_ifcReg;
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@ -14,19 +14,11 @@ template<typename T> static inline T RoundUpTo4(T input)
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return (input + 3) & (((T)-1) - 3);
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}
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LL_HsUsart::LL_HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
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: m_usart(usart)
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, m_rxDma(dma, streamRx)
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, m_txDma(dma, streamTx)
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: LL_UsartCore(usart, dma, streamRx, streamTx)
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{
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LL_CrcHandler::Instance().AttachSlot(m_crcSlot);
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LL_DMA_EnableIT_TC(dma, streamRx);
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LL_DMA_EnableIT_TE(dma, streamRx);
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LL_DMA_EnableIT_TC(dma, streamTx);
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LL_DMA_EnableIT_TE(dma, streamTx);
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LL_USART_EnableIT_IDLE(usart);
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memset(&m_stats, 0, sizeof(m_stats));
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}
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@ -119,11 +111,7 @@ void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFor
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while(waitForCrcQueue && LL_CrcHandler::Instance().IsQueued(m_crcSlot, 0));
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LL_DMA_ConfigAddresses(m_txDma.GetDma(), m_txDma.GetStream(), reinterpret_cast<uint32_t>(&m_txBuffer.packet),
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LL_USART_DMA_GetRegAddr(m_usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
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LL_DMA_SetDataLength(m_txDma.GetDma(), m_txDma.GetStream(), m_txBuffer.requestedLength);
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LL_USART_EnableDMAReq_TX(m_usart);
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LL_DMA_EnableStream(m_txDma.GetDma(), m_txDma.GetStream());
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SetupTransmit(&m_txBuffer.packet, m_txBuffer.requestedLength);
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++m_stats.sent;
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}
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@ -131,67 +119,87 @@ void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitFor
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void LL_HsUsart::SetupReceive()
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{
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int packetIndex = m_rxBufferSelector;
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LL_DMA_ConfigAddresses(m_rxDma.GetDma(), m_rxDma.GetStream(), LL_USART_DMA_GetRegAddr(m_usart),
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reinterpret_cast<uint32_t>(&m_rxBuffers[packetIndex]), LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
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m_rxBuffers[packetIndex].requestedLength = sizeof(m_rxBuffers[packetIndex].packet);
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LL_DMA_SetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream(), m_rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
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LL_USART_EnableDMAReq_RX(m_usart);
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LL_USART_ClearFlag_ORE(m_usart);
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LL_DMA_EnableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
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m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
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LL_UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
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}
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void LL_HsUsart::UsartIrq(void)
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void LL_HsUsart::ReceiverIdle(void)
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{
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if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) { // receiver idle
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LL_USART_ClearFlag_IDLE(m_usart);
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uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
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if(rcvdLen >= sizeof(PacketHeader)) {
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if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
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if(rcvdLen >= sizeof(PacketHeader) +
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RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength)
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+ sizeof(uint32_t))
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LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
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else
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++m_stats.premature_payload;
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} else {
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m_rxBuffers[m_rxBufferSelector].error = 1;
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uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
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if(rcvdLen >= sizeof(PacketHeader)) {
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if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
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if(rcvdLen >= sizeof(PacketHeader) +
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RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength)
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+ sizeof(uint32_t))
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LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
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}
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} else
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++m_stats.premature_hdr;
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}
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else if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
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LL_USART_DisableIT_TC(m_usart);
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LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
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LL_USART_EnableDirectionTx(m_usart);
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m_txBuffer.busy = 0;
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}
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else
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++m_stats.premature_payload;
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} else {
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m_rxBuffers[m_rxBufferSelector].error = 1;
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LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
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}
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} else
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++m_stats.premature_hdr;
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}
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void LL_HsUsart::RxDmaIrq()
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void LL_HsUsart::TransmissionComplete(void)
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{
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LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
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LL_USART_EnableDirectionTx(m_usart);
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m_txBuffer.busy = 0;
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}
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void LL_HsUsart::RxDmaTransferComplete(void)
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{
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if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
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LL_CrcHandler::Instance().Enqueue(m_crcSlot, 1,
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&m_rxBuffers[m_rxBufferSelector].packet,
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sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength),
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this, m_rxBufferSelector);
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else {
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++m_stats.hdrError;
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m_rxBuffers[m_rxBufferSelector].error = true;
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}
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SwitchRxBuffers();
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}
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void LL_HsUsart::RxDmaHalfTransfer(void)
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{
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}
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void LL_HsUsart::RxDmaError(LL_DmaHelper::DmaErrorType reason)
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{
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m_rxBuffers[m_rxBufferSelector].error = 1;
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++m_stats.rxDmaError;
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SwitchRxBuffers();
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}
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void LL_HsUsart::TxDmaTransferComplete(void)
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{
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LL_USART_EnableIT_TC(m_usart);
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LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
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}
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void LL_HsUsart::TxDmaHalfTransfer(void)
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{
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}
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void LL_HsUsart::TxDmaError(LL_DmaHelper::DmaErrorType reason)
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{
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m_txBuffer.error = 1;
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++m_stats.txDmaError;
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}
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void LL_HsUsart::SwitchRxBuffers(void)
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{
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++m_stats.rcvd;
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if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
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*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
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if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
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LL_CrcHandler::Instance().Enqueue(m_crcSlot, 1,
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&m_rxBuffers[m_rxBufferSelector].packet,
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sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength),
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this, m_rxBufferSelector);
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else {
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++m_stats.hdrError;
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m_rxBuffers[m_rxBufferSelector].error = true;
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}
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} else if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
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*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
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m_rxBuffers[m_rxBufferSelector].error = 1;
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++m_stats.dmaError;
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}
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m_rxBufferSelector = !m_rxBufferSelector;
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if(m_rxBuffers[m_rxBufferSelector].busy)
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@ -226,25 +234,4 @@ void LL_HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, int prio)
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}
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void LL_HsUsart::TxDmaIrq()
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{
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if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
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*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
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LL_USART_EnableIT_TC(m_usart);
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LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
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}
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else if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
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*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
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m_txBuffer.error = 1;
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++m_stats.dmaError;
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}
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if(*m_txDma.GetIsReg() & m_txDma.GetFeMask())
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*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
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if(*m_txDma.GetIsReg() & m_txDma.GetHtMask())
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*m_txDma.GetIfcReg() = m_txDma.GetHtMask();
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if(*m_txDma.GetIsReg() & m_txDma.GetDmeMask())
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*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
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}
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} // namespace f4ll
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@ -8,13 +8,14 @@
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#ifndef LL_HSUSART_H_
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#define LL_HSUSART_H_
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#include <platform/usart_ll.h>
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#include <ll_usartcore.h>
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#include <ll_crchandler.h>
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namespace f4ll {
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struct DMAINFO;
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class LL_HsUsart : public LL_CrcHandler::ICallback
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class LL_HsUsart : public LL_CrcHandler::ICallback, public LL_UsartCore
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{
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public:
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LL_HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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@ -32,55 +33,56 @@ public:
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} __attribute__((aligned));
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struct Stats {
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uint32_t overrun;
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uint32_t hdrError;
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uint32_t payloadErrror;
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uint32_t pep1, pep2;
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uint32_t dmaError;
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uint32_t rcvd;
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uint32_t premature_hdr;
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uint32_t premature_payload;
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uint32_t sent;
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uint32_t skiped;
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uint32_t overrun = 0;
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uint32_t hdrError = 0;
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uint32_t payloadErrror = 0;
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uint32_t pep1 = 0;
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uint32_t pep2 = 0;
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uint32_t rxDmaError = 0;
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uint32_t txDmaError = 0;
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uint32_t rcvd = 0;
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uint32_t premature_hdr = 0;
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uint32_t premature_payload = 0;
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uint32_t sent = 0;
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uint32_t skiped = 0;
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};
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struct IHsUsartCallback {
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virtual bool PacketReceived(LL_HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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};
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//LL_CRCHandler::ICallback interface functions
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// LL_CRCHandler::ICallback interface functions
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, int prio);
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, int prio);
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason);
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void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
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void SetupReceive(void);
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void RxProcessed(bool second);
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uint8_t* GetTxPacketBuffer(void);
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USART_TypeDef* GetUsart(void);
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Stats const & GetStats();
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bool IsTxBusy();
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bool IsTxFailed();
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Stats const & GetStats(void);
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bool IsTxBusy(void);
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bool IsTxFailed(void);
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bool IsRxBusy(bool second);
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bool IsRxFailed(bool second);
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void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
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static inline void HandleUsartIrq(LL_HsUsart *obj) {
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obj->UsartIrq();
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}
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static inline void HandleRxDmaIrq(LL_HsUsart *obj) {
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obj->RxDmaIrq();
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}
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static inline void HandleTxDmaIrq(LL_HsUsart *obj) {
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obj->TxDmaIrq();
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}
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private:
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void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
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bool CheckHeader(PacketHeader &header);
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void UsartIrq(void);
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void RxDmaIrq(void);
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void TxDmaIrq(void);
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void SwitchRxBuffers(void);
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struct Buffer {
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Packet packet;
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@ -93,9 +95,6 @@ private:
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static const uint8_t STARTMARKER = 0x95;
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USART_TypeDef *m_usart;
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LL_DmaHelper m_rxDma;
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LL_DmaHelper m_txDma;
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uint8_t m_rxSerialNo = -1;
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uint8_t m_txSerialNo = -1;
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Stats m_stats;
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116
lib/ll_usartcore.cpp
Normal file
116
lib/ll_usartcore.cpp
Normal file
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@ -0,0 +1,116 @@
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/*
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* ll_dmadrivenusartcore.cpp
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*
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* Created on: Nov 4, 2019
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* Author: abody
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*/
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#include <ll_usartcore.h>
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namespace f4ll {
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LL_UsartCore::LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
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: m_usart(usart)
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, m_rxDma(dma, streamRx)
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, m_txDma(dma, streamTx)
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{
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LL_DMA_EnableIT_TC(dma, streamRx);
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LL_DMA_EnableIT_TE(dma, streamRx);
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LL_DMA_EnableIT_TC(dma, streamTx);
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LL_DMA_EnableIT_TE(dma, streamTx);
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LL_USART_EnableIT_IDLE(usart);
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}
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void LL_UsartCore::UsartIsr()
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{
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if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) { // receiver idle
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LL_USART_ClearFlag_IDLE(m_usart);
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ReceiverIdle();
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} else if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
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LL_USART_DisableIT_TC(m_usart);
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TransmissionComplete();
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||||
}
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::RxDmaIsr()
|
||||
{
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
|
||||
if(m_rxDma.IsEnabledIt_TC())
|
||||
RxDmaTransferComplete();
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetHtMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetHtMask();
|
||||
if(m_rxDma.IsEnabledIt_HT())
|
||||
RxDmaHalfTransfer();
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
|
||||
if(m_rxDma.IsEnabledIt_TE())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::Transfer);
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetFeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetFeMask();
|
||||
if(m_rxDma.IsEnabledIt_FE())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::Fifo);
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetDmeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetDmeMask();
|
||||
if(m_rxDma.IsEnabledIt_DME())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::DirectMode);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::TxDmaIsr()
|
||||
{
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
|
||||
if(m_txDma.IsEnabledIt_TC())
|
||||
TxDmaTransferComplete();
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetHtMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetHtMask();
|
||||
if(m_txDma.IsEnabledIt_HT())
|
||||
TxDmaHalfTransfer();
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
|
||||
if(m_txDma.IsEnabledIt_TE())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::Transfer);
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetFeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
|
||||
if(m_txDma.IsEnabledIt_FE())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::Fifo);
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetDmeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
|
||||
if(m_txDma.IsEnabledIt_DME())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::DirectMode);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::SetupTransmit(void const *buffer, uint16_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(m_txDma.GetDma(), m_txDma.GetStream(), reinterpret_cast<uint32_t>(buffer),
|
||||
LL_USART_DMA_GetRegAddr(m_usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_SetDataLength(m_txDma.GetDma(), m_txDma.GetStream(), length);
|
||||
LL_USART_EnableDMAReq_TX(m_usart);
|
||||
LL_DMA_EnableStream(m_txDma.GetDma(), m_txDma.GetStream());
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::SetupReceive(void *buffer, uint16_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(m_rxDma.GetDma(), m_rxDma.GetStream(), LL_USART_DMA_GetRegAddr(m_usart),
|
||||
reinterpret_cast<uint32_t>(buffer), LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
||||
LL_DMA_SetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream(), length);
|
||||
LL_USART_EnableDMAReq_RX(m_usart);
|
||||
LL_USART_ClearFlag_ORE(m_usart);
|
||||
LL_DMA_EnableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
}
|
||||
|
||||
} /* namespace f4ll */
|
51
lib/ll_usartcore.h
Normal file
51
lib/ll_usartcore.h
Normal file
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* ll_dmadrivenusartcore.h
|
||||
*
|
||||
* Created on: Nov 4, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef LL_USARTCORE_H_
|
||||
#define LL_USARTCORE_H_
|
||||
#include <platform/usart_ll.h>
|
||||
|
||||
#include "ll_dmahelper.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
class LL_UsartCore
|
||||
{
|
||||
public:
|
||||
static inline void HandleUsartIrq(LL_UsartCore *_this) { _this->UsartIsr(); }
|
||||
static inline void HandleRxDmaIrq(LL_UsartCore *_this) { _this->RxDmaIsr(); }
|
||||
static inline void HandleTxDmaIrq(LL_UsartCore *_this) { _this->TxDmaIsr(); }
|
||||
|
||||
protected:
|
||||
LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
|
||||
|
||||
virtual void ReceiverIdle() = 0;
|
||||
virtual void TransmissionComplete() = 0;
|
||||
|
||||
virtual void RxDmaTransferComplete() = 0;
|
||||
virtual void RxDmaHalfTransfer() = 0;
|
||||
virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason) = 0;
|
||||
|
||||
virtual void TxDmaTransferComplete() = 0;
|
||||
virtual void TxDmaHalfTransfer() = 0;
|
||||
virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason) = 0;
|
||||
|
||||
void SetupTransmit(void const *buffer, uint16_t length);
|
||||
void SetupReceive(void *buffer, uint16_t length);
|
||||
|
||||
void UsartIsr();
|
||||
void RxDmaIsr();
|
||||
void TxDmaIsr();
|
||||
|
||||
USART_TypeDef *m_usart;
|
||||
LL_DmaHelper m_rxDma;
|
||||
LL_DmaHelper m_txDma;
|
||||
};
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
||||
#endif /* LL_USARTCORE_H_ */
|
Loading…
Add table
Add a link
Reference in a new issue