playground-stm32/f407ve_hs_uart
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usart_handler: DMA based memory copy

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This commit is contained in:
Attila Body 2019-10-01 14:49:10 +02:00
parent e8ab90c2b3
commit ecd6c1d5d6
13 changed files with 367 additions and 408 deletions
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21
app/application.c
View file

@ -1,4 +1,5 @@
#include <string.h>
#include <stdlib.h>
#include "application.h"
#include "globals.h"
#include "strutil.h"
@ -6,6 +7,7 @@
#include "usart_handler.h"
#include "crc_handler.h"
#include "console_handler.h"
#include "memcpy_dma.h"
#define PACKAGE_DELAY_MS 0
#define STATS_DELAY_MS 1000
@ -21,7 +23,9 @@
void MainLoop()
{
static uint8_t const text2Send[] = "------------------------------------------------\r\n| Megszentsegtelenithetetlensegeskedeseitekert |\r\n------------------------------------------------\r\n";
uint8_t const text2Send[] __attribute__((aligned(4))) =
"Megszentsegtelenithetetlensegeskedeseitekert\r\n"
"--------------------------------------------\r\n\0\0\0";
struct initdata_t {
USART_TypeDef* uart;
@ -40,6 +44,14 @@ void MainLoop()
uint32_t prevSentTick = 0;
uint8_t statId = 0;
uint32_t tmp = sizeof(text2Send) - 1;
uint32_t randmask = 0x80000000;
do
if(randmask & tmp)
break;
while((randmask = randmask >> 1));
randmask -= 1;
for(uint16_t idx = 0; idx < sizeof(g_uartStatuses) / sizeof(g_uartStatuses[0]); ++idx) {
struct initdata_t const *id = &initdata[idx];
InitUartStatus(&g_uartStatuses[idx], id->uart, id->dma, id->stream_rx, id->stream_tx,
@ -49,9 +61,10 @@ void MainLoop()
InitCrcStatus(&g_crcStatus, DMA2, LL_DMA_STREAM_4);
InitDmaInfo(&g_ConsoleTxDmaInfo, DMA1, LL_DMA_STREAM_4);
InitDmaInfo(&g_ConsoleTxDmaInfo, CONSOLE_DMA_ENGINE, CONSOLE_TX_DMA_STREAM);
LL_DMA_EnableIT_TC(g_ConsoleTxDmaInfo.dma, g_ConsoleTxDmaInfo.stream);
LL_DMA_EnableIT_TE(g_ConsoleTxDmaInfo.dma, g_ConsoleTxDmaInfo.stream);
InitMemcpyDma(MEMCPY_DMA_ENGINE, MEMCPY_DMA_STREAM);
lastStatsTick = HAL_GetTick();
@ -66,7 +79,7 @@ void MainLoop()
for(uint16_t idx = 0; idx < sizeof(g_uartStatuses) / sizeof(g_uartStatuses[0]); ++idx) {
if(!g_uartStatuses[idx].txBuffer.busy && send) {
PostPacket(&g_uartStatuses[idx], NULL, sizeof(text2Send) -1, &g_crcStatus);
PostPacket(&g_uartStatuses[idx], text2Send, sizeof(text2Send) - 1 - (rand() & randmask), &g_crcStatus);
}
for(uint16_t rIdx = 0; rIdx < 2; ++rIdx)
if(g_uartStatuses[idx].rxBuffers[rIdx].busy || g_uartStatuses[idx].rxBuffers[rIdx].error)

9
app/config.h
View file

@ -16,4 +16,13 @@
#define USART5_OFFSET 3
#define USART6_OFFSET 4
#define CONSOLE_DMA_ENGINE DMA1
#define CONSOLE_TX_DMA_STREAM LL_DMA_STREAM_4
#define CRC_DMA_ENGINE DMA2
#define CRC_DMA_STREAM LL_DMA_STREAM_4
#define MEMCPY_DMA_ENGINE DMA2
#define MEMCPY_DMA_STREAM LL_DMA_STREAM_0
#endif /* CONFIG_H_ */

1
app/diag.h
View file

@ -21,6 +21,7 @@ if(x) { \
#define DIAG_CRC_CALC_END() LL_GPIO_ResetOutputPin(DIAG0_GPIO_Port, DIAG0_Pin)//; LL_GPIO_TogglePin(DIAG3_GPIO_Port, DIAG3_Pin)
#define DIAG_INTERRUPT_IN() LL_GPIO_SetOutputPin(DIAG1_GPIO_Port, DIAG1_Pin)
#define DIAG_INTERRUPT_OUT() LL_GPIO_ResetOutputPin(DIAG1_GPIO_Port, DIAG1_Pin)
#define DIAG_ERROR_EVENT() LL_GPIO_TogglePin(DIAG2_GPIO_Port, DIAG2_Pin)
#else // _ENABLE_DIAG

2
app/stats.h
View file

@ -7,6 +7,7 @@
#ifndef STATS_H_
#define STATS_H_
#include "diag.h"
#ifndef DIAG_ERROR_EVENT
# define DIAG_ERROR_EVENT()
@ -41,6 +42,7 @@ static inline void StatsIncPayloadError(STATS *s, uint32_t pep1, uint32_t pep2)
s->pep2 = pep2;
}
static inline void StatsIncDmaError(STATS *s) {
DIAG_ERROR_EVENT();
++s->dmaError;
}
static inline void StatsIncRcvd(STATS *s) {