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usart_handler: DMA based memory copy

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This commit is contained in:
Attila Body 2019-10-01 14:49:10 +02:00
parent e8ab90c2b3
commit ecd6c1d5d6
13 changed files with 367 additions and 408 deletions
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47
Src/dma.c
View file

@ -61,13 +61,13 @@ void MX_DMA_Init(void)
LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_4, LL_DMA_PERIPH_INCREMENT);
/* Set memory increment mode */
LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_4, LL_DMA_MEMORY_INCREMENT);
LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_4, LL_DMA_MEMORY_NOINCREMENT);
/* Set peripheral data width */
LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_4, LL_DMA_PDATAALIGN_BYTE);
LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_4, LL_DMA_PDATAALIGN_WORD);
/* Set memory data width */
LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_4, LL_DMA_MDATAALIGN_BYTE);
LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_4, LL_DMA_MDATAALIGN_WORD);
/* Enable FIFO mode */
LL_DMA_EnableFifoMode(DMA2, LL_DMA_STREAM_4);
@ -81,6 +81,44 @@ void MX_DMA_Init(void)
/* Set peripheral burst size */
LL_DMA_SetPeriphBurstxfer(DMA2, LL_DMA_STREAM_4, LL_DMA_PBURST_SINGLE);
/* Configure DMA request MEMTOMEM_DMA2_Stream0 */
/* Select channel */
LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_0, LL_DMA_CHANNEL_0);
/* Set transfer direction */
LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_0, LL_DMA_DIRECTION_MEMORY_TO_MEMORY);
/* Set priority level */
LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_0, LL_DMA_PRIORITY_LOW);
/* Set DMA mode */
LL_DMA_SetMode(DMA2, LL_DMA_STREAM_0, LL_DMA_MODE_NORMAL);
/* Set peripheral increment mode */
LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_0, LL_DMA_PERIPH_INCREMENT);
/* Set memory increment mode */
LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_0, LL_DMA_MEMORY_INCREMENT);
/* Set peripheral data width */
LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_0, LL_DMA_PDATAALIGN_WORD);
/* Set memory data width */
LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_0, LL_DMA_MDATAALIGN_WORD);
/* Enable FIFO mode */
LL_DMA_EnableFifoMode(DMA2, LL_DMA_STREAM_0);
/* Set FIFO threshold */
LL_DMA_SetFIFOThreshold(DMA2, LL_DMA_STREAM_0, LL_DMA_FIFOTHRESHOLD_FULL);
/* Set memory burst size */
LL_DMA_SetMemoryBurstxfer(DMA2, LL_DMA_STREAM_0, LL_DMA_MBURST_SINGLE);
/* Set peripheral burst size */
LL_DMA_SetPeriphBurstxfer(DMA2, LL_DMA_STREAM_0, LL_DMA_PBURST_SINGLE);
/* DMA interrupt init */
/* DMA1_Stream0_IRQn interrupt configuration */
NVIC_SetPriority(DMA1_Stream0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
@ -106,6 +144,9 @@ void MX_DMA_Init(void)
/* DMA1_Stream7_IRQn interrupt configuration */
NVIC_SetPriority(DMA1_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(DMA1_Stream7_IRQn);
/* DMA2_Stream0_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(DMA2_Stream0_IRQn);
/* DMA2_Stream1_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(DMA2_Stream1_IRQn);

15
Src/stm32f4xx_it.c
View file

@ -26,6 +26,7 @@
#include "usart_handler.h"
#include "crc_handler.h"
#include "console_handler.h"
#include "memcpy_dma.h"
#include "globals.h"
#include "diag.h"
@ -380,6 +381,20 @@ void UART5_IRQHandler(void)
/* USER CODE END UART5_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream0 global interrupt.
*/
void DMA2_Stream0_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
HandleMemcpyDmaIrq();
/* USER CODE END DMA2_Stream0_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
/* USER CODE END DMA2_Stream0_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream1 global interrupt.
*/