playground-stm32/f407ve_hs_uart
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This commit is contained in:
Attila Body 2025-06-08 23:15:46 +02:00
parent 66c9d451ab
commit eaf7ebc191
Signed by: abody
GPG key ID: BD0C6214E68FB5CF
5 changed files with 128 additions and 127 deletions
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20
components/f4ll/inc/f4ll/console_handler.h
View file

@ -24,16 +24,16 @@ private:
console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
// LL_UsartCore pure virtual function implementations
virtual void receiver_idle(void);
virtual void transmission_complete(void);
virtual void framing_error(void);
virtual void overrun(void);
virtual void rx_dma_transfer_complete(void);
virtual void rx_dma_half_transfer(void);
virtual void rx_dma_error(dma_helper::dma_error_type reason);
virtual void tx_dma_transfer_complete(void);
virtual void tx_dma_half_transfer(void);
virtual void tx_dma_error(dma_helper::dma_error_type reason);
virtual void receiver_idle(void) override;
virtual void transmission_complete(void) override;
virtual void framing_error(void) override;
virtual void overrun(void) override;
virtual void rx_dma_transfer_complete(void) override;
virtual void rx_dma_half_transfer(void) override;
virtual void rx_dma_error(dma_helper::dma_error_type reason) override;
virtual void tx_dma_transfer_complete(void) override;
virtual void tx_dma_half_transfer(void) override;
virtual void tx_dma_error(dma_helper::dma_error_type reason) override;
char m_buffer[128];
uint16_t m_used = 0;

10
components/f4ll/inc/f4ll/dma_helper.h
View file

@ -29,11 +29,11 @@ public:
inline uint32_t get_ht_mask() const { return m_ht_masks[m_stream]; }
inline uint32_t get_tc_mask() const { return m_tc_masks[m_stream]; }
inline bool is_enabled_it_ht() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
inline bool is_enabled_it_te() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
inline bool is_enabled_it_tc() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
inline bool is_enabled_it_dme() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
inline bool is_enabled_it_fe() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
inline bool is_enabled_it_ht() const { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
inline bool is_enabled_it_te() const { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
inline bool is_enabled_it_tc() const { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
inline bool is_enabled_it_dme() const { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
inline bool is_enabled_it_fe() const { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
enum class dma_error_type { transfer, direct_mode, fifo };

94
components/f4ll/inc/f4ll/packet_usart.h
View file

@ -29,21 +29,21 @@ public:
uint8_t hash;
};
struct Packet
struct packet
{
packet_header header;
uint8_t payload[256 + sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned));
struct Stats
struct stats
{
uint32_t overrun = 0;
uint32_t hdrError = 0;
uint32_t payloadErrror = 0;
uint32_t hdr_error = 0;
uint32_t payload_errror = 0;
uint32_t pep1 = 0;
uint32_t pep2 = 0;
uint32_t rxDmaError = 0;
uint32_t txDmaError = 0;
uint32_t rx_dma_error = 0;
uint32_t tx_dma_error = 0;
uint32_t rcvd = 0;
uint32_t premature_hdr = 0;
uint32_t premature_payload = 0;
@ -51,71 +51,71 @@ public:
uint32_t skiped = 0;
};
struct IHsUsartCallback
struct ihs_usart_callback
{
virtual bool PacketReceived(packet_usart *caller, uintptr_t userParam, Packet const &packet) = 0;
virtual bool packet_received(packet_usart *caller, uintptr_t user_param, packet const &packet) = 0;
};
// crc_handler::ICallback interface functions
virtual void crc_succeeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
virtual void crc_failed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
virtual void crc_succeeded(uintptr_t callback_param, uint32_t crc, uint8_t task) override;
virtual void crc_failed(uintptr_t callback_param, uint32_t crc, uint8_t task) override;
void PostPacket(uint8_t const *payload, uint8_t length, bool wait_for_crc_queue = true);
void SetupReceive(void);
void post_packet(uint8_t const *payload, uint8_t length, bool wait_for_crc_queue = true);
void setup_receive(void);
void RxProcessed(bool second);
void rx_processed(bool second);
// Getters
uint8_t *GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
uint8_t const *GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
USART_TypeDef *GetUsart(void) const { return m_usart; }
Stats const &GetStats(void) const { return m_stats; }
inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
inline bool IsTxFailed(void) const { return m_txBuffer.error; }
inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
uint8_t *get_tx_packet_buffer(void) { return m_tx_buffer.pkt.payload; }
uint8_t const *get_rx_packet_buffer(bool second) { return m_rx_buffers[second].pkt.payload; }
USART_TypeDef *get_usart(void) const { return m_usart; }
stats const &get_stats(void) const { return m_stats; }
inline bool is_tx_busy(void) const { return m_tx_buffer.busy; }
inline bool is_tx_failed(void) const { return m_tx_buffer.error; }
inline bool is_rx_busy(bool second) const { return m_rx_buffers[second].busy; }
inline bool is_rx_failed(bool second) const { return m_rx_buffers[second].error; }
void SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam);
void set_callback(ihs_usart_callback *callback, uintptr_t callback_param);
private:
void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
bool CheckHeader(packet_header &header);
void SwitchRxBuffers(void);
void build_header(packet &packet, uint8_t serial_nr, uint8_t length);
bool check_header(packet_header &header);
void switch_rx_buffers(void);
// UsartCore pure virtual function implementations
virtual void receiver_idle(void);
virtual void transmission_complete(void);
virtual void framing_error(void);
virtual void overrun(void);
virtual void rx_dma_transfer_complete(void);
virtual void rx_dma_half_transfer(void);
virtual void rx_dma_error(dma_helper::dma_error_type reason);
virtual void tx_dma_transfer_complete(void);
virtual void tx_dma_half_transfer(void);
virtual void tx_dma_error(dma_helper::dma_error_type reason);
virtual void receiver_idle(void) override;
virtual void transmission_complete(void) override;
virtual void framing_error(void) override;
virtual void overrun(void) override;
virtual void rx_dma_transfer_complete(void) override;
virtual void rx_dma_half_transfer(void) override;
virtual void rx_dma_error(dma_helper::dma_error_type reason) override;
virtual void tx_dma_transfer_complete(void) override;
virtual void tx_dma_half_transfer(void) override;
virtual void tx_dma_error(dma_helper::dma_error_type reason) override;
struct Buffer
{
Packet packet;
packet pkt;
// transfer area ends here
bool volatile busy = 0;
bool volatile error = 0;
uint16_t requestedLength = 0;
uint32_t errorInfo = 0;
uint16_t requested_length = 0;
uint32_t error_info = 0;
};
static const uint8_t STARTMARKER = 0x95;
uint8_t m_rxSerialNo = -1;
uint8_t m_txSerialNo = -1;
Stats m_stats;
bool m_rxBufferSelector = false;
uint8_t m_rx_serial_nr = -1;
uint8_t m_tx_serial_nr = -1;
stats m_stats;
bool m_rx_buffer_selector = false;
crc_handler::slot<2> m_crcSlot;
IHsUsartCallback *m_userCallback = nullptr;
uintptr_t m_userCallbackParam = 0;
Buffer m_txBuffer;
Buffer m_rxBuffers[2];
crc_handler::slot<2> m_crc_slot;
ihs_usart_callback *m_user_callback = nullptr;
uintptr_t m_user_callback_param = 0;
Buffer m_tx_buffer;
Buffer m_rx_buffers[2];
};
}