Fine-tuning "libs" API
This commit is contained in:
parent
ffec0e2b57
commit
e8cff640ac
18 changed files with 244 additions and 204 deletions
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@ -12,12 +12,12 @@
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#define PACKAGE_DELAY_MS 0
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#define STATS_DELAY_MS 1000
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// UART DMA RX TX
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// USART DMA RX TX
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// 1 2 2 7
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// 2 1 5 6
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// 3 1 1 3
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// 6 2 1 6
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// console UART
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// console USART
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// 4 1 2 4
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void MainLoop()
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@ -53,7 +53,7 @@ void MainLoop()
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for(uint16_t idx = 0; idx < sizeof(g_uartStatuses) / sizeof(g_uartStatuses[0]); ++idx) {
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struct initdata_t const *id = &initdata[idx];
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InitUartStatus(&g_uartStatuses[idx], id->uart, id->dma, id->stream_rx, id->stream_tx,
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&g_crcStatus, idx + UARTCOUNT, idx);
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&g_crcStatus, idx + USARTCOUNT, idx, NULL, NULL);
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memcpy(GetTxBuffer(&g_uartStatuses[idx]), text2Send, sizeof(text2Send) -1);
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}
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@ -92,7 +92,7 @@ void MainLoop()
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PrintStats((char*)g_statsBuf, statId, &g_uartStatuses[statId].stats, UART4, &g_ConsoleTxDmaInfo);
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lastStatsTick += STATS_DELAY_MS;
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++statId;
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if(statId >= UARTCOUNT)
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if(statId >= USARTCOUNT)
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statId = 0;
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}
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uint32_t ein = LL_GPIO_ReadInputPort(KEY1_GPIO_Port);
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@ -10,7 +10,6 @@
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#include <inttypes.h>
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#include "main.h"
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#include <stats.h>
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void MainLoop();
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@ -8,8 +8,8 @@
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#ifndef CONFIG_H_
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#define CONFIG_H_
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#define UARTCOUNT 4
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#define CRCTASKCOUNT (UARTCOUNT * 2)
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#define USARTCOUNT 4
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#define CRCTASKCOUNT (USARTCOUNT * 2)
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#define USART1_OFFSET 0
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#define USART2_OFFSET 1
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#define USART3_OFFSET 2
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@ -7,9 +7,9 @@
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#include "globals.h"
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UARTSTATUS g_uartStatuses[UARTCOUNT];
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USARTSTATUS g_uartStatuses[USARTCOUNT];
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struct crcstatus_t g_crcStatus;
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CRCSTATUS g_crcStatus;
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DMAINFO g_ConsoleTxDmaInfo;
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uint8_t g_statsBuf[128];
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@ -14,9 +14,9 @@
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#include "dma_helper.h"
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#include "crc_handler.h"
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extern UARTSTATUS g_uartStatuses[UARTCOUNT];
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extern USARTSTATUS g_uartStatuses[USARTCOUNT];
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extern struct crcstatus_t g_crcStatus;
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extern CRCSTATUS g_crcStatus;
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extern DMAINFO g_ConsoleTxDmaInfo;
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extern uint8_t g_statsBuf[128];
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6
app/platform/crc_ll.h
Normal file
6
app/platform/crc_ll.h
Normal file
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@ -0,0 +1,6 @@
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#ifndef __PLATFORM_CRC_LL_H_INCLUDED
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#define __PLATFORM_CRC_LL_H_INCLUDED
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#include "crc.h"
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#endif // __PLATFORM_CRC_LL_H_INCLUDED
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6
app/platform/dma_ll.h
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6
app/platform/dma_ll.h
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@ -0,0 +1,6 @@
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#ifndef __PLATFORM_DMA_LL_H_INCLUDED
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#define __PLATFORM_DMA_LL_H_INCLUDED
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#include "dma.h"
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#endif // __PLATFORM_DMA_LL_H_INCLUDED
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6
app/platform/usart_ll.h
Normal file
6
app/platform/usart_ll.h
Normal file
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@ -0,0 +1,6 @@
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#ifndef __PLATFORM_USART_LL_H_INCLUDED
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#define __PLATFORM_USART_LL_H_INCLUDED
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#include "usart.h"
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#endif // __PLATFORM_USART_LL_H_INCLUDED
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68
app/stats.h
68
app/stats.h
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@ -1,68 +0,0 @@
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/*
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* stats.h
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*
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* Created on: Sep 16, 2019
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* Author: abody
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*/
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#ifndef STATS_H_
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#define STATS_H_
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#include "diag.h"
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#ifndef DIAG_ERROR_EVENT
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# define DIAG_ERROR_EVENT()
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#endif
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typedef struct {
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uint32_t overrun;
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uint32_t hdrError;
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uint32_t lastErrHdr;
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uint32_t payloadErrror;
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uint32_t pep1, pep2;
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uint32_t dmaError;
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uint32_t rcvd;
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uint32_t premature_hdr;
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uint32_t premature_payload;
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uint32_t sent;
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uint32_t skiped;
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} STATS;
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#ifndef STATS_DISABLED
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static inline void StatsIncOverrun(STATS *s) {
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++s->overrun;
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}
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static inline void StatsIncHdrError(STATS *s, uint32_t hdr) {
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DIAG_ERROR_EVENT();
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++s->hdrError;
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}
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static inline void StatsIncPayloadError(STATS *s, uint32_t pep1, uint32_t pep2) {
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DIAG_ERROR_EVENT();
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++s->payloadErrror;
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s->pep1 = pep1;
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s->pep2 = pep2;
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}
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static inline void StatsIncDmaError(STATS *s) {
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DIAG_ERROR_EVENT();
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++s->dmaError;
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}
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static inline void StatsIncRcvd(STATS *s) {
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++s->rcvd;
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}
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static inline void StatsIncPremature_hdr(STATS *s) {
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++s->premature_hdr;
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}
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static inline void StatsIncPremature_payload(STATS *s) {
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++s->premature_payload;
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}
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static inline void StatsIncSent(STATS *s) {
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++s->sent;
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}
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static inline void StatsAddSkiped(STATS *s, uint8_t cnt) {
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s->skiped += s->rcvd > 2 ? cnt : 0;
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}
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#else // STATS_DISABLED
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#define StatsIncSent(x)
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#endif // STATS_DISABLED
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#endif /* STATS_H_ */
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@ -40,7 +40,7 @@ void HandleConsoleUsartIrq(USART_TypeDef *usart)
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b += strcpy_ex(b,s); \
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b += uitodec(b,u);
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void PrintStats(char *buffer, uint8_t id, STATS *stats, USART_TypeDef *usart, DMAINFO *dmaInfo)
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void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo)
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{
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char ids[] = " : ";
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char *bs = buffer;
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@ -14,6 +14,6 @@
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void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart);
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void HandleConsoleUsartIrq(USART_TypeDef *usart);
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void PrintStats(char *buffer, uint8_t id, STATS *stats, USART_TypeDef *usart, DMAINFO *dmaInfo);
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void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo);
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#endif /* INTERRUPT_HANDLERS_H_ */
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@ -4,9 +4,8 @@
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* Created on: Aug 29, 2019
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* Author: abody
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*/
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#include <dma.h>
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#include <string.h>
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#include "crc.h"
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#include <platform/crc_ll.h>
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#include "dma_helper.h"
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#include "diag.h"
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#include "crc_handler.h"
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@ -28,7 +27,7 @@
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#endif
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void InitCrcStatus(struct crcstatus_t *st, DMA_TypeDef *dma, uint32_t stream)
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void InitCrcStatus(CRCSTATUS *st, DMA_TypeDef *dma, uint32_t stream)
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{
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InitDmaInfo(&st->dmaInfo, dma, stream);
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LL_DMA_EnableIT_TC(dma, stream);
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@ -38,7 +37,7 @@ void InitCrcStatus(struct crcstatus_t *st, DMA_TypeDef *dma, uint32_t stream)
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memset((void*)st->crcTasks, 0, sizeof(st->crcTasks));
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}
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uint8_t EnqueueCrcTask(struct crcstatus_t *status, uint8_t slot, uint8_t *address, uint16_t len,
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uint8_t EnqueueCrcTask(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len,
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void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
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{
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uint32_t prim = __get_PRIMASK();
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@ -65,13 +64,13 @@ uint8_t EnqueueCrcTask(struct crcstatus_t *status, uint8_t slot, uint8_t *addres
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return need_start;
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}
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void WaitCrcResults(struct crcstatus_t *status, uint8_t slot)
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void WaitCrcResults(CRCSTATUS *status, uint8_t slot)
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{
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while(IsSlotQueued(status, slot));
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while(GetActiveSlot(status) == slot);
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}
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uint32_t ComputeCrc(struct crcstatus_t *status, uint8_t slot, uint8_t *address, uint16_t len)
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uint32_t ComputeCrc(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len)
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{
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uint32_t result;
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EnqueueCrcTask(status, slot, address, len, NULL, &result);
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@ -79,7 +78,7 @@ uint32_t ComputeCrc(struct crcstatus_t *status, uint8_t slot, uint8_t *address,
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return result;
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}
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void StartNextCrcTask(struct crcstatus_t *status)
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void StartNextCrcTask(CRCSTATUS *status)
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{
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uint16_t slot;
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for(slot = 0; slot < CRCTASKCOUNT; ++slot)
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status->activeSlot = 0xff;
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}
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void HandleCrcDmaIrq(struct crcstatus_t *status)
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void HandleCrcDmaIrq(CRCSTATUS *status)
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{
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DIAG_INTERRUPT_IN();
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if(*status->dmaInfo.isReg & status->dmaInfo.tcMask) { // DMA transfer complete
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@ -9,14 +9,18 @@
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#define CRC_HANDLER_H_
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#include <inttypes.h>
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#include <dma_helper.h>
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#ifdef HAVE_CONFIG
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#include "config.h"
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#endif // HAVE_CONFIG
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#include <dma_helper.h>
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#ifndef CRCTASKCOUNT
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#define CRCTASKCOUNT 8
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#define CRCTASKCOUNT 2
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#endif
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struct crcstatus_t {
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typedef struct {
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DMAINFO dmaInfo;
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volatile uint8_t activeSlot;
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struct crctask_t {
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void (*callback)(void*, uint32_t, uint8_t);
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void *callbackParam;
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} volatile crcTasks[CRCTASKCOUNT];
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};
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} CRCSTATUS;
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//#define CRCTASKCOUNT (sizeof(((struct crcstatus_t*)0)->crcTasks)/sizeof(struct crctask_t))
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void InitCrcStatus(struct crcstatus_t *status, DMA_TypeDef *dma, uint32_t stream);
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static inline uint8_t GetActiveSlot(struct crcstatus_t *status) {
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void InitCrcStatus(CRCSTATUS *status, DMA_TypeDef *dma, uint32_t stream);
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static inline uint8_t GetActiveSlot(CRCSTATUS *status) {
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return status->activeSlot;
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}
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static inline uint8_t IsSlotQueued(struct crcstatus_t *status, uint8_t slot) {
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static inline uint8_t IsSlotQueued(CRCSTATUS *status, uint8_t slot) {
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return status->crcTasks[slot].address != NULL;
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}
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static inline uint8_t IsSlotActive(struct crcstatus_t *status, uint8_t slot) {
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static inline uint8_t IsSlotActive(CRCSTATUS *status, uint8_t slot) {
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return status->crcTasks[slot].callback != NULL || status->crcTasks[slot].callbackParam != NULL;
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}
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uint8_t EnqueueCrcTask(struct crcstatus_t *crcStatus, uint8_t slot, uint8_t *address, uint16_t len,
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uint8_t EnqueueCrcTask(CRCSTATUS *crcStatus, uint8_t slot, uint8_t *address, uint16_t len,
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void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
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void WaitCrcResults(struct crcstatus_t *status, uint8_t slot);
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uint32_t ComputeCrc(struct crcstatus_t *status, uint8_t slot, uint8_t *address, uint16_t len);
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void ComputeCrcAsync(struct crcstatus_t *status, uint8_t slot,
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void WaitCrcResults(CRCSTATUS *status, uint8_t slot);
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uint32_t ComputeCrc(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len);
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void ComputeCrcAsync(CRCSTATUS *status, uint8_t slot,
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uint8_t *address, uint16_t len,
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void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
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void HandleCrcDmaIrq(struct crcstatus_t *status);
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void HandleCrcDmaIrq(CRCSTATUS *status);
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#endif /* CRC_HANDLER_H_ */
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#ifndef DMA_HELPER_H_
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#define DMA_HELPER_H_
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#include <inttypes.h>
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#include "dma.h"
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#include <platform/dma_ll.h>
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typedef struct {
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DMA_TypeDef *dma;
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@ -31,7 +31,6 @@ void * MemcpyDma(void *dst, void const *src, size_t length)
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LL_DMA_SetM2MDstAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)dst);
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LL_DMA_SetDataLength(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (length+3)/4 );
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g_memcpyDmaBusy = 1;
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//DIAG_CRC_CALC_START();
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LL_DMA_EnableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
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while(g_memcpyDmaBusy);
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return dst;
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#define MEMCPY_DMA_H_
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#include <inttypes.h>
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#include "dma.h"
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//#include "dma_helper.h"
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//extern DMAINFO g_memcpyDmaInfo;
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#include <platform/dma_ll.h>
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void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream);
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void * MemcpyDma(void *dst, void const *src, size_t length);
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/*
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* uart_handler.c
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* usart_handler.c
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*
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* Created on: Sep 16, 2019
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* Author: abody
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*/
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#include <string.h>
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#include "globals.h"
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#include <platform/usart_ll.h>
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#include "diag.h"
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#include "usart_handler.h"
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#include "dma_helper.h"
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# define DIAG_INTERRUPT_OUT()
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#endif
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#define STARTMARKER 0x95
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static inline uint32_t RoundUpTo4(uint32_t inp)
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{
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return (inp + 3) & 0xfffc;
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}
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void InitUartStatus(
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UARTSTATUS *st, USART_TypeDef *uart, DMA_TypeDef *dma,
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USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
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uint32_t stream_rx, uint32_t stream_tx,
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struct crcstatus_t *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot)
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CRCSTATUS *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot,
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PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
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{
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st->uart = uart;
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st->usart = usart;
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InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
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InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
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st->txBuffer.busy = 0;
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st->rxBuffers[1].error = 0;
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st->rxBuffers[0].requestedLength = 0;
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st->rxBuffers[1].requestedLength = 0;
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st->txBuffer.usartStatus = st;
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st->rxBuffers[0].usartStatus = st;
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st->rxBuffers[1].usartStatus = st;
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st->packetReceivedCallback = packetReceivedCallback;
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st->packetReceivedCallbacParam = packetReceivedCallbackParam;
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st->rxSerial = -1;
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st->txSerial = 0;
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st->activeRxBuf = 0;
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LL_DMA_EnableIT_TE(dma, stream_rx);
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LL_DMA_EnableIT_TC(dma, stream_tx);
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LL_DMA_EnableIT_TE(dma, stream_tx);
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LL_USART_EnableIT_IDLE(uart);
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LL_USART_EnableIT_IDLE(usart);
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}
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static inline void BuildHeader(UARTBUFFER *buffer, uint8_t serial, uint8_t length)
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uint8_t* GetTxBuffer(USARTSTATUS *status)
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{
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return status->txBuffer.packet.payload;
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}
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static inline void BuildHeader(struct usart_buffer *buffer, uint8_t serial, uint8_t length)
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{
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uint8_t hash = STARTMARKER;
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buffer->packet.header.startByte = STARTMARKER;
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@ -67,51 +86,61 @@ static inline void BuildHeader(UARTBUFFER *buffer, uint8_t serial, uint8_t lengt
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buffer->packet.header.hash = hash;
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}
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static inline uint8_t CheckHeader(UARTPACKET *packet) {
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static inline uint8_t CheckHeader(USARTPACKET *packet) {
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return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
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}
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|
||||
uint8_t PostPacket(UARTSTATUS *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus)
|
||||
uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, CRCSTATUS *crcStatus)
|
||||
{
|
||||
if(length > 256)
|
||||
return 1;
|
||||
|
||||
BuildHeader(&status->txBuffer, status->txSerial++, length);
|
||||
uint16_t payloadLength = (length+3) & 0xfffc; // round up to 4
|
||||
if(payload)
|
||||
uint16_t payloadLength = RoundUpTo4(length);
|
||||
if(payload) {
|
||||
#ifdef USART_USE_MEMCPY_DMA
|
||||
if((uint32_t)payload & 3)
|
||||
memcpy(status->txBuffer.packet.payload, payload, length);
|
||||
else
|
||||
MemcpyDma(status->txBuffer.packet.payload, payload, length);
|
||||
status->txBuffer.requestedLength = sizeof(UARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
|
||||
#else
|
||||
memcpy(status->txBuffer.packet.payload, payload, length);
|
||||
#endif
|
||||
}
|
||||
status->txBuffer.requestedLength = sizeof(USARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
|
||||
status->txBuffer.busy = 1;
|
||||
status->txBuffer.error = 0;
|
||||
EnqueueCrcTask(crcStatus, status->txCrcSlot, status->txBuffer.packet.payload, length,
|
||||
NULL, (uint32_t*)(status->txBuffer.packet.payload + payloadLength));
|
||||
while(IsSlotQueued(crcStatus, status->txCrcSlot));
|
||||
SetupTransmit(status->uart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
|
||||
SetupTransmit(status->usart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
|
||||
|
||||
StatsIncSent(&status->stats);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void SetupReceive(UARTSTATUS *status)
|
||||
|
||||
void SetupReceive(USARTSTATUS *status)
|
||||
{
|
||||
uint8_t packetIndex = status->activeRxBuf;
|
||||
|
||||
LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->uart), (uint32_t)&status->rxBuffers[packetIndex],
|
||||
LL_DMA_GetDataTransferDirection(status->rxDmaInfo.dma, status->rxDmaInfo.stream));
|
||||
LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->usart), (uint32_t)&status->rxBuffers[packetIndex],
|
||||
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
||||
status->rxBuffers[packetIndex].requestedLength = sizeof(status->rxBuffers[packetIndex].packet);
|
||||
LL_DMA_SetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream, status->rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
|
||||
LL_USART_EnableDMAReq_RX(status->uart);
|
||||
LL_USART_ClearFlag_ORE(status->uart);
|
||||
LL_USART_EnableDMAReq_RX(status->usart);
|
||||
LL_USART_ClearFlag_ORE(status->usart);
|
||||
LL_DMA_EnableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
}
|
||||
|
||||
void ConsumePacket(UARTSTATUS *status, uint8_t packetIndex, struct crcstatus_t *crcStatus)
|
||||
|
||||
void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex, CRCSTATUS *crcStatus)
|
||||
{
|
||||
UARTBUFFER *buffer = &status->rxBuffers[packetIndex];
|
||||
struct usart_buffer *buffer = &status->rxBuffers[packetIndex];
|
||||
if(buffer->busy) {
|
||||
if(buffer->error)
|
||||
StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + ((buffer->packet.header.payloadLength + 1 + 3) & 0xfffc)));
|
||||
StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + RoundUpTo4(buffer->packet.header.payloadLength + 1)));
|
||||
else {
|
||||
uint8_t diff = buffer->packet.header.serial - status->rxSerial;
|
||||
if(diff > 1)
|
||||
|
@ -123,28 +152,31 @@ void ConsumePacket(UARTSTATUS *status, uint8_t packetIndex, struct crcstatus_t *
|
|||
buffer->busy = buffer->error = 0;
|
||||
}
|
||||
|
||||
void SetupTransmit(USART_TypeDef *uart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
|
||||
|
||||
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(uart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_SetDataLength(dma, stream, length);
|
||||
LL_USART_EnableDMAReq_TX(uart);
|
||||
LL_USART_EnableDMAReq_TX(usart);
|
||||
LL_DMA_EnableStream(dma, stream);
|
||||
}
|
||||
|
||||
void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
|
||||
{
|
||||
UARTBUFFER *ub = (UARTBUFFER*) callbackParm;
|
||||
struct usart_buffer *ub = (struct usart_buffer*) callbackParm;
|
||||
if(!success)
|
||||
ub->error = 1;
|
||||
else if(*(uint32_t*) (ub->packet.payload + ((ub->packet.header.payloadLength + 1 + 3) & 0xfffc)) == calculatedCrc)
|
||||
else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength + 1)))
|
||||
ub->busy = 1;
|
||||
else {
|
||||
ub->error = ub->busy = 1;
|
||||
ub->errorInfo = calculatedCrc;
|
||||
}
|
||||
if(ub->usartStatus->packetReceivedCallback)
|
||||
ub->usartStatus->packetReceivedCallback(ub->usartStatus->packetReceivedCallbacParam, ub);
|
||||
}
|
||||
|
||||
void HandleUsartRxDmaIrq(UARTSTATUS *status)
|
||||
void HandleUsartRxDmaIrq(USARTSTATUS *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
StatsIncRcvd(&status->stats);
|
||||
|
@ -173,12 +205,12 @@ void HandleUsartRxDmaIrq(UARTSTATUS *status)
|
|||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleUsartTxDmaIrq(UARTSTATUS *status)
|
||||
void HandleUsartTxDmaIrq(USARTSTATUS *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
|
||||
LL_USART_EnableIT_TC(status->uart);
|
||||
LL_USART_EnableIT_TC(status->usart);
|
||||
LL_DMA_DisableStream(status->txDmaInfo.dma, status->txDmaInfo.stream);
|
||||
}
|
||||
else if(*status->txDmaInfo.isReg & status->txDmaInfo.teMask) {
|
||||
|
@ -195,15 +227,15 @@ void HandleUsartTxDmaIrq(UARTSTATUS *status)
|
|||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleUsartIrq(UARTSTATUS *status)
|
||||
void HandleUsartIrq(USARTSTATUS *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(LL_USART_IsActiveFlag_IDLE(status->uart) && LL_USART_IsEnabledIT_IDLE(status->uart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(status->uart);
|
||||
if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(status->usart);
|
||||
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
if(rcvdLen >= sizeof(UARTPACKETHEADER)) {
|
||||
if(rcvdLen >= sizeof(USARTPACKETHEADER)) {
|
||||
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
|
||||
if(rcvdLen >= sizeof(UARTPACKETHEADER) + ((status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1 + 3) &0xfffc) + sizeof(uint32_t))
|
||||
if(rcvdLen >= sizeof(USARTPACKETHEADER) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
|
||||
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
else
|
||||
StatsIncPremature_payload(&status->stats);
|
||||
|
@ -214,10 +246,10 @@ void HandleUsartIrq(UARTSTATUS *status)
|
|||
} else
|
||||
StatsIncPremature_hdr(&status->stats);
|
||||
}
|
||||
else if(LL_USART_IsActiveFlag_TC(status->uart) && LL_USART_IsEnabledIT_TC(status->uart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(status->uart);
|
||||
LL_USART_DisableDirectionTx(status->uart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(status->uart);
|
||||
else if(LL_USART_IsActiveFlag_TC(status->usart) && LL_USART_IsEnabledIT_TC(status->usart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(status->usart);
|
||||
LL_USART_DisableDirectionTx(status->usart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(status->usart);
|
||||
status->txBuffer.busy = 0;
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
|
|
|
@ -1,81 +1,142 @@
|
|||
/*
|
||||
* uart_handler.h
|
||||
* usart_handler.h
|
||||
*
|
||||
* Created on: Sep 16, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef UART_HANDLER_H_
|
||||
#define UART_HANDLER_H_
|
||||
#ifndef USART_HANDLER_H_
|
||||
#define USART_HANDLER_H_
|
||||
#include <inttypes.h>
|
||||
#include <dma.h>
|
||||
#include <stats.h>
|
||||
|
||||
#include "dma_helper.h"
|
||||
#include "crc_handler.h"
|
||||
|
||||
/*
|
||||
* TH UART RXDMA TXDMA
|
||||
* 0 1 D2S5 D2S7
|
||||
* 1 3 D1S1 D1S3
|
||||
* 2 2 D1S5 D1S6
|
||||
* 3 6 D2S2 D2S6
|
||||
struct _usart_status;
|
||||
typedef struct _usart_status USARTSTATUS;
|
||||
struct usart_buffer;
|
||||
|
||||
typedef void (*PACKETRECEIVEDCALLBACK)(void *userParam, struct usart_buffer *buffer);
|
||||
|
||||
void InitUartStatus(
|
||||
USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
|
||||
uint32_t stream_rx, uint32_t stream_tx,
|
||||
CRCSTATUS *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot,
|
||||
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam);
|
||||
|
||||
uint8_t* GetTxBuffer(USARTSTATUS *status);
|
||||
|
||||
uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, CRCSTATUS *crcStatus);
|
||||
void SetupReceive(USARTSTATUS *status);
|
||||
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length);
|
||||
void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex, CRCSTATUS *crcStatus);
|
||||
|
||||
void HandleUsartRxDmaIrq(USARTSTATUS *status);
|
||||
void HandleUsartTxDmaIrq(USARTSTATUS *status);
|
||||
void HandleUsartIrq(USARTSTATUS *status);
|
||||
|
||||
/******************************************************************************************
|
||||
*
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
struct usart_stats {
|
||||
uint32_t overrun;
|
||||
uint32_t hdrError;
|
||||
uint32_t lastErrHdr;
|
||||
uint32_t payloadErrror;
|
||||
uint32_t pep1, pep2;
|
||||
uint32_t dmaError;
|
||||
uint32_t rcvd;
|
||||
uint32_t premature_hdr;
|
||||
uint32_t premature_payload;
|
||||
uint32_t sent;
|
||||
uint32_t skiped;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
uint8_t startByte;
|
||||
uint8_t serial;
|
||||
uint8_t payloadLength;
|
||||
uint8_t hash;
|
||||
} UARTPACKETHEADER;
|
||||
} USARTPACKETHEADER;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UARTPACKETHEADER header;
|
||||
typedef struct {
|
||||
USARTPACKETHEADER header;
|
||||
//!!! should start on word offset !!!
|
||||
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
|
||||
} __attribute__((aligned)) UARTPACKET;
|
||||
} __attribute__((aligned)) USARTPACKET;
|
||||
|
||||
typedef struct _UARTBUFFER {
|
||||
UARTPACKET packet;
|
||||
struct usart_buffer {
|
||||
USARTPACKET packet;
|
||||
//transfer area ends here
|
||||
volatile uint8_t busy;
|
||||
volatile uint8_t error;
|
||||
uint16_t requestedLength;
|
||||
uint32_t errorInfo;
|
||||
} UARTBUFFER;
|
||||
USARTSTATUS *usartStatus;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
USART_TypeDef *uart;
|
||||
struct _usart_status {
|
||||
USART_TypeDef *usart;
|
||||
DMAINFO rxDmaInfo;
|
||||
DMAINFO txDmaInfo;
|
||||
struct crcstatus_t *crcStatus;
|
||||
CRCSTATUS *crcStatus;
|
||||
uint8_t rxSerial;
|
||||
uint8_t txSerial;
|
||||
STATS stats;
|
||||
struct usart_stats stats;
|
||||
uint8_t activeRxBuf;
|
||||
uint8_t rxCrcSlot;
|
||||
uint8_t txCrcSlot;
|
||||
UARTBUFFER txBuffer;
|
||||
UARTBUFFER rxBuffers[2];
|
||||
} UARTSTATUS;
|
||||
PACKETRECEIVEDCALLBACK packetReceivedCallback;
|
||||
void *packetReceivedCallbacParam;
|
||||
struct usart_buffer txBuffer;
|
||||
struct usart_buffer rxBuffers[2];
|
||||
};
|
||||
|
||||
#define STARTMARKER 0x95
|
||||
|
||||
void InitUartStatus(
|
||||
UARTSTATUS *st, USART_TypeDef *uart, DMA_TypeDef *dma,
|
||||
uint32_t stream_rx, uint32_t stream_tx,
|
||||
struct crcstatus_t *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot);
|
||||
static inline uint8_t* GetTxBuffer(UARTSTATUS *status) {
|
||||
return status->txBuffer.packet.payload;
|
||||
#ifndef USART_STATS_DISABLED
|
||||
static inline void StatsIncOverrun(struct usart_stats *s) {
|
||||
++s->overrun;
|
||||
}
|
||||
static inline void StatsIncHdrError(struct usart_stats *s, uint32_t hdr) {
|
||||
++s->hdrError;
|
||||
s->lastErrHdr = hdr;
|
||||
}
|
||||
static inline void StatsIncPayloadError(struct usart_stats *s, uint32_t pep1, uint32_t pep2) {
|
||||
++s->payloadErrror;
|
||||
s->pep1 = pep1;
|
||||
s->pep2 = pep2;
|
||||
}
|
||||
static inline void StatsIncDmaError(struct usart_stats *s) {
|
||||
++s->dmaError;
|
||||
}
|
||||
static inline void StatsIncRcvd(struct usart_stats *s) {
|
||||
++s->rcvd;
|
||||
}
|
||||
static inline void StatsIncPremature_hdr(struct usart_stats *s) {
|
||||
++s->premature_hdr;
|
||||
}
|
||||
static inline void StatsIncPremature_payload(struct usart_stats *s) {
|
||||
++s->premature_payload;
|
||||
}
|
||||
static inline void StatsIncSent(struct usart_stats *s) {
|
||||
++s->sent;
|
||||
}
|
||||
static inline void StatsAddSkiped(struct usart_stats *s, uint8_t cnt) {
|
||||
s->skiped += s->rcvd > 2 ? cnt : 0;
|
||||
}
|
||||
uint8_t PostPacket(UARTSTATUS *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus);
|
||||
void SetupReceive(UARTSTATUS *status);
|
||||
void SetupTransmit(USART_TypeDef *uart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length);
|
||||
void ConsumePacket(UARTSTATUS *status, uint8_t packetIndex, struct crcstatus_t *crcStatus);
|
||||
|
||||
void HandleUsartRxDmaIrq(UARTSTATUS *status);
|
||||
void HandleUsartTxDmaIrq(UARTSTATUS *status);
|
||||
void HandleUsartIrq(UARTSTATUS *status);
|
||||
#else // USART_STATS_DISABLED
|
||||
#define StatsIncOverrun(x)
|
||||
#define StatsIncHdrError(x,y)
|
||||
#define StatsIncPayloadError(x,y,z)
|
||||
#define StatsIncDmaError(x)
|
||||
#define StatsIncRcvd(x)
|
||||
#define StatsIncPremature_hdr(x)
|
||||
#define StatsIncPremature_payload(x)
|
||||
#define StatsIncSent(x)
|
||||
#define StatsAddSkiped(x)
|
||||
#endif // USART_STATS_DISABLED
|
||||
|
||||
#endif /* UART_HANDLER_H_ */
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue