cleaning up
This commit is contained in:
parent
491062cac6
commit
c439c48643
9 changed files with 63 additions and 100 deletions
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@ -158,6 +158,7 @@
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<listOptionValue builtIn="false" value="DEBUG"/>
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<listOptionValue builtIn="false" value="STM32F407xx"/>
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<listOptionValue builtIn="false" value="HAVE_CONFIG"/>
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<listOptionValue builtIn="false" value="ENABLE_DIAG"/>
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</option>
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.941145715" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
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<listOptionValue builtIn="false" value="../Inc"/>
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@ -191,6 +192,7 @@
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<listOptionValue builtIn="false" value="DEBUG"/>
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<listOptionValue builtIn="false" value="STM32F407xx"/>
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<listOptionValue builtIn="false" value="HAVE_CONFIG"/>
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<listOptionValue builtIn="false" value="ENABLE_DIAG"/>
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</option>
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<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.687772733" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp"/>
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</tool>
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16
App/diag.h
16
App/diag.h
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@ -8,7 +8,7 @@
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#ifndef DIAG_H_
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#define DIAG_H_
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#ifdef _ENABLE_DIAG
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#ifdef ENABLE_DIAG
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#define DIAG_RX_BUFFER_SWITCH(x) \
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if(x) { \
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LL_GPIO_SetOutputPin(LED0_GPIO_Port, LED0_Pin); \
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@ -18,13 +18,13 @@ if(x) { \
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LL_GPIO_SetOutputPin(LED1_GPIO_Port, LED1_Pin); \
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}
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#define DIAG_INTERRUPT_IN() LL_GPIO_SetOutputPin(DEBUG0_GPIO_Port, DEBUG0_Pin)
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#define DIAG_INTERRUPT_OUT() LL_GPIO_ResetOutputPin(DEBUG0_GPIO_Port, DEBUG0_Pin)
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#define DIAG_CRC_CALC_START() LL_GPIO_SetOutputPin(DEBUG1_GPIO_Port, DEBUG1_Pin)
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#define DIAG_CRC_CALC_END() LL_GPIO_ResetOutputPin(DEBUG1_GPIO_Port, DEBUG1_Pin)
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//#define DIAG_ERROR_EVENT() LL_GPIO_TogglePin(DEBUG2_GPIO_Port, DEBUG2_Pin)
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#define DIAG_ENTER_BUSY() LL_GPIO_SetOutputPin(DEBUG2_GPIO_Port, DEBUG2_Pin)
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#define DIAG_EXIT_BUSY() LL_GPIO_ResetOutputPin(DEBUG2_GPIO_Port, DEBUG2_Pin)
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#define DIAG_INTERRUPT_IN() LL_GPIO_SetOutputPin(DBG0_GPIO_Port, DBG0_Pin)
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#define DIAG_INTERRUPT_OUT() LL_GPIO_ResetOutputPin(DBG0_GPIO_Port, DBG0_Pin)
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#define DIAG_CRC_CALC_START() LL_GPIO_SetOutputPin(DBG1_GPIO_Port, DBG1_Pin)
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#define DIAG_CRC_CALC_END() LL_GPIO_ResetOutputPin(DBG1_GPIO_Port, DBG1_Pin)
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//#define DIAG_ERROR_EVENT() LL_GPIO_TogglePin(DBG2_GPIO_Port, DBG2_Pin)
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#define DIAG_ENTER_BUSY() LL_GPIO_SetOutputPin(DBG2_GPIO_Port, DBG2_Pin)
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#define DIAG_EXIT_BUSY() LL_GPIO_ResetOutputPin(DBG2_GPIO_Port, DBG2_Pin)
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#endif // _ENABLE_DIAG
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@ -7,7 +7,7 @@
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#include "globals.h"
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USARTSTATUS g_uartStatuses[USARTCOUNT];
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struct usartstatus_t g_uartStatuses[USARTCOUNT];
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struct crcstatus_t g_crcStatus;
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@ -14,7 +14,7 @@
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#include "f4ll_c/dma_helper.h"
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#include "f4ll_c/crc_handler.h"
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extern USARTSTATUS g_uartStatuses[USARTCOUNT];
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extern struct usartstatus_t g_uartStatuses[USARTCOUNT];
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extern struct crcstatus_t g_crcStatus;
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10
Src/dma.c
10
Src/dma.c
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@ -138,9 +138,6 @@ void MX_DMA_Init(void)
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/* DMA1_Stream6_IRQn interrupt configuration */
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NVIC_SetPriority(DMA1_Stream6_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA1_Stream6_IRQn);
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/* DMA2_Stream0_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA2_Stream0_IRQn);
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/* DMA2_Stream1_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA2_Stream1_IRQn);
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@ -153,14 +150,11 @@ void MX_DMA_Init(void)
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/* DMA2_Stream4_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
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NVIC_EnableIRQ(DMA2_Stream4_IRQn);
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/* DMA2_Stream5_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
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NVIC_EnableIRQ(DMA2_Stream5_IRQn);
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/* DMA2_Stream6_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream6_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
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NVIC_SetPriority(DMA2_Stream6_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA2_Stream6_IRQn);
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/* DMA2_Stream7_IRQn interrupt configuration */
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NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
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NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(DMA2_Stream7_IRQn);
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}
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@ -16,15 +16,11 @@
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#include "f4ll_c/dma_helper.h"
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#ifndef CRCTASKCOUNT
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#define CRCTASKCOUNT 2
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#endif
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struct crcslottask_t {
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void * volatile address;
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uint16_t wordCount;
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void (* volatile callback)(void*, uint32_t, uint8_t);
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void * volatile callbackParam;
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void (*callback)(void*, uint32_t, uint8_t);
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void *callbackParam;
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};
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struct crcslotlistitem_t {
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@ -35,21 +31,20 @@ struct crcslotlistitem_t {
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struct crcstatus_t {
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DMAINFO dmaInfo;
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struct crcslotlistitem_t * volatile activeSlot;
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uint8_t volatile activeTask;
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struct crcslotlistitem_t *activeSlot;
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uint8_t activeTask;
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struct crcslotlistitem_t *first;
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};
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void InitCrcStatus(struct crcstatus_t *status, DMA_TypeDef *dma, uint32_t stream);
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uint8_t GetActiveSlot(struct crcslotlistitem_t **slot_out, struct crcstatus_t *status);
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uint8_t GetActiveTask(struct crcslotlistitem_t **slot_out, struct crcstatus_t volatile *status);
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static inline uint8_t IsSlotQueued(struct crcslotlistitem_t *slot, uint8_t task) {
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static inline uint8_t IsSlotQueued(struct crcslotlistitem_t volatile *slot, uint8_t task) {
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return slot->tasks[task].address != NULL;
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}
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static inline uint8_t IsSlotActive(struct crcslotlistitem_t *slot, uint8_t task) {
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static inline uint8_t IsSlotActive(struct crcslotlistitem_t volatile *slot, uint8_t task) {
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return slot->tasks[task].callback != NULL || slot->tasks[task].callbackParam != NULL;
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}
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@ -12,28 +12,27 @@
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#include "f4ll_c/dma_helper.h"
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#include "f4ll_c/crc_handler.h"
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struct _usart_status;
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typedef struct _usart_status USARTSTATUS;
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struct usart_buffer;
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struct usartstatus_t;
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typedef void (*PACKETRECEIVEDCALLBACK)(void *userParam, struct usart_buffer *buffer);
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void InitUartStatus(
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USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
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struct usartstatus_t *st, USART_TypeDef *usart, DMA_TypeDef *dma,
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uint32_t stream_rx, uint32_t stream_tx,
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struct crcstatus_t *crcStatus,
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PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam);
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uint8_t* GetTxBuffer(USARTSTATUS *status);
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uint8_t* GetTxBuffer(struct usartstatus_t *status);
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uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue);
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void SetupReceive(USARTSTATUS *status);
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uint8_t PostPacket(struct usartstatus_t *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue);
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void SetupReceive(struct usartstatus_t *status);
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void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length);
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void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex);
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void ConsumePacket(struct usartstatus_t *status, uint8_t packetIndex);
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void HandleUsartRxDmaIrq(USARTSTATUS *status);
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void HandleUsartTxDmaIrq(USARTSTATUS *status);
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void HandleUsartIrq(USARTSTATUS *status);
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void HandleUsartRxDmaIrq(struct usartstatus_t *status);
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void HandleUsartTxDmaIrq(struct usartstatus_t *status);
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void HandleUsartIrq(struct usartstatus_t *status);
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/******************************************************************************************
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*
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@ -55,30 +54,30 @@ struct usart_stats {
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uint32_t skiped;
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};
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typedef struct {
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struct usartpacketheader_t {
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uint8_t startByte;
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uint8_t serial;
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uint8_t payloadLength;
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uint8_t hash;
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} USARTPACKETHEADER;
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};
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typedef struct {
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USARTPACKETHEADER header;
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struct usartpacket_t {
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struct usartpacketheader_t header;
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//!!! should start on word offset !!!
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uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
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} __attribute__((aligned)) USARTPACKET;
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} __attribute__((aligned));
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struct usart_buffer {
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USARTPACKET packet;
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struct usartpacket_t packet;
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//transfer area ends here
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volatile uint8_t busy;
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volatile uint8_t error;
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uint16_t requestedLength;
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uint32_t errorInfo;
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USARTSTATUS *usartStatus;
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struct usartstatus_t *usartStatus;
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};
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struct _usart_status {
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struct usartstatus_t {
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USART_TypeDef *usart;
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DMAINFO rxDmaInfo;
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DMAINFO txDmaInfo;
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@ -27,18 +27,6 @@
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# define DIAG_INTERRUPT_OUT()
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#endif
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#define SLOTHITORYSIZE 8192
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typedef struct crcstatus_t * CRCSTATUSPTR;
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typedef struct crcslotlistitem_t * CRCSLOTPTR;
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CRCSLOTPTR slot0History[SLOTHITORYSIZE];
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CRCSLOTPTR slot1History[SLOTHITORYSIZE];
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CRCSLOTPTR *slotHistoryPtrs[2] = { slot0History, slot1History };
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uint32_t slotIndexes[2] = {0, 0};
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uint32_t volatile spuriousCount = 0;
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void InitCrcStatus(struct crcstatus_t *st, DMA_TypeDef *dma, uint32_t stream)
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{
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InitDmaInfo(&st->dmaInfo, dma, stream);
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@ -62,7 +50,7 @@ void AttachCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slot, s
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__set_PRIMASK(prim);
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}
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uint8_t GetActiveSlot(struct crcslotlistitem_t **slot_out, struct crcstatus_t *status)
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uint8_t GetActiveTask(struct crcslotlistitem_t **slot_out, struct crcstatus_t volatile *status)
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{
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uint8_t ret;
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@ -82,12 +70,11 @@ uint8_t EnqueueCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slo
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{
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uint32_t prim = __get_PRIMASK();
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uint16_t need_start;
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struct crcstatus_t volatile *st = status;
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LL_GPIO_SetOutputPin(DBG0_GPIO_Port, task ? DBG1_Pin : DBG0_Pin);
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while(status->activeSlot == slot && status->activeTask == task);
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while(st->activeSlot == slot && st->activeTask == task);
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__disable_irq();
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need_start = (status->activeSlot == NULL);
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need_start = (st->activeSlot == NULL);
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slot->tasks[task].address = need_start ? NULL : address;
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slot->tasks[task].wordCount = (len+3)/4;
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slot->tasks[task].callback = callback;
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@ -105,7 +92,6 @@ uint8_t EnqueueCrcTask(struct crcstatus_t *status, struct crcslotlistitem_t *slo
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DIAG_CRC_CALC_START();
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LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
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}
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LL_GPIO_ResetOutputPin(DBG0_GPIO_Port, task ? DBG1_Pin : DBG0_Pin);
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return need_start;
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}
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@ -114,7 +100,7 @@ void WaitCrcResults(struct crcstatus_t *status, struct crcslotlistitem_t *slot,
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struct crcslotlistitem_t *slotQueued;
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while(IsSlotQueued(slot, task));
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while(GetActiveSlot(&slotQueued, status) == task && slotQueued == slot);
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while(GetActiveTask(&slotQueued, status) == task && slotQueued == slot);
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}
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@ -122,19 +108,19 @@ uint32_t ComputeCrc(struct crcstatus_t *status, struct crcslotlistitem_t *slot,
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{
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uint32_t result;
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EnqueueCrcTask(status, slot, task, address, len, NULL, &result);
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while(slot->tasks[task].callbackParam);
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while((struct crcslotlistitem_t volatile *)slot->tasks[task].callbackParam);
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return result;
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}
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// only called from ISR context
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static void StartNextCrcTask(struct crcstatus_t *status)
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{
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int stillMore;
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char moreTasks;
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uint8_t index = 0;
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do {
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struct crcslotlistitem_t *slot = status->first;
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stillMore = 0;
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moreTasks = 0;
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while(slot) {
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if(index < slot->count) {
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if(slot->tasks[index].address) {
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@ -148,28 +134,22 @@ static void StartNextCrcTask(struct crcstatus_t *status)
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return;
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}
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if(index + 1 < slot->count)
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stillMore = 1;
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moreTasks = 1;
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}
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slot = slot->next;
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}
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++index;
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} while(stillMore);
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} while(moreTasks);
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status->activeSlot = NULL;
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}
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void HandleCrcDmaIrq(struct crcstatus_t *status)
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{
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LL_GPIO_SetOutputPin(DBG0_GPIO_Port, DBG2_Pin);
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DIAG_INTERRUPT_IN();
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if(*status->dmaInfo.isReg & status->dmaInfo.tcMask) { // DMA transfer complete
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*status->dmaInfo.ifcReg = status->dmaInfo.tcMask;
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LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
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if(status->activeSlot) {
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// (slotHistoryPtrs[status->activeTask][slotIndexes[status->activeTask]++]) = status->activeSlot;
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// while(slotIndexes[status->activeTask] >= SLOTHITORYSIZE);
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struct crcslottask_t *tsk = &status->activeSlot->tasks[status->activeTask];
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if(tsk->callback)
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tsk->callback(tsk->callbackParam, CRC->DR, 1);
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@ -194,13 +174,6 @@ void HandleCrcDmaIrq(struct crcstatus_t *status)
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StartNextCrcTask(status);
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}
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}
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else
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{
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++spuriousCount;
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}
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DIAG_INTERRUPT_OUT();
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LL_GPIO_ResetOutputPin(DBG0_GPIO_Port, DBG2_Pin);
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}
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@ -31,7 +31,7 @@ static inline uint32_t RoundUpTo4(uint32_t inp)
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}
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void InitUartStatus(
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USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
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struct usartstatus_t *st, USART_TypeDef *usart, DMA_TypeDef *dma,
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uint32_t stream_rx, uint32_t stream_tx,
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struct crcstatus_t *crcStatus,
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PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
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@ -80,7 +80,7 @@ void InitUartStatus(
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}
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uint8_t* GetTxBuffer(USARTSTATUS *status)
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uint8_t* GetTxBuffer(struct usartstatus_t *status)
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{
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return status->txBuffer.packet.payload;
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}
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@ -97,13 +97,13 @@ static inline void BuildHeader(struct usart_buffer *buffer, uint8_t serial, uint
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buffer->packet.header.hash = hash;
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}
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static inline uint8_t CheckHeader(USARTPACKET *packet)
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static inline uint8_t CheckHeader(struct usartpacket_t *packet)
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{
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return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
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}
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uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue)
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uint8_t PostPacket(struct usartstatus_t *status, uint8_t const *payload, uint16_t length, struct crcstatus_t *crcStatus, uint8_t waitForCrcQueue)
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{
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// static uint32_t count = 0;
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// ITM->PORT[1].u32 = count++;
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@ -116,7 +116,7 @@ uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length,
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uint16_t payloadLength = RoundUpTo4(length);
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if(payload)
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||||
memcpy(status->txBuffer.packet.payload, payload, length);
|
||||
status->txBuffer.requestedLength = sizeof(USARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
|
||||
status->txBuffer.requestedLength = sizeof(struct usartpacketheader_t) + payloadLength + sizeof(uint32_t); // +4 for the hash
|
||||
status->txBuffer.busy = 1;
|
||||
status->txBuffer.error = 0;
|
||||
EnqueueCrcTask(status->crcStatus, &status->crcSlot, 0, status->txBuffer.packet.payload, length,
|
||||
|
|
@ -129,7 +129,7 @@ uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length,
|
|||
}
|
||||
|
||||
|
||||
void SetupReceive(USARTSTATUS *status)
|
||||
void SetupReceive(struct usartstatus_t *status)
|
||||
{
|
||||
uint8_t packetIndex = status->activeRxBuf;
|
||||
|
||||
|
|
@ -143,7 +143,7 @@ void SetupReceive(USARTSTATUS *status)
|
|||
}
|
||||
|
||||
|
||||
void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex)
|
||||
void ConsumePacket(struct usartstatus_t *status, uint8_t packetIndex)
|
||||
{
|
||||
struct usart_buffer *buffer = &status->rxBuffers[packetIndex];
|
||||
if(buffer->busy) {
|
||||
|
|
@ -184,7 +184,7 @@ void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t s
|
|||
ub->usartStatus->packetReceivedCallback(ub->usartStatus->packetReceivedCallbacParam, ub);
|
||||
}
|
||||
|
||||
void HandleUsartRxDmaIrq(USARTSTATUS *status)
|
||||
void HandleUsartRxDmaIrq(struct usartstatus_t *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
StatsIncRcvd(&status->stats);
|
||||
|
|
@ -213,7 +213,7 @@ void HandleUsartRxDmaIrq(USARTSTATUS *status)
|
|||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleUsartTxDmaIrq(USARTSTATUS *status)
|
||||
void HandleUsartTxDmaIrq(struct usartstatus_t *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
|
||||
|
|
@ -235,15 +235,15 @@ void HandleUsartTxDmaIrq(USARTSTATUS *status)
|
|||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleUsartIrq(USARTSTATUS *status)
|
||||
void HandleUsartIrq(struct usartstatus_t *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(status->usart);
|
||||
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
if(rcvdLen >= sizeof(USARTPACKETHEADER)) {
|
||||
if(rcvdLen >= sizeof(struct usartpacketheader_t)) {
|
||||
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
|
||||
if(rcvdLen >= sizeof(USARTPACKETHEADER) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
|
||||
if(rcvdLen >= sizeof(struct usartpacketheader_t) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
|
||||
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
else
|
||||
StatsIncPremature_payload(&status->stats);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue