playground-stm32/f407ve_hs_uart
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Convert the project to CMake

Browse source 
revamp f4ll
move f4ll upstream to codeberg
This commit is contained in:
Attila Body 2025-06-08 23:15:46 +02:00
parent bc01b1f0e8
commit b1c676c394
Signed by: abody
GPG key ID: BD0C6214E68FB5CF
244 changed files with 159826 additions and 189336 deletions
Download patch file Download diff file Expand all files Collapse all files

1219
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
View file

File diff suppressed because it is too large Load diff

1043
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
View file

File diff suppressed because it is too large Load diff

2611
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
View file

File diff suppressed because it is too large Load diff

628
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
View file

@ -1,315 +1,313 @@
/**
******************************************************************************
* @file stm32f4xx_hal_dma_ex.c
* @author MCD Application Team
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private Constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/** @addtogroup DMAEx_Exported_Functions_Group1
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer with interrupt
(+) Change on the fly the memory0 or memory1 address.
@endverbatim
* @{
*/
/**
* @brief Starts the multi_buffer DMA Transfer.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
}
else
{
/* Process Locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Enable the double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Return error status */
status = HAL_BUSY;
}
}
return status;
}
/**
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Check callback functions */
if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
{
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Enable the Double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
/* Enable Common interrupts*/
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
hdma->Instance->FCR |= DMA_IT_FE;
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
hdma->Instance->CR |= DMA_IT_HT;
}
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdma);
/* Return error status */
status = HAL_BUSY;
}
return status;
}
/**
* @brief Change the memory0 or memory1 address on the fly.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param Address The new address
* @param memory the memory to be changed, This parameter can be one of
* the following values:
* MEMORY0 /
* MEMORY1
* @note The MEMORY0 address can be changed only when the current transfer use
* MEMORY1 and the MEMORY1 address can be changed only when the current
* transfer use MEMORY0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
{
if(memory == MEMORY0)
{
/* change the memory0 address */
hdma->Instance->M0AR = Address;
}
else
{
/* change the memory1 address */
hdma->Instance->M1AR = Address;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
/**
* @brief Set the DMA Transfer parameter.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
hdma->Instance->PAR = DstAddress;
/* Configure DMA Stream source address */
hdma->Instance->M0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
hdma->Instance->PAR = SrcAddress;
/* Configure DMA Stream destination address */
hdma->Instance->M0AR = DstAddress;
}
}
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f4xx_hal_dma_ex.c
* @author MCD Application Team
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private Constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/** @addtogroup DMAEx_Exported_Functions_Group1
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer with interrupt
(+) Change on the fly the memory0 or memory1 address.
@endverbatim
* @{
*/
/**
* @brief Starts the multi_buffer DMA Transfer.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
}
else
{
/* Process Locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Enable the double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Return error status */
status = HAL_BUSY;
}
}
return status;
}
/**
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Check callback functions */
if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
{
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Enable the Double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
/* Enable Common interrupts*/
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
hdma->Instance->FCR |= DMA_IT_FE;
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
hdma->Instance->CR |= DMA_IT_HT;
}
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdma);
/* Return error status */
status = HAL_BUSY;
}
return status;
}
/**
* @brief Change the memory0 or memory1 address on the fly.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param Address The new address
* @param memory the memory to be changed, This parameter can be one of
* the following values:
* MEMORY0 /
* MEMORY1
* @note The MEMORY0 address can be changed only when the current transfer use
* MEMORY1 and the MEMORY1 address can be changed only when the current
* transfer use MEMORY0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
{
if(memory == MEMORY0)
{
/* change the memory0 address */
hdma->Instance->M0AR = Address;
}
else
{
/* change the memory1 address */
hdma->Instance->M1AR = Address;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
/**
* @brief Set the DMA Transfer parameter.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
hdma->Instance->PAR = DstAddress;
/* Configure DMA Stream source address */
hdma->Instance->M0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
hdma->Instance->PAR = SrcAddress;
/* Configure DMA Stream destination address */
hdma->Instance->M0AR = DstAddress;
}
}
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

993
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
View file

@ -1,440 +1,553 @@
/**
******************************************************************************
* @file stm32f4xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two different
interrupts pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rule:
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
* of bounds [0,3] in following API :
* HAL_EXTI_SetConfigLine
* HAL_EXTI_GetConfigLine
* HAL_EXTI_ClearConfigLine
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Clear EXTI line configuration */
EXTI->IMR &= ~pExtiConfig->Line;
EXTI->EMR &= ~pExtiConfig->Line;
/* Select the Mode for the selected external interrupts */
regval = (uint32_t)EXTI_BASE;
regval += pExtiConfig->Mode;
*(__IO uint32_t *) regval |= pExtiConfig->Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~pExtiConfig->Line;
EXTI->FTSR &= ~pExtiConfig->Line;
/* Select the trigger for the selected external interrupts */
if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)
{
/* Rising Falling edge */
EXTI->RTSR |= pExtiConfig->Line;
EXTI->FTSR |= pExtiConfig->Line;
}
else
{
regval = (uint32_t)EXTI_BASE;
regval += pExtiConfig->Trigger;
*(__IO uint32_t *) regval |= pExtiConfig->Line;
}
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* Get EXTI mode to configiguration structure */
if ((EXTI->IMR & hexti->Line) == hexti->Line)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else if ((EXTI->EMR & hexti->Line) == hexti->Line)
{
pExtiConfig->Mode = EXTI_MODE_EVENT;
}
else
{
/* No MODE selected */
pExtiConfig->Mode = 0x0Bu;
}
/* Get EXTI Trigger to configiguration structure */
if ((EXTI->RTSR & hexti->Line) == hexti->Line)
{
if ((EXTI->FTSR & hexti->Line) == hexti->Line)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
}
else if ((EXTI->FTSR & hexti->Line) == hexti->Line)
{
pExtiConfig->Trigger = EXTI_TRIGGER_FALLING;
}
else
{
/* No Trigger selected */
pExtiConfig->Trigger = 0x00u;
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* 1] Clear interrupt mode */
EXTI->IMR = (EXTI->IMR & ~hexti->Line);
/* 2] Clear event mode */
EXTI->EMR = (EXTI->EMR & ~hexti->Line);
/* 3] Clear triggers */
EXTI->RTSR = (EXTI->RTSR & ~hexti->Line);
EXTI->FTSR = (EXTI->FTSR & ~hexti->Line);
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->RisingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
if (EXTI->PR != 0x00u)
{
/* Clear pending bit */
EXTI->PR = hexti->Line;
/* Call callback */
if (hexti->RisingCallback != NULL)
{
hexti->RisingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Get pending bit */
regaddr = &EXTI->PR;
/* return 1 if bit is set else 0 */
regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line));
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
EXTI->PR = hexti->Line;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
EXTI->SWIER = hexti->Line;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f4xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two different
interrupts pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rule:
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
* of bounds [0,3] in following API :
* HAL_EXTI_SetConfigLine
* HAL_EXTI_GetConfigLine
* HAL_EXTI_ClearConfigLine
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Compute line mask */
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
EXTI->RTSR |= maskline;
}
else
{
EXTI->RTSR &= ~maskline;
}
/* Configure falling trigger */
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
EXTI->FTSR |= maskline;
}
else
{
EXTI->FTSR &= ~maskline;
}
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
EXTI->IMR |= maskline;
}
else
{
EXTI->IMR &= ~maskline;
}
/* Configure event mode : read current mode */
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
EXTI->EMR |= maskline;
}
else
{
EXTI->EMR &= ~maskline;
}
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* Compute line mask */
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
/* Check if selected line is enable */
if ((EXTI->IMR & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
/* Check if selected line is enable */
if ((EXTI->EMR & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* Get default Trigger and GPIOSel configuration */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
/* Check if configuration of selected line is enable */
if ((EXTI->RTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
/* Get falling configuration */
/* Check if configuration of selected line is enable */
if ((EXTI->FTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
}
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
EXTI->IMR = (EXTI->IMR & ~maskline);
/* 2] Clear event mode */
EXTI->EMR = (EXTI->EMR & ~maskline);
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
{
EXTI->RTSR = (EXTI->RTSR & ~maskline);
EXTI->FTSR = (EXTI->FTSR & ~maskline);
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
uint32_t regval;
uint32_t maskline;
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regval = (EXTI->PR & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
EXTI->PR = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* return 1 if bit is set else 0 */
regval = ((EXTI->PR & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
uint32_t maskline;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Clear Pending bit */
EXTI->PR = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Generate Software interrupt */
EXTI->SWIER = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1541
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
View file

File diff suppressed because it is too large Load diff

2694
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
View file

File diff suppressed because it is too large Load diff

347
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
View file

@ -1,175 +1,172 @@
/**
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @brief FLASH RAMFUNC module driver.
* This file provides a FLASH firmware functions which should be
* executed from internal SRAM
* + Stop/Start the flash interface while System Run
* + Enable/Disable the flash sleep while System Run
@verbatim
==============================================================================
##### APIs executed from Internal RAM #####
==============================================================================
[..]
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
Functions that are be executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
-----------------------
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
*** GNU Compiler ***
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
* @{
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
* @brief Peripheral Extended features functions
*
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM
transfers.
@endverbatim
* @{
*/
/**
* @brief Stop the flash interface while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Stop the flash interface while System Run */
SET_BIT(PWR->CR, PWR_CR_FISSR);
return HAL_OK;
}
/**
* @brief Start the flash interface while System Run
* @note This mode is only available for STM32F411xx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Start the flash interface while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
return HAL_OK;
}
/**
* @brief Enable the flash sleep while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode could n't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable the flash sleep while System Run */
SET_BIT(PWR->CR, PWR_CR_FMSSR);
return HAL_OK;
}
/**
* @brief Disable the flash sleep while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Disable the flash sleep while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @brief FLASH RAMFUNC module driver.
* This file provides a FLASH firmware functions which should be
* executed from internal SRAM
* + Stop/Start the flash interface while System Run
* + Enable/Disable the flash sleep while System Run
@verbatim
==============================================================================
##### APIs executed from Internal RAM #####
==============================================================================
[..]
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
Functions that are be executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
-----------------------
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
*** GNU Compiler ***
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
* @{
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
* @brief Peripheral Extended features functions
*
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM
transfers.
@endverbatim
* @{
*/
/**
* @brief Stop the flash interface while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Stop the flash interface while System Run */
SET_BIT(PWR->CR, PWR_CR_FISSR);
return HAL_OK;
}
/**
* @brief Start the flash interface while System Run
* @note This mode is only available for STM32F411xx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Start the flash interface while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
return HAL_OK;
}
/**
* @brief Enable the flash sleep while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode could n't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable the flash sleep while System Run */
SET_BIT(PWR->CR, PWR_CR_FMSSR);
return HAL_OK;
}
/**
* @brief Disable the flash sleep while System Run
* @note This mode is only available for STM32F41xxx/STM32F446xx devices.
* @note This mode couldn't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
{
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Disable the flash sleep while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1069
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
View file

File diff suppressed because it is too large Load diff

3207
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c Normal file
View file

File diff suppressed because it is too large Load diff

2395
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c Normal file
View file

File diff suppressed because it is too large Load diff

1641
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c Normal file
View file

File diff suppressed because it is too large Load diff

961
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c Normal file
View file

@ -0,0 +1,961 @@
/**
******************************************************************************
* @file stm32f4xx_hal_pccard.c
* @author MCD Application Team
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions
to interface with PCCARD devices. This driver is used for:
(+) PCCARD/Compact Flash memory configuration sequence using the function
HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
both common and attribute spaces.
(+) Read PCCARD/Compact Flash memory maker and device IDs using the function
HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
the CompactFlash_ID structure declared by the function caller.
(+) Access PCCARD/Compact Flash memory by read/write operations using the functions
HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
(+) Perform PCCARD/Compact Flash Reset chip operation using the function
HAL_PCCARD_Reset()/HAL_CF_Reset.
(+) Perform PCCARD/Compact Flash erase sector operation using the function
HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
(+) Read the PCCARD/Compact Flash status operation using the function
HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
(+) You can monitor the PCCARD/Compact Flash device HAL state by calling
the function HAL_PCCARD_GetState()/HAL_CF_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
operations. If a PCCARD/Compact Flash device contains different operations
and/or implementations, it should be implemented separately.
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_PCCARD_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : PCCARD MspInit.
(+) MspDeInitCallback : PCCARD MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_PCCARD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : PCCARD MspInit.
(+) MspDeInitCallback : PCCARD MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_PCCARD_Init and if the state is HAL_PCCARD_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_PCCARD_Init
and HAL_PCCARD_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_PCCARD_Init and HAL_PCCARD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_PCCARD_RegisterCallback before calling HAL_PCCARD_DeInit
or HAL_PCCARD_Init function.
When The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
#if defined(FMC_Bank4) || defined(FSMC_Bank4)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
#ifdef HAL_PCCARD_MODULE_ENABLED
/** @defgroup PCCARD PCCARD
* @brief PCCARD HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
* @{
*/
#define PCCARD_TIMEOUT_READ_ID 0x0000FFFFU
#define PCCARD_TIMEOUT_READ_WRITE_SECTOR 0x0000FFFFU
#define PCCARD_TIMEOUT_ERASE_SECTOR 0x00000400U
#define PCCARD_TIMEOUT_STATUS 0x01000000U
#define PCCARD_STATUS_OK (uint8_t)0x58
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function ----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
* @{
*/
/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### PCCARD Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize
the PCCARD memory
@endverbatim
* @{
*/
/**
* @brief Perform the PCCARD memory Initialization sequence
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param ComSpaceTiming Common space timing structure
* @param AttSpaceTiming Attribute space timing structure
* @param IOSpaceTiming IO space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
{
/* Check the PCCARD controller state */
if (hpccard == NULL)
{
return HAL_ERROR;
}
if (hpccard->State == HAL_PCCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpccard->Lock = HAL_UNLOCKED;
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
if (hpccard->MspInitCallback == NULL)
{
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
}
hpccard->ItCallback = HAL_PCCARD_ITCallback;
/* Init the low level hardware */
hpccard->MspInitCallback(hpccard);
#else
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
}
/* Initialize the PCCARD state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD control Interface */
FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
/* Init PCCARD common space timing Interface */
FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
/* Init PCCARD attribute space timing Interface */
FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
/* Init PCCARD IO space timing Interface */
FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
/* Enable the PCCARD device */
__FMC_PCCARD_ENABLE(hpccard->Instance);
/* Update the PCCARD state */
hpccard->State = HAL_PCCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief Perform the PCCARD memory De-initialization sequence
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
{
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
if (hpccard->MspDeInitCallback == NULL)
{
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
}
/* DeInit the low level hardware */
hpccard->MspDeInitCallback(hpccard);
#else
/* De-Initialize the low level hardware (MSP) */
HAL_PCCARD_MspDeInit(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Configure the PCCARD registers with their reset values */
FMC_PCCARD_DeInit(hpccard->Instance);
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief PCCARD MSP Init
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpccard);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCCARD_MspInit could be implemented in the user file
*/
}
/**
* @brief PCCARD MSP DeInit
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpccard);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCCARD_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### PCCARD Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the PCCARD memory
@endverbatim
* @{
*/
/**
* @brief Read Compact Flash's ID.
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param CompactFlash_ID Compact flash ID structure.
* @param pStatus pointer to compact flash status
* @retval HAL status
*
*/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Initialize timeout value */
timeout = PCCARD_TIMEOUT_READ_ID;
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize the PCCARD status */
*pStatus = PCCARD_READY;
/* Send the Identify Command */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xECEC;
/* Read PCCARD IDs and timeout treatment */
do
{
/* Read the PCCARD status */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
else
{
/* Read PCCARD ID bytes */
for (index = 0U; index < 16U; index++)
{
CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
}
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Read sector from PCCARD memory
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param pBuffer pointer to destination read buffer
* @param SectorAddress Sector address to read
* @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Initialize timeout value */
timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
do
{
/* wait till the Status = 0x80 */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status == 0x80U) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
do
{
/* wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Read bytes */
for (; index < PCCARD_SECTOR_SIZE; index++)
{
*(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Write sector to PCCARD memory
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param pBuffer pointer to source write buffer
* @param SectorAddress Sector address to write
* @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Initialize timeout value */
timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
do
{
/* Wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Write bytes */
for (; index < PCCARD_SECTOR_SIZE; index++)
{
*(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
}
do
{
/* Wait till the Status = PCCARD_STATUS_WRITE_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status != PCCARD_STATUS_WRITE_OK) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Erase sector from PCCARD memory
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param SectorAddress Sector address to erase
* @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
/* wait till the PCCARD is ready */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
while ((status != PCCARD_STATUS_WRITE_OK) && timeout)
{
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Reset the PCCARD memory
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
{
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Provide a SW reset and Read and verify the:
- PCCard Configuration Option Register at address 0x98000200 --> 0x80
- Card Configuration and Status Register at address 0x98000202 --> 0x00
- Pin Replacement Register at address 0x98000204 --> 0x0C
- Socket and Copy Register at address 0x98000206 --> 0x00
*/
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
*(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief This function handles PCCARD device interrupt request.
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
{
/* Check PCCARD interrupt Rising edge flag */
if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
{
/* PCCARD interrupt callback*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Rising edge pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
}
/* Check PCCARD interrupt Level flag */
if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
{
/* PCCARD interrupt callback*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Level pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
}
/* Check PCCARD interrupt Falling edge flag */
if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
{
/* PCCARD interrupt callback*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Falling edge pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
}
/* Check PCCARD interrupt FIFO empty flag */
if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
{
/* PCCARD interrupt callback*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt FIFO empty pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
}
}
/**
* @brief PCCARD interrupt feature callback
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpccard);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCCARD_ITCallback could be implemented in the user file
*/
}
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User PCCARD Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hpccard : PCCARD handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_PCCARD_MSP_INIT_CB_ID PCCARD MspInit callback ID
* @arg @ref HAL_PCCARD_MSP_DEINIT_CB_ID PCCARD MspDeInit callback ID
* @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
pPCCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpccard);
if (hpccard->State == HAL_PCCARD_STATE_READY)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = pCallback;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = pCallback;
break;
case HAL_PCCARD_IT_CB_ID :
hpccard->ItCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hpccard->State == HAL_PCCARD_STATE_RESET)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = pCallback;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpccard);
return status;
}
/**
* @brief Unregister a User PCCARD Callback
* PCCARD Callback is redirected to the weak (surcharged) predefined callback
* @param hpccard : PCCARD handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_PCCARD_MSP_INIT_CB_ID PCCARD MspInit callback ID
* @arg @ref HAL_PCCARD_MSP_DEINIT_CB_ID PCCARD MspDeInit callback ID
* @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpccard);
if (hpccard->State == HAL_PCCARD_STATE_READY)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
break;
case HAL_PCCARD_IT_CB_ID :
hpccard->ItCallback = HAL_PCCARD_ITCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hpccard->State == HAL_PCCARD_STATE_RESET)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpccard);
return status;
}
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup PCCARD_Exported_Functions_Group3 State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### PCCARD State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the PCCARD controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief return the PCCARD controller state
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL state
*/
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
{
return hpccard->State;
}
/**
* @brief Get the compact flash memory status
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval New status of the PCCARD operation. This parameter can be:
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - CompactFlash_READY: when memory is ready for the next operation
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
uint32_t timeout = PCCARD_TIMEOUT_STATUS;
uint32_t status_pccard = 0U;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_PCCARD_STATUS_ONGOING;
}
status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
while ((status_pccard == PCCARD_BUSY) && timeout)
{
status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if (timeout == 0U)
{
status_pccard = PCCARD_TIMEOUT_ERROR;
}
/* Return the operation status */
return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
* @brief Reads the Compact Flash memory status using the Read status command
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval The status of the Compact Flash memory. This parameter can be:
* - CompactFlash_BUSY: when memory is busy
* - CompactFlash_READY: when memory is ready for the next operation
* - CompactFlash_ERROR: when the previous operation generates error
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
uint8_t data = 0U;
uint8_t status_pccard = PCCARD_BUSY;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_PCCARD_STATUS_ONGOING;
}
/* Read status operation */
data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
if ((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
{
status_pccard = PCCARD_TIMEOUT_ERROR;
}
else if ((data & PCCARD_READY) == PCCARD_READY)
{
status_pccard = PCCARD_READY;
}
return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PCCARD_MODULE_ENABLED */
/**
* @}
*/
#endif /* FMC_Bank4 || FSMC_Bank4 */

4617
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c
View file

File diff suppressed because it is too large Load diff

695
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c
View file

@ -1,348 +1,347 @@
/**
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
* @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Extended features functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Update FIFO configuration
@endverbatim
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Set Tx FIFO
* @param hpcd PCD handle
* @param fifo The number of Tx fifo
* @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i;
uint32_t Tx_Offset;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txm can use the space allocated for Txn.
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
if (fifo == 0U)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0U; i < (fifo - 1U); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
}
return HAL_OK;
}
/**
* @brief Set Rx FIFO
* @param hpcd PCD handle
* @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 1U;
hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief Deactivate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 0U;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait Detect flag or a timeout is happen*/
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > 1000U)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
}
}
/* Right response got */
HAL_Delay(200U);
/* Check Detect flag*/
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/*Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
{
/* Case of Standard Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
{
/* case Dedicated Charging Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* case Charging Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Battery Charging capability discovery finished */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/**
* @brief Activate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
/* Power Down USB tranceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Enable Battery charging */
USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
hpcd->battery_charging_active = 1U;
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
/* Disable Battery charging */
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
hpcd->battery_charging_active = 0U;
return HAL_OK;
}
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
* @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Update FIFO configuration
@endverbatim
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Set Tx FIFO
* @param hpcd PCD handle
* @param fifo The number of Tx fifo
* @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i;
uint32_t Tx_Offset;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txm can use the space allocated for Txn.
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
if (fifo == 0U)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0U; i < (fifo - 1U); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
}
return HAL_OK;
}
/**
* @brief Set Rx FIFO
* @param hpcd PCD handle
* @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|| defined(STM32F423xx)
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 1U;
hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief Deactivate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 0U;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
defined(STM32F423xx) */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \
|| defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait for Min DCD Timeout */
HAL_Delay(300U);
/* Check Detect flag */
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/* Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
{
/* Case of Standard Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
{
/* case Dedicated Charging Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* case Charging Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Battery Charging capability discovery finished */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
/* Check for the Timeout, else start USB Device */
if ((HAL_GetTick() - tickstart) > 1000U)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/**
* @brief Activate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
/* Power Down USB transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Enable Battery charging */
USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
hpcd->battery_charging_active = 1U;
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
/* Disable Battery charging */
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
hpcd->battery_charging_active = 0U;
return HAL_OK;
}
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1157
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
View file

File diff suppressed because it is too large Load diff

1204
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
View file

File diff suppressed because it is too large Load diff

2221
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
View file

File diff suppressed because it is too large Load diff

7575
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
View file

File diff suppressed because it is too large Load diff

6603
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
View file

File diff suppressed because it is too large Load diff

2029
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c
View file

File diff suppressed because it is too large Load diff

6633
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c
View file

File diff suppressed because it is too large Load diff

1969
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c
View file

File diff suppressed because it is too large Load diff

210
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c
View file

@ -1,107 +1,103 @@
/**
******************************************************************************
* @file stm32f4xx_ll_crc.c
* @author MCD Application Team
* @brief CRC LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_crc.h"
#include "stm32f4xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
#if defined (CRC)
/** @addtogroup CRC_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRC_LL_Exported_Functions
* @{
*/
/** @addtogroup CRC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize CRC registers (Registers restored to their default values).
* @param CRCx CRC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: CRC registers are de-initialized
* - ERROR: CRC registers are not de-initialized
*/
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(CRCx));
if (CRCx == CRC)
{
/* Force CRC reset */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
/* Release CRC reset */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
}
else
{
status = ERROR;
}
return (status);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (CRC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f4xx_ll_crc.c
* @author MCD Application Team
* @brief CRC LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_crc.h"
#include "stm32f4xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
#if defined (CRC)
/** @addtogroup CRC_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRC_LL_Exported_Functions
* @{
*/
/** @addtogroup CRC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize CRC registers (Registers restored to their default values).
* @param CRCx CRC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: CRC registers are de-initialized
* - ERROR: CRC registers are not de-initialized
*/
ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(CRCx));
if (CRCx == CRC)
{
/* Force CRC reset */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
/* Release CRC reset */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
}
else
{
status = ERROR;
}
return (status);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (CRC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

848
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c
View file

@ -1,425 +1,423 @@
/**
******************************************************************************
* @file stm32f4xx_ll_dma.c
* @author MCD Application Team
* @brief DMA LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_dma.h"
#include "stm32f4xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
#if defined (DMA1) || defined (DMA2)
/** @defgroup DMA_LL DMA
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DMA_LL_Private_Macros
* @{
*/
#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
((__VALUE__) == LL_DMA_MODE_PFCTRL))
#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
((__VALUE__) == LL_DMA_CHANNEL_1) || \
((__VALUE__) == LL_DMA_CHANNEL_2) || \
((__VALUE__) == LL_DMA_CHANNEL_3) || \
((__VALUE__) == LL_DMA_CHANNEL_4) || \
((__VALUE__) == LL_DMA_CHANNEL_5) || \
((__VALUE__) == LL_DMA_CHANNEL_6) || \
((__VALUE__) == LL_DMA_CHANNEL_7))
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
(((STREAM) == LL_DMA_STREAM_0) || \
((STREAM) == LL_DMA_STREAM_1) || \
((STREAM) == LL_DMA_STREAM_2) || \
((STREAM) == LL_DMA_STREAM_3) || \
((STREAM) == LL_DMA_STREAM_4) || \
((STREAM) == LL_DMA_STREAM_5) || \
((STREAM) == LL_DMA_STREAM_6) || \
((STREAM) == LL_DMA_STREAM_7) || \
((STREAM) == LL_DMA_STREAM_ALL))) ||\
(((INSTANCE) == DMA2) && \
(((STREAM) == LL_DMA_STREAM_0) || \
((STREAM) == LL_DMA_STREAM_1) || \
((STREAM) == LL_DMA_STREAM_2) || \
((STREAM) == LL_DMA_STREAM_3) || \
((STREAM) == LL_DMA_STREAM_4) || \
((STREAM) == LL_DMA_STREAM_5) || \
((STREAM) == LL_DMA_STREAM_6) || \
((STREAM) == LL_DMA_STREAM_7) || \
((STREAM) == LL_DMA_STREAM_ALL))))
#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
((STATE) == LL_DMA_FIFOMODE_ENABLE))
#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
((BURST) == LL_DMA_MBURST_INC4) || \
((BURST) == LL_DMA_MBURST_INC8) || \
((BURST) == LL_DMA_MBURST_INC16))
#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
((BURST) == LL_DMA_PBURST_INC4) || \
((BURST) == LL_DMA_PBURST_INC8) || \
((BURST) == LL_DMA_PBURST_INC16))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_LL_Exported_Functions
* @{
*/
/** @addtogroup DMA_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the DMA registers to their default reset values.
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
* @arg @ref LL_DMA_STREAM_1
* @arg @ref LL_DMA_STREAM_2
* @arg @ref LL_DMA_STREAM_3
* @arg @ref LL_DMA_STREAM_4
* @arg @ref LL_DMA_STREAM_5
* @arg @ref LL_DMA_STREAM_6
* @arg @ref LL_DMA_STREAM_7
* @arg @ref LL_DMA_STREAM_ALL
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are de-initialized
* - ERROR: DMA registers are not de-initialized
*/
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
{
DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
ErrorStatus status = SUCCESS;
/* Check the DMA Instance DMAx and Stream parameters*/
assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
if (Stream == LL_DMA_STREAM_ALL)
{
if (DMAx == DMA1)
{
/* Force reset of DMA clock */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
/* Release reset of DMA clock */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
}
else if (DMAx == DMA2)
{
/* Force reset of DMA clock */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
/* Release reset of DMA clock */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
}
else
{
status = ERROR;
}
}
else
{
/* Disable the selected Stream */
LL_DMA_DisableStream(DMAx,Stream);
/* Get the DMA Stream Instance */
tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
/* Reset DMAx_Streamy configuration register */
LL_DMA_WriteReg(tmp, CR, 0U);
/* Reset DMAx_Streamy remaining bytes register */
LL_DMA_WriteReg(tmp, NDTR, 0U);
/* Reset DMAx_Streamy peripheral address register */
LL_DMA_WriteReg(tmp, PAR, 0U);
/* Reset DMAx_Streamy memory address register */
LL_DMA_WriteReg(tmp, M0AR, 0U);
/* Reset DMAx_Streamy memory address register */
LL_DMA_WriteReg(tmp, M1AR, 0U);
/* Reset DMAx_Streamy FIFO control register */
LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
/* Reset Channel register field for DMAx Stream*/
LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
if(Stream == LL_DMA_STREAM_0)
{
/* Reset the Stream0 pending flags */
DMAx->LIFCR = 0x0000003FU;
}
else if(Stream == LL_DMA_STREAM_1)
{
/* Reset the Stream1 pending flags */
DMAx->LIFCR = 0x00000F40U;
}
else if(Stream == LL_DMA_STREAM_2)
{
/* Reset the Stream2 pending flags */
DMAx->LIFCR = 0x003F0000U;
}
else if(Stream == LL_DMA_STREAM_3)
{
/* Reset the Stream3 pending flags */
DMAx->LIFCR = 0x0F400000U;
}
else if(Stream == LL_DMA_STREAM_4)
{
/* Reset the Stream4 pending flags */
DMAx->HIFCR = 0x0000003FU;
}
else if(Stream == LL_DMA_STREAM_5)
{
/* Reset the Stream5 pending flags */
DMAx->HIFCR = 0x00000F40U;
}
else if(Stream == LL_DMA_STREAM_6)
{
/* Reset the Stream6 pending flags */
DMAx->HIFCR = 0x003F0000U;
}
else if(Stream == LL_DMA_STREAM_7)
{
/* Reset the Stream7 pending flags */
DMAx->HIFCR = 0x0F400000U;
}
else
{
status = ERROR;
}
}
return status;
}
/**
* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
* @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
* @arg @ref __LL_DMA_GET_INSTANCE
* @arg @ref __LL_DMA_GET_STREAM
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
* @arg @ref LL_DMA_STREAM_1
* @arg @ref LL_DMA_STREAM_2
* @arg @ref LL_DMA_STREAM_3
* @arg @ref LL_DMA_STREAM_4
* @arg @ref LL_DMA_STREAM_5
* @arg @ref LL_DMA_STREAM_6
* @arg @ref LL_DMA_STREAM_7
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are initialized
* - ERROR: Not applicable
*/
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Check the DMA Instance DMAx and Stream parameters*/
assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
/* Check the DMA parameters from DMA_InitStruct */
assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
/* Check the memory burst, peripheral burst and FIFO threshold parameters only
when FIFO mode is enabled */
if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
{
assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
}
/*---------------------------- DMAx SxCR Configuration ------------------------
* Configure DMAx_Streamy: data transfer direction, data transfer mode,
* peripheral and memory increment mode,
* data size alignment and priority level with parameters :
* - Direction: DMA_SxCR_DIR[1:0] bits
* - Mode: DMA_SxCR_CIRC bit
* - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
* - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
* - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
* - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
* - Priority: DMA_SxCR_PL[1:0] bits
*/
LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
DMA_InitStruct->Mode | \
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
DMA_InitStruct->MemoryOrM2MDstIncMode | \
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
DMA_InitStruct->MemoryOrM2MDstDataSize | \
DMA_InitStruct->Priority
);
if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
{
/*---------------------------- DMAx SxFCR Configuration ------------------------
* Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
* - FIFOMode: DMA_SxFCR_DMDIS bit
* - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
*/
LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
/*---------------------------- DMAx SxCR Configuration --------------------------
* Configure DMAx_Streamy: memory burst transfer with parameters :
* - MemBurst: DMA_SxCR_MBURST[1:0] bits
*/
LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
/*---------------------------- DMAx SxCR Configuration --------------------------
* Configure DMAx_Streamy: peripheral burst transfer with parameters :
* - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
*/
LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
}
/*-------------------------- DMAx SxM0AR Configuration --------------------------
* Configure the memory or destination base address with parameter :
* - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
*/
LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
/*-------------------------- DMAx SxPAR Configuration ---------------------------
* Configure the peripheral or source base address with parameter :
* - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
*/
LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
/*--------------------------- DMAx SxNDTR Configuration -------------------------
* Configure the peripheral base address with parameter :
* - NbData: DMA_SxNDT[15:0] bits
*/
LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
/*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
* Configure the peripheral base address with parameter :
* - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
*/
LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
return SUCCESS;
}
/**
* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval None
*/
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Set DMA_InitStruct fields to default values */
DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
DMA_InitStruct->NbData = 0x00000000U;
DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMA1 || DMA2 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f4xx_ll_dma.c
* @author MCD Application Team
* @brief DMA LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_dma.h"
#include "stm32f4xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
#if defined (DMA1) || defined (DMA2)
/** @defgroup DMA_LL DMA
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DMA_LL_Private_Macros
* @{
*/
#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
((__VALUE__) == LL_DMA_MODE_PFCTRL))
#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
((__VALUE__) == LL_DMA_CHANNEL_1) || \
((__VALUE__) == LL_DMA_CHANNEL_2) || \
((__VALUE__) == LL_DMA_CHANNEL_3) || \
((__VALUE__) == LL_DMA_CHANNEL_4) || \
((__VALUE__) == LL_DMA_CHANNEL_5) || \
((__VALUE__) == LL_DMA_CHANNEL_6) || \
((__VALUE__) == LL_DMA_CHANNEL_7))
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
(((STREAM) == LL_DMA_STREAM_0) || \
((STREAM) == LL_DMA_STREAM_1) || \
((STREAM) == LL_DMA_STREAM_2) || \
((STREAM) == LL_DMA_STREAM_3) || \
((STREAM) == LL_DMA_STREAM_4) || \
((STREAM) == LL_DMA_STREAM_5) || \
((STREAM) == LL_DMA_STREAM_6) || \
((STREAM) == LL_DMA_STREAM_7) || \
((STREAM) == LL_DMA_STREAM_ALL))) ||\
(((INSTANCE) == DMA2) && \
(((STREAM) == LL_DMA_STREAM_0) || \
((STREAM) == LL_DMA_STREAM_1) || \
((STREAM) == LL_DMA_STREAM_2) || \
((STREAM) == LL_DMA_STREAM_3) || \
((STREAM) == LL_DMA_STREAM_4) || \
((STREAM) == LL_DMA_STREAM_5) || \
((STREAM) == LL_DMA_STREAM_6) || \
((STREAM) == LL_DMA_STREAM_7) || \
((STREAM) == LL_DMA_STREAM_ALL))))
#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
((STATE) == LL_DMA_FIFOMODE_ENABLE))
#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
((BURST) == LL_DMA_MBURST_INC4) || \
((BURST) == LL_DMA_MBURST_INC8) || \
((BURST) == LL_DMA_MBURST_INC16))
#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
((BURST) == LL_DMA_PBURST_INC4) || \
((BURST) == LL_DMA_PBURST_INC8) || \
((BURST) == LL_DMA_PBURST_INC16))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_LL_Exported_Functions
* @{
*/
/** @addtogroup DMA_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the DMA registers to their default reset values.
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
* @arg @ref LL_DMA_STREAM_1
* @arg @ref LL_DMA_STREAM_2
* @arg @ref LL_DMA_STREAM_3
* @arg @ref LL_DMA_STREAM_4
* @arg @ref LL_DMA_STREAM_5
* @arg @ref LL_DMA_STREAM_6
* @arg @ref LL_DMA_STREAM_7
* @arg @ref LL_DMA_STREAM_ALL
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are de-initialized
* - ERROR: DMA registers are not de-initialized
*/
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
{
DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
ErrorStatus status = SUCCESS;
/* Check the DMA Instance DMAx and Stream parameters*/
assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
if (Stream == LL_DMA_STREAM_ALL)
{
if (DMAx == DMA1)
{
/* Force reset of DMA clock */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
/* Release reset of DMA clock */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
}
else if (DMAx == DMA2)
{
/* Force reset of DMA clock */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
/* Release reset of DMA clock */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
}
else
{
status = ERROR;
}
}
else
{
/* Disable the selected Stream */
LL_DMA_DisableStream(DMAx,Stream);
/* Get the DMA Stream Instance */
tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
/* Reset DMAx_Streamy configuration register */
LL_DMA_WriteReg(tmp, CR, 0U);
/* Reset DMAx_Streamy remaining bytes register */
LL_DMA_WriteReg(tmp, NDTR, 0U);
/* Reset DMAx_Streamy peripheral address register */
LL_DMA_WriteReg(tmp, PAR, 0U);
/* Reset DMAx_Streamy memory address register */
LL_DMA_WriteReg(tmp, M0AR, 0U);
/* Reset DMAx_Streamy memory address register */
LL_DMA_WriteReg(tmp, M1AR, 0U);
/* Reset DMAx_Streamy FIFO control register */
LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
/* Reset Channel register field for DMAx Stream*/
LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
if(Stream == LL_DMA_STREAM_0)
{
/* Reset the Stream0 pending flags */
DMAx->LIFCR = 0x0000003FU;
}
else if(Stream == LL_DMA_STREAM_1)
{
/* Reset the Stream1 pending flags */
DMAx->LIFCR = 0x00000F40U;
}
else if(Stream == LL_DMA_STREAM_2)
{
/* Reset the Stream2 pending flags */
DMAx->LIFCR = 0x003F0000U;
}
else if(Stream == LL_DMA_STREAM_3)
{
/* Reset the Stream3 pending flags */
DMAx->LIFCR = 0x0F400000U;
}
else if(Stream == LL_DMA_STREAM_4)
{
/* Reset the Stream4 pending flags */
DMAx->HIFCR = 0x0000003FU;
}
else if(Stream == LL_DMA_STREAM_5)
{
/* Reset the Stream5 pending flags */
DMAx->HIFCR = 0x00000F40U;
}
else if(Stream == LL_DMA_STREAM_6)
{
/* Reset the Stream6 pending flags */
DMAx->HIFCR = 0x003F0000U;
}
else if(Stream == LL_DMA_STREAM_7)
{
/* Reset the Stream7 pending flags */
DMAx->HIFCR = 0x0F400000U;
}
else
{
status = ERROR;
}
}
return status;
}
/**
* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
* @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
* @arg @ref __LL_DMA_GET_INSTANCE
* @arg @ref __LL_DMA_GET_STREAM
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
* @arg @ref LL_DMA_STREAM_1
* @arg @ref LL_DMA_STREAM_2
* @arg @ref LL_DMA_STREAM_3
* @arg @ref LL_DMA_STREAM_4
* @arg @ref LL_DMA_STREAM_5
* @arg @ref LL_DMA_STREAM_6
* @arg @ref LL_DMA_STREAM_7
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are initialized
* - ERROR: Not applicable
*/
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Check the DMA Instance DMAx and Stream parameters*/
assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
/* Check the DMA parameters from DMA_InitStruct */
assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
/* Check the memory burst, peripheral burst and FIFO threshold parameters only
when FIFO mode is enabled */
if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
{
assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
}
/*---------------------------- DMAx SxCR Configuration ------------------------
* Configure DMAx_Streamy: data transfer direction, data transfer mode,
* peripheral and memory increment mode,
* data size alignment and priority level with parameters :
* - Direction: DMA_SxCR_DIR[1:0] bits
* - Mode: DMA_SxCR_CIRC bit
* - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
* - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
* - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
* - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
* - Priority: DMA_SxCR_PL[1:0] bits
*/
LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
DMA_InitStruct->Mode | \
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
DMA_InitStruct->MemoryOrM2MDstIncMode | \
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
DMA_InitStruct->MemoryOrM2MDstDataSize | \
DMA_InitStruct->Priority
);
if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
{
/*---------------------------- DMAx SxFCR Configuration ------------------------
* Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
* - FIFOMode: DMA_SxFCR_DMDIS bit
* - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
*/
LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
/*---------------------------- DMAx SxCR Configuration --------------------------
* Configure DMAx_Streamy: memory burst transfer with parameters :
* - MemBurst: DMA_SxCR_MBURST[1:0] bits
*/
LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
/*---------------------------- DMAx SxCR Configuration --------------------------
* Configure DMAx_Streamy: peripheral burst transfer with parameters :
* - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
*/
LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
}
/*-------------------------- DMAx SxM0AR Configuration --------------------------
* Configure the memory or destination base address with parameter :
* - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
*/
LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
/*-------------------------- DMAx SxPAR Configuration ---------------------------
* Configure the peripheral or source base address with parameter :
* - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
*/
LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
/*--------------------------- DMAx SxNDTR Configuration -------------------------
* Configure the peripheral base address with parameter :
* - NbData: DMA_SxNDT[15:0] bits
*/
LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
/*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
* Configure the peripheral base address with parameter :
* - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
*/
LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
return SUCCESS;
}
/**
* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval None
*/
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Set DMA_InitStruct fields to default values */
DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
DMA_InitStruct->NbData = 0x00000000U;
DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMA1 || DMA2 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

426
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c
View file

@ -1,214 +1,212 @@
/**
******************************************************************************
* @file stm32f4xx_ll_exti.c
* @author MCD Application Team
* @brief EXTI LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_exti.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup EXTI_LL_Private_Macros
* @{
*/
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_LL_Exported_Functions
* @{
*/
/** @addtogroup EXTI_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the EXTI registers to their default reset values.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are de-initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_DeInit(void)
{
/* Interrupt mask register set to default reset values */
LL_EXTI_WriteReg(IMR, 0x00000000U);
/* Event mask register set to default reset values */
LL_EXTI_WriteReg(EMR, 0x00000000U);
/* Rising Trigger selection register set to default reset values */
LL_EXTI_WriteReg(RTSR, 0x00000000U);
/* Falling Trigger selection register set to default reset values */
LL_EXTI_WriteReg(FTSR, 0x00000000U);
/* Software interrupt event register set to default reset values */
LL_EXTI_WriteReg(SWIER, 0x00000000U);
/* Pending register set to default reset values */
LL_EXTI_WriteReg(PR, 0x00FFFFFFU);
return SUCCESS;
}
/**
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
/* ENABLE LineCommand */
if (EXTI_InitStruct->LineCommand != DISABLE)
{
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
/* Configure EXTI Lines in range from 0 to 31 */
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
{
switch (EXTI_InitStruct->Mode)
{
case LL_EXTI_MODE_IT:
/* First Disable Event on provided Lines */
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable IT on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_EVENT:
/* First Disable IT on provided Lines */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Event on provided Lines */
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_IT_EVENT:
/* Directly Enable IT & Event on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
switch (EXTI_InitStruct->Trigger)
{
case LL_EXTI_TRIGGER_RISING:
/* First Disable Falling Trigger on provided Lines */
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Rising Trigger on provided Lines */
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_FALLING:
/* First Disable Rising Trigger on provided Lines */
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Falling Trigger on provided Lines */
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_RISING_FALLING:
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
}
}
}
/* DISABLE LineCommand */
else
{
/* De-configure EXTI Lines in range from 0 to 31 */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
}
return status;
}
/**
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval None
*/
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
EXTI_InitStruct->LineCommand = DISABLE;
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (EXTI) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f4xx_ll_exti.c
* @author MCD Application Team
* @brief EXTI LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_exti.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup EXTI_LL_Private_Macros
* @{
*/
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_LL_Exported_Functions
* @{
*/
/** @addtogroup EXTI_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the EXTI registers to their default reset values.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are de-initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_DeInit(void)
{
/* Interrupt mask register set to default reset values */
LL_EXTI_WriteReg(IMR, 0x00000000U);
/* Event mask register set to default reset values */
LL_EXTI_WriteReg(EMR, 0x00000000U);
/* Rising Trigger selection register set to default reset values */
LL_EXTI_WriteReg(RTSR, 0x00000000U);
/* Falling Trigger selection register set to default reset values */
LL_EXTI_WriteReg(FTSR, 0x00000000U);
/* Software interrupt event register set to default reset values */
LL_EXTI_WriteReg(SWIER, 0x00000000U);
/* Pending register set to default reset values */
LL_EXTI_WriteReg(PR, 0x00FFFFFFU);
return SUCCESS;
}
/**
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
/* ENABLE LineCommand */
if (EXTI_InitStruct->LineCommand != DISABLE)
{
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
/* Configure EXTI Lines in range from 0 to 31 */
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
{
switch (EXTI_InitStruct->Mode)
{
case LL_EXTI_MODE_IT:
/* First Disable Event on provided Lines */
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable IT on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_EVENT:
/* First Disable IT on provided Lines */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Event on provided Lines */
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_IT_EVENT:
/* Directly Enable IT & Event on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
switch (EXTI_InitStruct->Trigger)
{
case LL_EXTI_TRIGGER_RISING:
/* First Disable Falling Trigger on provided Lines */
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Rising Trigger on provided Lines */
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_FALLING:
/* First Disable Rising Trigger on provided Lines */
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Falling Trigger on provided Lines */
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_RISING_FALLING:
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
}
}
}
/* DISABLE LineCommand */
else
{
/* De-configure EXTI Lines in range from 0 to 31 */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
}
return status;
}
/**
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval None
*/
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
EXTI_InitStruct->LineCommand = DISABLE;
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (EXTI) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

2070
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c
View file

File diff suppressed because it is too large Load diff

610
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c
View file

@ -1,307 +1,303 @@
/**
******************************************************************************
* @file stm32f4xx_ll_gpio.c
* @author MCD Application Team
* @brief GPIO LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_gpio.h"
#include "stm32f4xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
/** @addtogroup GPIO_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup GPIO_LL_Private_Macros
* @{
*/
#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
((__VALUE__) == LL_GPIO_MODE_ANALOG))
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
((__VALUE__) == LL_GPIO_PULL_UP) ||\
((__VALUE__) == LL_GPIO_PULL_DOWN))
#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
((__VALUE__) == LL_GPIO_AF_1 ) ||\
((__VALUE__) == LL_GPIO_AF_2 ) ||\
((__VALUE__) == LL_GPIO_AF_3 ) ||\
((__VALUE__) == LL_GPIO_AF_4 ) ||\
((__VALUE__) == LL_GPIO_AF_5 ) ||\
((__VALUE__) == LL_GPIO_AF_6 ) ||\
((__VALUE__) == LL_GPIO_AF_7 ) ||\
((__VALUE__) == LL_GPIO_AF_8 ) ||\
((__VALUE__) == LL_GPIO_AF_9 ) ||\
((__VALUE__) == LL_GPIO_AF_10 ) ||\
((__VALUE__) == LL_GPIO_AF_11 ) ||\
((__VALUE__) == LL_GPIO_AF_12 ) ||\
((__VALUE__) == LL_GPIO_AF_13 ) ||\
((__VALUE__) == LL_GPIO_AF_14 ) ||\
((__VALUE__) == LL_GPIO_AF_15 ))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_LL_Exported_Functions
* @{
*/
/** @addtogroup GPIO_LL_EF_Init
* @{
*/
/**
* @brief De-initialize GPIO registers (Registers restored to their default values).
* @param GPIOx GPIO Port
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are de-initialized
* - ERROR: Wrong GPIO Port
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Force and Release reset on clock of GPIOx Port */
if (GPIOx == GPIOA)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
}
else if (GPIOx == GPIOB)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
}
else if (GPIOx == GPIOC)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
}
#if defined(GPIOD)
else if (GPIOx == GPIOD)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
}
#endif /* GPIOD */
#if defined(GPIOE)
else if (GPIOx == GPIOE)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
}
#endif /* GPIOE */
#if defined(GPIOF)
else if (GPIOx == GPIOF)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
}
#endif /* GPIOF */
#if defined(GPIOG)
else if (GPIOx == GPIOG)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
}
#endif /* GPIOG */
#if defined(GPIOH)
else if (GPIOx == GPIOH)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
}
#endif /* GPIOH */
#if defined(GPIOI)
else if (GPIOx == GPIOI)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);
}
#endif /* GPIOI */
#if defined(GPIOJ)
else if (GPIOx == GPIOJ)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
}
#endif /* GPIOJ */
#if defined(GPIOK)
else if (GPIOx == GPIOK)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);
}
#endif /* GPIOK */
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
* @param GPIOx GPIO Port
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
* that contains the configuration information for the specified GPIO peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
* - ERROR: Not applicable
*/
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
uint32_t pinpos = 0x00000000U;
uint32_t currentpin = 0x00000000U;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
/* ------------------------- Configure the port pins ---------------- */
/* Initialize pinpos on first pin set */
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
/* Configure the port pins */
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
{
/* Get current io position */
currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
if (currentpin)
{
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Speed mode parameters */
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
}
/* Pull-up Pull down resistor configuration*/
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
{
/* Check Alternate parameter */
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
/* Speed mode configuration */
if (POSITION_VAL(currentpin) < 0x00000008U)
{
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
else
{
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
}
pinpos++;
}
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
}
return (SUCCESS);
}
/**
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f4xx_ll_gpio.c
* @author MCD Application Team
* @brief GPIO LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_gpio.h"
#include "stm32f4xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
/** @addtogroup GPIO_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup GPIO_LL_Private_Macros
* @{
*/
#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
((__VALUE__) == LL_GPIO_MODE_ANALOG))
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
((__VALUE__) == LL_GPIO_PULL_UP) ||\
((__VALUE__) == LL_GPIO_PULL_DOWN))
#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
((__VALUE__) == LL_GPIO_AF_1 ) ||\
((__VALUE__) == LL_GPIO_AF_2 ) ||\
((__VALUE__) == LL_GPIO_AF_3 ) ||\
((__VALUE__) == LL_GPIO_AF_4 ) ||\
((__VALUE__) == LL_GPIO_AF_5 ) ||\
((__VALUE__) == LL_GPIO_AF_6 ) ||\
((__VALUE__) == LL_GPIO_AF_7 ) ||\
((__VALUE__) == LL_GPIO_AF_8 ) ||\
((__VALUE__) == LL_GPIO_AF_9 ) ||\
((__VALUE__) == LL_GPIO_AF_10 ) ||\
((__VALUE__) == LL_GPIO_AF_11 ) ||\
((__VALUE__) == LL_GPIO_AF_12 ) ||\
((__VALUE__) == LL_GPIO_AF_13 ) ||\
((__VALUE__) == LL_GPIO_AF_14 ) ||\
((__VALUE__) == LL_GPIO_AF_15 ))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_LL_Exported_Functions
* @{
*/
/** @addtogroup GPIO_LL_EF_Init
* @{
*/
/**
* @brief De-initialize GPIO registers (Registers restored to their default values).
* @param GPIOx GPIO Port
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are de-initialized
* - ERROR: Wrong GPIO Port
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Force and Release reset on clock of GPIOx Port */
if (GPIOx == GPIOA)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
}
else if (GPIOx == GPIOB)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
}
else if (GPIOx == GPIOC)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
}
#if defined(GPIOD)
else if (GPIOx == GPIOD)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
}
#endif /* GPIOD */
#if defined(GPIOE)
else if (GPIOx == GPIOE)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
}
#endif /* GPIOE */
#if defined(GPIOF)
else if (GPIOx == GPIOF)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
}
#endif /* GPIOF */
#if defined(GPIOG)
else if (GPIOx == GPIOG)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
}
#endif /* GPIOG */
#if defined(GPIOH)
else if (GPIOx == GPIOH)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
}
#endif /* GPIOH */
#if defined(GPIOI)
else if (GPIOx == GPIOI)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);
}
#endif /* GPIOI */
#if defined(GPIOJ)
else if (GPIOx == GPIOJ)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
}
#endif /* GPIOJ */
#if defined(GPIOK)
else if (GPIOx == GPIOK)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);
}
#endif /* GPIOK */
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
* @param GPIOx GPIO Port
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
* that contains the configuration information for the specified GPIO peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
* - ERROR: Not applicable
*/
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
uint32_t pinpos = 0x00000000U;
uint32_t currentpin = 0x00000000U;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
/* ------------------------- Configure the port pins ---------------- */
/* Initialize pinpos on first pin set */
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
/* Configure the port pins */
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
{
/* Get current io position */
currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
if (currentpin)
{
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Speed mode parameters */
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
}
/* Pull-up Pull down resistor configuration*/
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
{
/* Check Alternate parameter */
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
/* Speed mode configuration */
if (POSITION_VAL(currentpin) < 0x00000008U)
{
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
else
{
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
return (SUCCESS);
}
/**
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

3340
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c
View file

File diff suppressed because it is too large Load diff

3069
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
View file

File diff suppressed because it is too large Load diff

1249
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c
View file

File diff suppressed because it is too large Load diff

1008
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c
View file

File diff suppressed because it is too large Load diff

4355
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c
View file

File diff suppressed because it is too large Load diff

1489
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c
View file

File diff suppressed because it is too large Load diff