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14 changed files with 398 additions and 399 deletions
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@ -1,5 +1,5 @@
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/*
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* ll_crchandler.cpp
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* ll_crc_handler.cpp
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*
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* Created on: Oct 26, 2019
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* Author: compi
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@ -8,151 +8,153 @@
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namespace f4ll {
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CrcHandler::CrcHandler(DMA_TypeDef *dma, uint32_t stream) : m_dma(dma, stream) {
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LL_DMA_EnableIT_TC(dma, stream);
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LL_DMA_EnableIT_TE(dma, stream);
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LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
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crc_handler::crc_handler(DMA_TypeDef *dma, uint32_t stream)
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: m_dma(dma, stream)
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{
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LL_DMA_EnableIT_TC(dma, stream);
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LL_DMA_EnableIT_TE(dma, stream);
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LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
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}
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void CrcHandler::AttachSlot(SlotBase &slot) {
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for (unsigned int i = 0; i < slot.m_taskCount; ++i) {
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auto &task(slot[i]);
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task.m_address = nullptr;
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task.m_wordCount = 0;
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task.m_callback = nullptr;
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task.m_callbackParam = 0;
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}
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uint32_t prim = __get_PRIMASK();
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__disable_irq();
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slot.m_next = m_firstSlot;
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m_firstSlot = &slot;
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__set_PRIMASK(prim);
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}
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bool CrcHandler::Enqueue(SlotBase &slot, uint8_t task, void const *address,
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uint16_t len, ICallback *cb, uintptr_t cbParam) {
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uint32_t prim = __get_PRIMASK();
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bool immediate;
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// TODO: do we need sanity check here? (is slot attached, is task in range,
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// etc...?)
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while (IsActive(slot, task))
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;
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__disable_irq();
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immediate = m_activeSlot == nullptr;
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slot[task].m_address = (!immediate) ? address : nullptr;
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slot[task].m_wordCount = (len + 3) / 4;
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slot[task].m_callback = cb;
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slot[task].m_callbackParam = cbParam;
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if (immediate) {
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m_activeSlot = &slot;
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m_activeTask = task;
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}
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__set_PRIMASK(prim);
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if (immediate) {
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CRC->CR = 1;
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LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(),
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(uint32_t)address);
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LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), (len + 3) / 4);
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LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
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}
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return immediate;
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}
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bool CrcHandler::IsActive(SlotBase &slot, uint8_t task) const {
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return task < slot.m_taskCount && slot[task].m_wordCount != 0;
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}
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bool CrcHandler::IsQueued(SlotBase &slot, uint8_t task) const {
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return task < slot.m_taskCount && slot[task].m_address != nullptr;
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}
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bool CrcHandler::IsRunning(SlotBase &slot, uint8_t task) const {
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return task < slot.m_taskCount && slot[task].m_wordCount &&
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!slot[task].m_address;
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}
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void CrcHandler::DmaTransferCompleted(void) {
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if (*m_dma.GetIsReg() & m_dma.GetTcMask()) { // DMA transfer complete
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*m_dma.GetIfcReg() = m_dma.GetTcMask();
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LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
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if (m_activeSlot) {
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if ((*m_activeSlot)[m_activeTask].m_callback)
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(*m_activeSlot)[m_activeTask].m_callback->CrcSucceeded(
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(*m_activeSlot)[m_activeTask].m_callbackParam, CRC->DR,
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m_activeTask);
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else if ((*m_activeSlot)[m_activeTask].m_callbackParam)
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*reinterpret_cast<uint32_t *>(
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(*m_activeSlot)[m_activeTask].m_callbackParam) = CRC->DR;
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void crc_handler::attach_slot(slot_base &slot)
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{
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for (unsigned int i = 0; i < slot.m_task_count; ++i) {
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auto &task(slot[i]);
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task.m_address = nullptr;
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task.m_word_count = 0;
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task.m_callback = nullptr;
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task.m_callback_param = 0;
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}
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} else if (*m_dma.GetIsReg() & m_dma.GetTeMask()) { // DMA transfer error
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*m_dma.GetIfcReg() = m_dma.GetTeMask();
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LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
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if (m_activeSlot) {
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if ((*m_activeSlot)[m_activeTask].m_callback)
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(*m_activeSlot)[m_activeTask].m_callback->CrcFailed(
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(*m_activeSlot)[m_activeTask].m_callbackParam, CRC->DR,
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m_activeTask);
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else if ((*m_activeSlot)[m_activeTask].m_callbackParam)
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*reinterpret_cast<uint32_t *>(
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(*m_activeSlot)[m_activeTask].m_callbackParam) = -1;
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}
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}
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(*m_activeSlot)[m_activeTask].m_callback = nullptr;
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(*m_activeSlot)[m_activeTask].m_callbackParam = 0;
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(*m_activeSlot)[m_activeTask].m_wordCount = 0;
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StartNextTask();
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uint32_t prim = __get_PRIMASK();
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__disable_irq();
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slot.m_next = m_first_slot;
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m_first_slot = &slot;
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__set_PRIMASK(prim);
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}
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void CrcHandler::StartNextTask(void) {
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bool moreTasks;
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uint8_t index = 0;
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bool crc_handler::enqueue(slot_base &slot, uint8_t task, void const *address, uint16_t len, icallback *cb, uintptr_t cbParam)
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{
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uint32_t prim = __get_PRIMASK();
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bool immediate;
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do {
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SlotBase volatile *slot = m_firstSlot;
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moreTasks = false;
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while (slot) {
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if (index < slot->m_taskCount) {
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if ((*slot)[index].m_address) {
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m_activeSlot = slot;
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m_activeTask = index;
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CRC->CR = 1;
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LL_DMA_SetM2MSrcAddress(
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m_dma.GetDma(), m_dma.GetStream(),
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reinterpret_cast<uint32_t>((*slot)[index].m_address));
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LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(),
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(*slot)[index].m_wordCount);
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LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
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(*slot)[index].m_address = nullptr; // marking as started
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return;
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// TODO: do we need sanity check here? (is slot attached, is task in range,
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// etc...?)
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while (is_active(slot, task))
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;
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__disable_irq();
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immediate = m_active_slot == nullptr;
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slot[task].m_address = (!immediate) ? address : nullptr;
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slot[task].m_word_count = (len + 3) / 4;
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slot[task].m_callback = cb;
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slot[task].m_callback_param = cbParam;
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if (immediate) {
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m_active_slot = &slot;
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m_activeTask = task;
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}
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__set_PRIMASK(prim);
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if (immediate) {
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CRC->CR = 1;
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LL_DMA_SetM2MSrcAddress(m_dma.get_dma(), m_dma.get_stream(), (uint32_t)address);
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LL_DMA_SetDataLength(m_dma.get_dma(), m_dma.get_stream(), (len + 3) / 4);
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LL_DMA_EnableStream(m_dma.get_dma(), m_dma.get_stream());
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}
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return immediate;
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}
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bool crc_handler::is_active(slot_base &slot, uint8_t task) const
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{
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return task < slot.m_task_count && slot[task].m_word_count != 0;
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}
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bool crc_handler::is_queued(slot_base &slot, uint8_t task) const
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{
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return task < slot.m_task_count && slot[task].m_address != nullptr;
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}
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bool crc_handler::is_running(slot_base &slot, uint8_t task) const
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{
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return task < slot.m_task_count && slot[task].m_word_count && !slot[task].m_address;
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}
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void crc_handler::dma_transfer_completed(void)
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{
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if (*m_dma.get_is_reg() & m_dma.get_tc_mask()) { // DMA transfer complete
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*m_dma.get_ifc_reg() = m_dma.get_tc_mask();
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LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream());
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if (m_active_slot) {
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if ((*m_active_slot)[m_activeTask].m_callback) {
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(*m_active_slot)[m_activeTask].m_callback->crc_succeeded(
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(*m_active_slot)[m_activeTask].m_callback_param, CRC->DR, m_activeTask);
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} else if ((*m_active_slot)[m_activeTask].m_callback_param) {
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*reinterpret_cast<uint32_t *>((*m_active_slot)[m_activeTask].m_callback_param) = CRC->DR;
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}
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}
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} else if (*m_dma.get_is_reg() & m_dma.get_te_mask()) { // DMA transfer error
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*m_dma.get_ifc_reg() = m_dma.get_te_mask();
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LL_DMA_DisableStream(m_dma.get_dma(), m_dma.get_stream());
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if (m_active_slot) {
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if ((*m_active_slot)[m_activeTask].m_callback) {
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(*m_active_slot)[m_activeTask].m_callback->crc_failed(
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(*m_active_slot)[m_activeTask].m_callback_param, CRC->DR, m_activeTask);
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} else if ((*m_active_slot)[m_activeTask].m_callback_param) {
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*reinterpret_cast<uint32_t *>((*m_active_slot)[m_activeTask].m_callback_param) = -1;
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}
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}
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if (index + 1 < slot->m_taskCount)
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moreTasks = true;
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}
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slot = slot->m_next;
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}
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++index;
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} while (moreTasks);
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m_activeSlot = nullptr;
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(*m_active_slot)[m_activeTask].m_callback = nullptr;
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(*m_active_slot)[m_activeTask].m_callback_param = 0;
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(*m_active_slot)[m_activeTask].m_word_count = 0;
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start_next_task();
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}
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void CrcHandler::WaitResults(SlotBase &slot, uint8_t task) const {
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while (IsQueued(slot, task))
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;
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while (IsActive(slot, task))
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;
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void crc_handler::start_next_task(void)
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{
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bool moreTasks;
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uint8_t index = 0;
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do {
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slot_base volatile *slot = m_first_slot;
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moreTasks = false;
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while (slot) {
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if (index < slot->m_task_count) {
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if ((*slot)[index].m_address) {
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m_active_slot = slot;
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m_activeTask = index;
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CRC->CR = 1;
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LL_DMA_SetM2MSrcAddress(m_dma.get_dma(), m_dma.get_stream(), reinterpret_cast<uint32_t>((*slot)[index].m_address));
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LL_DMA_SetDataLength(m_dma.get_dma(), m_dma.get_stream(), (*slot)[index].m_word_count);
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LL_DMA_EnableStream(m_dma.get_dma(), m_dma.get_stream());
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(*slot)[index].m_address = nullptr; // marking as started
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return;
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}
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if (index + 1 < slot->m_task_count) {
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moreTasks = true;
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}
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}
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slot = slot->m_next;
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}
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++index;
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} while (moreTasks);
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m_active_slot = nullptr;
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}
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uint32_t CrcHandler::Compute(SlotBase &slot, uint8_t task, void const *address,
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uint16_t len) {
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uint32_t result;
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Enqueue(slot, task, address, len, nullptr,
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reinterpret_cast<uintptr_t>(&result));
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while (IsActive(slot, task))
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;
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return result;
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void crc_handler::wait_results(slot_base &slot, uint8_t task) const
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{
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while (is_queued(slot, task))
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;
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while (is_active(slot, task))
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;
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}
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uint32_t crc_handler::compute(slot_base &slot, uint8_t task, void const *address, uint16_t len)
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{
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uint32_t result;
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enqueue(slot, task, address, len, nullptr, reinterpret_cast<uintptr_t>(&result));
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while (is_active(slot, task))
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;
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return result;
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}
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} // namespace f4ll
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