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This commit is contained in:
Attila Body 2025-06-08 18:41:07 +02:00
parent 3253c9413e
commit a4e25d702b
Signed by: abody
GPG key ID: BD0C6214E68FB5CF
14 changed files with 398 additions and 399 deletions
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14
components/app/src/application.cpp
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@ -6,14 +6,14 @@
*/
#ifdef USE_CPLUSPLUS
#include <string.h>
#include <stdlib.h>
#include "f4ll/packetusart.h"
#include "f4ll/crchandler.h"
#include "f4ll/memcpydma.h"
#include "f4ll/consolehandler.h"
#include "f4ll/crc_handler.h"
#include "f4ll/irqlock.h"
#include "f4ll/memcpydma.h"
#include "f4ll/packetusart.h"
#include "f4ll/strutil.h"
#include <stdlib.h>
#include <string.h>
extern "C" {
#include "main.h"
@ -38,8 +38,8 @@ extern "C" void MainLoop()
f4ll::MemcpyDma::Init(MEMCPY_DMA_ENGINE, MEMCPY_DMA_STREAM);
f4ll::CrcHandler::Init(DMA2, LL_DMA_STREAM_4);
f4ll::ConsoleHandler::Init(UART4, CONSOLE_DMA_ENGINE, 0u, CONSOLE_TX_DMA_STREAM);
f4ll::crc_handler::Init(DMA2, LL_DMA_STREAM_4);
f4ll::ConsoleHandler::Init(UART4, CONSOLE_DMA_ENGINE, 0u, CONSOLE_TX_DMA_STREAM);
f4ll::PacketUsart u1{ USART1, DMA2, LL_DMA_STREAM_2, LL_DMA_STREAM_7 };
f4ll::PacketUsart u2{ USART2, DMA1, LL_DMA_STREAM_5, LL_DMA_STREAM_6 };

43
components/app/src/irq_bridge.cpp
View file

@ -1,4 +1,6 @@
#include "f4ll/console_handler.h"
#include <f4ll/console_handler.h>
#include <f4ll/crc_handler.h>
#include <f4ll/memcpy_dma.h>
#include <config.h>
#include <globals.h>
@ -6,73 +8,80 @@
void usart1_rx_dma_isr(void)
{
f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART1_OFFSET]);
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART1_OFFSET]);
}
void usart1_tx_dma_isr(void)
{
f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART1_OFFSET]);
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART1_OFFSET]);
}
void usart1_isr(void)
{
f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART1_OFFSET]);
f4ll::PacketUsart::usart_isr(g_usarts[USART1_OFFSET]);
}
//
void usart2_rx_dma_isr(void)
{
f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART2_OFFSET]);
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART2_OFFSET]);
}
void usart2_tx_dma_isr(void)
{
f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART2_OFFSET]);
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART2_OFFSET]);
}
void usart2_isr(void)
{
f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART2_OFFSET]);
f4ll::PacketUsart::usart_isr(g_usarts[USART2_OFFSET]);
}
//
void usart3_rx_dma_isr(void)
{
f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART3_OFFSET]);
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART3_OFFSET]);
}
void usart3_tx_dma_isr(void)
{
f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART3_OFFSET]);
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART3_OFFSET]);
}
void usart3_isr(void)
{
f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART3_OFFSET]);
f4ll::PacketUsart::usart_isr(g_usarts[USART3_OFFSET]);
}
//
void usart4_rx_dma_isr(void) {} // console
void usart4_tx_dma_isr(void)
{
f4ll::console_handler::HandleTxDmaIrq(&f4ll::console_handler::instance());
f4ll::console_handler::tx_dma_isr(&f4ll::console_handler::instance());
} // console
void usart4_isr(void)
{
f4ll::console_handler::HandleUsartIrq(&f4ll::console_handler::instance());
f4ll::console_handler::usart_isr(&f4ll::console_handler::instance());
}
//
void usart6_rx_dma_isr(void)
{
f4ll::PacketUsart::HandleRxDmaIrq(g_usarts[USART6_OFFSET]);
f4ll::PacketUsart::rx_dma_isr(g_usarts[USART6_OFFSET]);
}
void usart6_tx_dma_isr(void)
{
f4ll::PacketUsart::HandleTxDmaIrq(g_usarts[USART6_OFFSET]);
f4ll::PacketUsart::tx_dma_isr(g_usarts[USART6_OFFSET]);
}
void usart6_isr(void)
{
f4ll::PacketUsart::HandleUsartIrq(g_usarts[USART6_OFFSET]);
f4ll::PacketUsart::usart_isr(g_usarts[USART6_OFFSET]);
}
void m2m1_dma_isr(void) {} // m2mcpy
void m2m2_dma_isr(void) {} // crc
void m2m1_dma_isr(void)
{
f4ll::memcpy_dma::instance().dma_transfer_completed();
} // m2mcpy
void m2m2_dma_isr(void)
{
f4ll::crc_handler::instance().dma_transfer_completed();
} // crc