playground-stm32/f407ve_hs_uart
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Convert the project to CMake

Browse source 
f4ll revamp
This commit is contained in:
Attila Body 2025-06-08 23:15:46 +02:00
parent bc01b1f0e8
commit 97437d1361
Signed by: abody
GPG key ID: BD0C6214E68FB5CF
243 changed files with 159825 additions and 189335 deletions
Download patch file Download diff file Expand all files Collapse all files

45
components/f4ll/inc/consolehandler.h
View file

@ -1,45 +0,0 @@
/*
* ll_consolehandler.h
*
* Created on: Nov 7, 2019
* Author: abody
*/
#ifndef LL_CONSOLEHANDLER_H_
#define LL_CONSOLEHANDLER_H_
#include "f4ll/packetusart.h"
#include "singleton.h"
namespace f4ll {
class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
{
friend class Singleton<ConsoleHandler>;
public:
void PrintStats(uint8_t id, PacketUsart &usart);
private:
ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
// LL_UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void FramingError(void);
virtual void Overrun(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
char m_buffer[128];
uint16_t m_used = 0;
};
} /* namespace f4ll */
#endif /* LL_CONSOLEHANDLER_H_ */

89
components/f4ll/inc/crchandler.h
View file

@ -1,89 +0,0 @@
/*
* ll_crchandler.h
*
* Created on: Oct 26, 2019
* Author: compi
*/
#ifndef LL_CRCHANDLER_H_
#define LL_CRCHANDLER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
#include "f4ll/dmahelper.h"
#include "singleton.h"
extern "C" void _HandleCrcDmaIrq(void);
namespace f4ll {
class CrcHandler : public Singleton<CrcHandler>
{
friend class Singleton<CrcHandler>;
public:
struct ICallback
{
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
};
class SlotBase
{
friend class CrcHandler;
public:
struct CrcTask {
void const * m_address; // changed to nullptr when execution starts
uint16_t m_wordCount;
ICallback *m_callback;
uintptr_t m_callbackParam;
};
private:
SlotBase volatile *m_next = nullptr;
uint8_t m_taskCount;
virtual CrcTask volatile & operator[](int index) volatile = 0;
protected:
SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
SlotBase() = delete;
SlotBase(SlotBase const &other) = delete;
};
template <uint8_t n> class Slot : public SlotBase
{
public:
Slot() : SlotBase(n) {}
virtual CrcTask volatile & operator[](int index) volatile { return m_tasks[index]; }
private:
Slot::CrcTask m_tasks[n];
};
void AttachSlot(SlotBase &slot);
bool Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam);
uint32_t Compute(SlotBase &slot, uint8_t task, void const *address, uint16_t len);
bool IsActive(SlotBase &slot, uint8_t task) const;
bool IsQueued(SlotBase &slot, uint8_t task) const;
bool IsRunning(SlotBase &slot, uint8_t task) const;
void DmaTransferCompleted(void);
private:
CrcHandler(DMA_TypeDef *dma, uint32_t stream);
friend void ::_HandleCrcDmaIrq(void);
void StartNextTask(void);
void WaitResults(SlotBase &slot, uint8_t task) const;
DmaHelper m_dma;
SlotBase volatile *m_firstSlot = nullptr;
SlotBase volatile *m_activeSlot = nullptr;
int volatile m_activeTask;
};
} // namespace f4ll
#endif /* LL_CRCHANDLER_H_ */

58
components/f4ll/inc/dmahelper.h
View file

@ -1,58 +0,0 @@
/*
* ll_dmahelper.h
*
* Created on: Oct 25, 2019
* Author: abody
*/
#ifndef LL_DMAHELPER_H_
#define LL_DMAHELPER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
namespace f4ll {
class DmaHelper {
public:
DmaHelper(DMA_TypeDef *dma, uint32_t stream);
DmaHelper(DmaHelper const &base) = default;
inline DMA_TypeDef* GetDma() const { return m_dma; }
inline uint32_t GetStream() const { return m_stream; }
inline volatile uint32_t* GetIsReg() const { return m_isReg; }
inline volatile uint32_t* GetIfcReg() const { return m_ifcReg; }
inline uint32_t GetFeMask() const { return m_FEMasks[m_stream]; }
inline uint32_t GetDmeMask() const { return m_DMEMasks[m_stream]; }
inline uint32_t GetTeMask() const { return m_TEMasks[m_stream]; }
inline uint32_t GetHtMask() const { return m_HTMasks[m_stream]; }
inline uint32_t GetTcMask() const { return m_TCMasks[m_stream]; }
inline bool IsEnabledIt_HT() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_TE() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_TC() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_DME() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_FE() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
enum class DmaErrorType {
Transfer,
DirectMode,
Fifo
};
private:
DMA_TypeDef *m_dma;
uint32_t m_stream;
volatile uint32_t *m_isReg;
volatile uint32_t *m_ifcReg;
static const uint32_t m_FEMasks[8];
static const uint32_t m_DMEMasks[8];
static const uint32_t m_TEMasks[8];
static const uint32_t m_HTMasks[8];
static const uint32_t m_TCMasks[8];
};
} /* namespace f4ll */
#endif /* LL_DMAHELPER_H_ */

1
components/f4ll/inc/f4ll
View file

@ -1 +0,0 @@
.

44
components/f4ll/inc/f4ll/console_handler.h Normal file
View file

@ -0,0 +1,44 @@
/*
* ll_consolehandler.h
*
* Created on: Nov 7, 2019
* Author: abody
*/
#ifndef LL_CONSOLEHANDLER_H_
#define LL_CONSOLEHANDLER_H_
#include <f4ll/packet_usart.h>
#include <f4ll/singleton.h>
namespace f4ll {
class console_handler : public usart_core, public singleton<console_handler>
{
friend class singleton<console_handler>;
public:
void PrintStats(uint8_t id, packet_usart &usart);
private:
console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
// LL_UsartCore pure virtual function implementations
virtual void receiver_idle(void) override;
virtual void transmission_complete(void) override;
virtual void framing_error(void) override;
virtual void overrun(void) override;
virtual void rx_dma_transfer_complete(void) override;
virtual void rx_dma_half_transfer(void) override;
virtual void rx_dma_error(dma_helper::dma_error_type reason) override;
virtual void tx_dma_transfer_complete(void) override;
virtual void tx_dma_half_transfer(void) override;
virtual void tx_dma_error(dma_helper::dma_error_type reason) override;
char m_buffer[128];
uint16_t m_used = 0;
};
} /* namespace f4ll */
#endif /* LL_CONSOLEHANDLER_H_ */

90
components/f4ll/inc/f4ll/crc_handler.h Normal file
View file

@ -0,0 +1,90 @@
/*
* ll_crc_handler.h
*
* Created on: Oct 26, 2019
* Author: compi
*/
#pragma once
#include <f4ll/dma_helper.h>
#include <f4ll/singleton.h>
#include <inttypes.h>
#include <platform/dma_ll.h>
namespace f4ll {
class crc_handler : public singleton<crc_handler>
{
friend class singleton<crc_handler>;
public:
struct icallback
{
virtual void crc_succeeded(uintptr_t callback_param, uint32_t crc, uint8_t task) = 0;
virtual void crc_failed(uintptr_t callback_param, uint32_t crc, uint8_t task) = 0;
};
class slot_base
{
friend class crc_handler;
public:
struct crc_task
{
void const *m_address; // changed to nullptr when execution starts
uint16_t m_word_count;
icallback *m_callback;
uintptr_t m_callback_param;
};
private:
slot_base volatile *m_next = nullptr;
uint8_t m_task_count;
virtual crc_task volatile &operator[](int index) volatile = 0;
protected:
slot_base(unsigned int task_count)
: m_task_count(task_count)
{
}
slot_base() = delete;
slot_base(slot_base const &other) = delete;
};
template <uint8_t n> class slot : public slot_base
{
public:
slot()
: slot_base(n)
{
}
virtual crc_task volatile &operator[](int index) volatile { return m_tasks[index]; }
private:
slot::crc_task m_tasks[n];
};
void attach_slot(slot_base &slot);
bool enqueue(slot_base &slot, uint8_t task, void const *address, uint16_t len, icallback *cb, uintptr_t cb_param);
uint32_t compute(slot_base &slot, uint8_t task, void const *address, uint16_t len);
bool is_active(slot_base &slot, uint8_t task) const;
bool is_queued(slot_base &slot, uint8_t task) const;
bool is_running(slot_base &slot, uint8_t task) const;
void dma_transfer_completed(void);
private:
crc_handler(DMA_TypeDef *dma, uint32_t stream);
void start_next_task(void);
void wait_results(slot_base &slot, uint8_t task) const;
dma_helper m_dma;
slot_base volatile *m_first_slot = nullptr;
slot_base volatile *m_active_slot = nullptr;
int volatile m_active_task;
};
} // namespace f4ll

60
components/f4ll/inc/f4ll/dma_helper.h Normal file
View file

@ -0,0 +1,60 @@
/*
* ll_dmahelper.h
*
* Created on: Oct 25, 2019
* Author: abody
*/
#ifndef LL_DMAHELPER_H_
#define LL_DMAHELPER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
namespace f4ll {
class dma_helper
{
public:
dma_helper(DMA_TypeDef *dma, uint32_t stream);
dma_helper(dma_helper const &base) = default;
inline DMA_TypeDef *get_dma() const { return m_dma; }
inline uint32_t get_stream() const { return m_stream; }
inline volatile uint32_t *get_is_reg() const { return m_is_reg; }
inline volatile uint32_t *get_ifc_reg() const { return m_ifc_reg; }
inline uint32_t get_fe_mask() const { return m_fe_masks[m_stream]; }
inline uint32_t get_dme_mask() const { return m_dme_masks[m_stream]; }
inline uint32_t get_te_mask() const { return m_te_masks[m_stream]; }
inline uint32_t get_ht_mask() const { return m_ht_masks[m_stream]; }
inline uint32_t get_tc_mask() const { return m_tc_masks[m_stream]; }
inline bool is_enabled_it_ht() const { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
inline bool is_enabled_it_te() const { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
inline bool is_enabled_it_tc() const { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
inline bool is_enabled_it_dme() const { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
inline bool is_enabled_it_fe() const { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
enum class dma_error_type { transfer, direct_mode, fifo };
private:
DMA_TypeDef *m_dma;
uint32_t m_stream;
volatile uint32_t *m_is_reg;
volatile uint32_t *m_ifc_reg;
static constexpr uint32_t const m_fe_masks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3,
DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
static constexpr uint32_t const m_dme_masks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3,
DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
static constexpr uint32_t const m_te_masks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3,
DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
static constexpr uint32_t const m_ht_masks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3,
DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
static constexpr uint32_t const m_tc_masks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3,
DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
};
} /* namespace f4ll */
#endif /* LL_DMAHELPER_H_ */

47
components/f4ll/inc/f4ll/fault.h Normal file
View file

@ -0,0 +1,47 @@
#ifndef __FAULT_H
#define __FAULT_H
#define FAULT_REASON_HARD_FAULT 1
#define FAULT_REASON_MEMMANAGE_FAULT 2
#define FAULT_REASON_BUS_FAULT 3
#define FAULT_REASON_USAGE_FAULT 4
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
uint32_t R0;
uint32_t R1;
uint32_t R2;
uint32_t R3;
uint32_t R4;
uint32_t R5;
uint32_t R6;
uint32_t R7;
uint32_t R8;
uint32_t R9;
uint32_t R10;
uint32_t R11;
uint32_t R12;
uint32_t SP;
uint32_t LR;
uint32_t PC;
uint32_t xPSR;
uint32_t PSP;
uint32_t MSP;
uint32_t EXC_RETURN;
uint32_t CONTROL;
} fault_context_t;
extern fault_context_t g_fault_context;
void app_fault_callback(uint32_t reason);
__attribute__((noreturn)) void fault_handler(uint32_t type, fault_context_t *context);
#ifdef __cplusplus
}
#endif
#endif /* __FAULT_H */

26
components/f4ll/inc/f4ll/irq_lock.h Normal file
View file

@ -0,0 +1,26 @@
#ifndef _IRQLOCK_H_INCLUDED
#define _IRQLOCK_H_INCLUDED
#include <inttypes.h>
#include <stm32f4xx.h>
namespace f4ll {
class irq_lock
{
public:
inline irq_lock()
: m_primask(__get_PRIMASK())
{
__disable_irq();
}
inline void release() { __set_PRIMASK(m_primask); }
inline ~irq_lock() { __set_PRIMASK(m_primask); }
private:
uint32_t m_primask;
};
}
#endif // _IRQLOCK_H_INCLUDED

27
components/f4ll/inc/f4ll/memcpy_dma.h Normal file
View file

@ -0,0 +1,27 @@
/*
* llmemcpydma.h
*
* Created on: Nov 4, 2019
* Author: abody
*/
#pragma once
#include <f4ll/dma_helper.h>
#include <f4ll/singleton.h>
namespace f4ll {
class memcpy_dma : public singleton<memcpy_dma>, private dma_helper
{
friend class singleton<memcpy_dma>;
public:
void *copy(void *dst, void const *src, uint16_t length);
void dma_transfer_completed();
private:
memcpy_dma(DMA_TypeDef *dma, uint32_t stream);
bool volatile m_busy = false;
};
} /* namespace f4ll */

122
components/f4ll/inc/f4ll/packet_usart.h Normal file
View file

@ -0,0 +1,122 @@
/*
* ll_HsUsart.h
*
* Created on: Oct 29, 2019
* Author: abody
*/
#ifndef LL_HSUSART_H_
#define LL_HSUSART_H_
#include <f4ll/crc_handler.h>
#include <f4ll/usart_core.h>
#include <platform/usart_ll.h>
namespace f4ll {
struct DMAINFO;
class packet_usart : public crc_handler::icallback, public usart_core
{
// friend class UsartCore;
public:
packet_usart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
struct packet_header
{ // !!! size should be multiple of 4 !!!
uint8_t start_byte;
uint8_t serial;
uint8_t payload_length;
uint8_t hash;
};
struct packet
{
packet_header header;
uint8_t payload[256 + sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned));
struct stats
{
uint32_t overrun = 0;
uint32_t hdr_error = 0;
uint32_t payload_errror = 0;
uint32_t pep1 = 0;
uint32_t pep2 = 0;
uint32_t rx_dma_error = 0;
uint32_t tx_dma_error = 0;
uint32_t rcvd = 0;
uint32_t premature_hdr = 0;
uint32_t premature_payload = 0;
uint32_t sent = 0;
uint32_t skiped = 0;
};
struct ihs_usart_callback
{
virtual bool packet_received(packet_usart *caller, uintptr_t user_param, packet const &packet) = 0;
};
// crc_handler::ICallback interface functions
virtual void crc_succeeded(uintptr_t callback_param, uint32_t crc, uint8_t task) override;
virtual void crc_failed(uintptr_t callback_param, uint32_t crc, uint8_t task) override;
void post_packet(uint8_t const *payload, uint8_t length, bool wait_for_crc_queue = true);
void setup_receive(void);
void rx_processed(bool second);
// Getters
uint8_t *get_tx_packet_buffer(void) { return m_tx_buffer.pkt.payload; }
uint8_t const *get_rx_packet_buffer(bool second) { return m_rx_buffers[second].pkt.payload; }
USART_TypeDef *get_usart(void) const { return m_usart; }
stats const &get_stats(void) const { return m_stats; }
inline bool is_tx_busy(void) const { return m_tx_buffer.busy; }
inline bool is_tx_failed(void) const { return m_tx_buffer.error; }
inline bool is_rx_busy(bool second) const { return m_rx_buffers[second].busy; }
inline bool is_rx_failed(bool second) const { return m_rx_buffers[second].error; }
void set_callback(ihs_usart_callback *callback, uintptr_t callback_param);
private:
void build_header(packet &packet, uint8_t serial_nr, uint8_t length);
bool check_header(packet_header &header);
void switch_rx_buffers(void);
// UsartCore pure virtual function implementations
virtual void receiver_idle(void) override;
virtual void transmission_complete(void) override;
virtual void framing_error(void) override;
virtual void overrun(void) override;
virtual void rx_dma_transfer_complete(void) override;
virtual void rx_dma_half_transfer(void) override;
virtual void rx_dma_error(dma_helper::dma_error_type reason) override;
virtual void tx_dma_transfer_complete(void) override;
virtual void tx_dma_half_transfer(void) override;
virtual void tx_dma_error(dma_helper::dma_error_type reason) override;
struct Buffer
{
packet pkt;
// transfer area ends here
bool volatile busy = 0;
bool volatile error = 0;
uint16_t requested_length = 0;
uint32_t error_info = 0;
};
static const uint8_t STARTMARKER = 0x95;
uint8_t m_rx_serial_nr = -1;
uint8_t m_tx_serial_nr = -1;
stats m_stats;
bool m_rx_buffer_selector = false;
crc_handler::slot<2> m_crc_slot;
ihs_usart_callback *m_user_callback = nullptr;
uintptr_t m_user_callback_param = 0;
Buffer m_tx_buffer;
Buffer m_rx_buffers[2];
};
}
#endif /* LL_HSUSART_H_ */

33
components/f4ll/inc/f4ll/singleton.h Normal file
View file

@ -0,0 +1,33 @@
#ifndef SINGLETON_H_
#define SINGLETON_H_
#include <utility>
namespace f4ll {
template <typename T> class singleton
{
public:
static T &instance()
{
return *m_instance;
}
template <typename... args_t> static T &init(args_t &&...args)
{
static T instance{std::forward<args_t>(args)...};
m_instance = &instance;
return instance;
}
protected:
singleton() = default;
singleton(const singleton &) = delete;
singleton &operator=(const singleton &) = delete;
static T *m_instance;
};
template <typename T> T *singleton<T>::m_instance = nullptr;
} // namespace f1ll {
#endif /* SINGLETON_H_ */

0
components/f4ll/inc/strutil.h → components/f4ll/inc/f4ll/str_util.h
View file

54
components/f4ll/inc/f4ll/usart_core.h Normal file
View file

@ -0,0 +1,54 @@
/*
* ll_dmadrivenusartcore.h
*
* Created on: Nov 4, 2019
* Author: abody
*/
#ifndef LL_USARTCORE_H_
#define LL_USARTCORE_H_
#include <platform/usart_ll.h>
#include <f4ll/dma_helper.h>
namespace f4ll {
class usart_core
{
public:
static inline void usart_isr(usart_core *_this) { _this->usart_isr(); }
static inline void rx_dma_isr(usart_core *_this) { _this->rx_dma_isr(); }
static inline void tx_dma_isr(usart_core *_this) { _this->tx_dma_isr(); }
void setup_transmit(void const *buffer, uint16_t length);
void setup_receive(void *buffer, uint16_t length);
protected:
usart_core(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
USART_TypeDef *m_usart;
dma_helper m_rx_dma;
dma_helper m_tx_dma;
private:
virtual void receiver_idle(void) = 0;
virtual void transmission_complete(void) = 0;
virtual void framing_error(void) = 0;
virtual void overrun(void) = 0;
virtual void rx_dma_transfer_complete(void) = 0;
virtual void rx_dma_half_transfer(void) = 0;
virtual void rx_dma_error(dma_helper::dma_error_type reason) = 0;
virtual void tx_dma_transfer_complete(void) = 0;
virtual void tx_dma_half_transfer(void) = 0;
virtual void tx_dma_error(dma_helper::dma_error_type reason) = 0;
void usart_isr();
void rx_dma_isr();
void tx_dma_isr();
};
} /* namespace f4ll */
#endif /* LL_USARTCORE_H_ */

19
components/f4ll/inc/fault.h
View file

@ -1,19 +0,0 @@
#ifndef __FAULT_H
#define __FAULT_H
#define FAULT_REASON_HARD_FAULT 1
#define FAULT_REASON_MEMMANAGE_FAULT 2
#define FAULT_REASON_BUS_FAULT 3
#define FAULT_REASON_USAGE_FAULT 4
#ifdef __cplusplus
extern "C" {
#endif
void app_fault_callback(uint32_t reason);
#ifdef __cplusplus
}
#endif
#endif /* __FAULT_H */

27
components/f4ll/inc/irqlock.h
View file

@ -1,27 +0,0 @@
#ifndef _IRQLOCK_H_INCLUDED
#define _IRQLOCK_H_INCLUDED
#include <inttypes.h>
#include <stm32f4xx.h>
namespace f4ll {
class IrqLock {
public:
inline IrqLock() : m_primask(__get_PRIMASK()) {
__disable_irq();
}
inline void Release() {
__set_PRIMASK(m_primask);
}
inline ~IrqLock() {
__set_PRIMASK(m_primask);
}
private:
uint32_t m_primask;
};
}
#endif // _IRQLOCK_H_INCLUDED

28
components/f4ll/inc/memcpydma.h
View file

@ -1,28 +0,0 @@
/*
* llmemcpydma.h
*
* Created on: Nov 4, 2019
* Author: abody
*/
#ifndef LL_MEMCPY_DMA_H_
#define LL_MEMCPY_DMA_H_
#include "f4ll/dmahelper.h"
#include "singleton.h"
namespace f4ll {
class MemcpyDma : public Singleton<MemcpyDma>, private DmaHelper
{
friend class Singleton<MemcpyDma>;
public:
void* Copy(void *dst, void const *src, uint16_t length);
void DmaTransferCompleted();
private:
MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
bool volatile m_busy = false;
};
} /* namespace f4ll */
#endif /* LL_MEMCPY_DMA_H_ */

117
components/f4ll/inc/packetusart.h
View file

@ -1,117 +0,0 @@
/*
* ll_HsUsart.h
*
* Created on: Oct 29, 2019
* Author: abody
*/
#ifndef LL_HSUSART_H_
#define LL_HSUSART_H_
#include <platform/usart_ll.h>
#include "f4ll/usartcore.h"
#include "f4ll/crchandler.h"
namespace f4ll {
struct DMAINFO;
class PacketUsart : public CrcHandler::ICallback, public UsartCore
{
// friend class UsartCore;
public:
PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
struct PacketHeader { // !!! size should be multiple of 4 !!!
uint8_t startByte;
uint8_t serial;
uint8_t payloadLength;
uint8_t hash;
};
struct Packet {
PacketHeader header;
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned));
struct Stats {
uint32_t overrun = 0;
uint32_t hdrError = 0;
uint32_t payloadErrror = 0;
uint32_t pep1 = 0;
uint32_t pep2 = 0;
uint32_t rxDmaError = 0;
uint32_t txDmaError = 0;
uint32_t rcvd = 0;
uint32_t premature_hdr = 0;
uint32_t premature_payload = 0;
uint32_t sent = 0;
uint32_t skiped = 0;
};
struct IHsUsartCallback {
virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
};
// CRCHandler::ICallback interface functions
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
void SetupReceive(void);
void RxProcessed(bool second);
// Getters
uint8_t* GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
uint8_t const * GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
USART_TypeDef* GetUsart(void) const { return m_usart; }
Stats const & GetStats(void) const { return m_stats; }
inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
inline bool IsTxFailed(void) const { return m_txBuffer.error; }
inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
private:
void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
bool CheckHeader(PacketHeader &header);
void SwitchRxBuffers(void);
// UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void FramingError(void);
virtual void Overrun(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
struct Buffer {
Packet packet;
//transfer area ends here
bool volatile busy = 0;
bool volatile error = 0;
uint16_t requestedLength = 0;
uint32_t errorInfo = 0;
};
static const uint8_t STARTMARKER = 0x95;
uint8_t m_rxSerialNo = -1;
uint8_t m_txSerialNo = -1;
Stats m_stats;
bool m_rxBufferSelector = false;
CrcHandler::Slot<2> m_crcSlot;
IHsUsartCallback *m_userCallback = nullptr;
uintptr_t m_userCallbackParam = 0;
Buffer m_txBuffer;
Buffer m_rxBuffers[2];
};
}
#endif /* LL_HSUSART_H_ */

55
components/f4ll/inc/usartcore.h
View file

@ -1,55 +0,0 @@
/*
* ll_dmadrivenusartcore.h
*
* Created on: Nov 4, 2019
* Author: abody
*/
#ifndef LL_USARTCORE_H_
#define LL_USARTCORE_H_
#include <platform/usart_ll.h>
#include "f4ll/dmahelper.h"
namespace f4ll {
class UsartCore
{
public:
static inline void HandleUsartIrq(UsartCore *_this) { _this->UsartIsr(); }
static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
void SetupTransmit(void const *buffer, uint16_t length);
void SetupReceive(void *buffer, uint16_t length);
protected:
UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
USART_TypeDef *m_usart;
DmaHelper m_rxDma;
DmaHelper m_txDma;
private:
virtual void ReceiverIdle(void) = 0;
virtual void TransmissionComplete(void) = 0;
virtual void FramingError(void) = 0;
virtual void Overrun(void) = 0;
virtual void RxDmaTransferComplete(void) = 0;
virtual void RxDmaHalfTransfer(void) = 0;
virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
virtual void TxDmaTransferComplete(void) = 0;
virtual void TxDmaHalfTransfer(void) = 0;
virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
void UsartIsr();
void RxDmaIsr();
void TxDmaIsr();
};
} /* namespace f4ll */
#endif /* LL_USARTCORE_H_ */