WIP - ready to debug

2019-10-31 14:01:38 +01:00 · 2019-10-31 14:01:38 +01:00 · 9670e6d397
commit 9670e6d397
parent 663d68baf1
14 changed files with 893 additions and 52 deletions
--- a/lib/ll_crchandler.cpp
+++ b/lib/ll_crchandler.cpp
@ -0,0 +1,156 @@
+/*
+ * ll_crchandler.cpp
+ *
+ *  Created on: Oct 26, 2019
+ *      Author: compi
+ */
+#include "ll_crchandler.h"
+
+namespace f4ll {
+
+LL_CrcHandler::LL_CrcHandler(DMA_TypeDef *dma, uint32_t stream)
+: m_dma(dma, stream)
+{
+	LL_DMA_EnableIT_TC(dma, stream);
+	LL_DMA_EnableIT_TE(dma, stream);
+	LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
+}
+
+
+void LL_CrcHandler::AttachSlot(Slot &slot)
+{
+	for(unsigned int i = 0; i < slot.m_taskCount; ++i ) {
+		auto &task(slot.m_tasks[i]);
+		task.m_address = nullptr;
+		task.m_wordCount = 0;
+		task.m_callback = nullptr;
+		task.m_callbackParam = 0;
+	}
+	slot.m_next = m_firstSlot;
+	uint32_t prim = __get_PRIMASK();
+	__disable_irq();
+	m_firstSlot = &slot;
+	__set_PRIMASK(prim);
+}
+
+
+bool LL_CrcHandler::Enqueue(Slot &slot, uint8_t prio, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam)
+{
+	uint32_t prim = __get_PRIMASK();
+	bool immediate;
+
+	// TODO: do we need sanity check here? (is slot attached, is prio in range, etc...?)
+
+	while(IsActive(slot,prio));
+	__disable_irq();
+	immediate = m_activeSlot == nullptr;
+	slot.m_tasks[prio].m_address = (!immediate) ? address : nullptr;
+	slot.m_tasks[prio].m_wordCount = (len+3)/4;
+	slot.m_tasks[prio].m_callback = cb;
+	slot.m_tasks[prio].m_callbackParam = cbParam;
+	if(immediate) {
+		m_activeSlot = &slot;
+		m_activePrio = prio;
+	}
+	__set_PRIMASK(prim);
+
+	if(immediate) {
+		CRC->CR = 1;
+		LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(), (uint32_t)address);
+		LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), (len+3)/4);
+		LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
+	}
+	return immediate;
+}
+
+bool LL_CrcHandler::IsActive(Slot &slot, uint8_t prio) const
+{
+	return prio < slot.m_taskCount && slot.m_tasks[prio].m_wordCount != 0;
+}
+
+bool LL_CrcHandler::IsQueued(Slot &slot, uint8_t prio) const
+{
+	return prio < slot.m_taskCount && slot.m_tasks[prio].m_address != nullptr;
+}
+
+bool LL_CrcHandler::IsRunning(Slot &slot, uint8_t prio) const
+{
+	return prio < slot.m_taskCount && slot.m_tasks[prio].m_wordCount && ! slot.m_tasks[prio].m_address;
+}
+
+void LL_CrcHandler::DmaTransferCompleted(void)
+{
+	if(* m_dma.GetIsReg() & m_dma.GetTcMask()) {	// DMA transfer complete
+		* m_dma.GetIcfReg() = m_dma.GetTcMask();
+		LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
+		if(m_activeSlot) {
+			if(m_activeSlot->m_tasks[m_activePrio].m_callback)
+				m_activeSlot->m_tasks[m_activePrio].m_callback->CrcSucceeded(m_activeSlot->m_tasks[m_activePrio].m_callbackParam, CRC->DR, m_activePrio);
+			else if(m_activeSlot->m_tasks[m_activePrio].m_callbackParam)
+				*reinterpret_cast<uint32_t*>(m_activeSlot->m_tasks[m_activePrio].m_callbackParam) = CRC->DR;
+		}
+	}
+	else if(*m_dma.GetIsReg() & m_dma.GetTeMask()) {	// DMA transfer error
+		*m_dma.GetIcfReg() = m_dma.GetTeMask();
+		LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
+		if(m_activeSlot) {
+			if(m_activeSlot->m_tasks[m_activePrio].m_callback)
+				m_activeSlot->m_tasks[m_activePrio].m_callback->CrcFailed(m_activeSlot->m_tasks[m_activePrio].m_callbackParam, CRC->DR, m_activePrio);
+			else if(m_activeSlot->m_tasks[m_activePrio].m_callbackParam)
+				*reinterpret_cast<uint32_t*>(m_activeSlot->m_tasks[m_activePrio].m_callbackParam) = -1;
+		}
+	}
+	m_activeSlot->m_tasks[m_activePrio].m_callback = nullptr;
+	m_activeSlot->m_tasks[m_activePrio].m_callbackParam = 0;
+	m_activeSlot->m_tasks[m_activePrio].m_wordCount = 0;
+	StartNextTask();
+}
+
+
+void LL_CrcHandler::StartNextTask(void)
+{
+	bool stillMore;
+	int index = 0;
+	do {
+		Slot *slot = m_firstSlot;
+		stillMore = false;
+		while(slot) {
+			if(index < slot->m_taskCount) {
+				if(slot->m_tasks[index].m_address) {
+					m_activeSlot = slot;
+					m_activePrio = index;
+					CRC->CR = 1;
+					LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(), reinterpret_cast<uint32_t>(slot->m_tasks[index].m_address));
+					LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), slot->m_tasks[index].m_wordCount);
+					LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
+					slot->m_tasks[index].m_address = nullptr;	// marking as started
+					return;
+				}
+				if(index + 1 < slot->m_taskCount)
+					stillMore = true;
+			}
+			slot = slot->m_next;
+		}
+		++index;
+	} while(stillMore);
+	m_activeSlot = nullptr;
+}
+
+
+void LL_CrcHandler::WaitResults(Slot &slot, uint8_t prio) const
+{
+	while(IsQueued(slot, prio));
+	while(IsActive(slot, prio));
+}
+
+
+uint32_t LL_CrcHandler::Compute(
+		Slot &slot, uint8_t prio, void const *address, uint16_t len)
+{
+	uint32_t result;
+	Enqueue(slot, prio, address, len, nullptr, reinterpret_cast<uintptr_t>(&result));
+	while(IsActive(slot, prio));
+	return result;
+}
+
+}	// namespace f4ll