This commit is contained in:
Attila Body 2019-11-15 20:45:11 +01:00
parent ee09dcef00
commit 83f510bb59
13 changed files with 213 additions and 64 deletions

View file

@ -19,6 +19,8 @@ PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream
: UsartCore(usart, dma, streamRx, streamTx)
{
CrcHandler::Instance().AttachSlot(m_crcSlot);
LL_USART_EnableIT_IDLE(usart);
LL_USART_EnableIT_ERROR(usart);
}

View file

@ -14,28 +14,37 @@ UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx,
, m_rxDma(dma, streamRx)
, m_txDma(dma, streamTx)
{
uint32_t status = usart->SR;
volatile uint32_t tmpreg = usart->DR; // clearing some of the error/status bits in the USART
(void) tmpreg;
(void) status;
*m_txDma.GetIfcReg() =
m_txDma.GetTcMask() | m_rxDma.GetHtMask() | m_txDma.GetTeMask() | m_rxDma.GetFeMask() | m_rxDma.GetDmeMask();
*m_rxDma.GetIfcReg() =
m_rxDma.GetTcMask() | m_rxDma.GetHtMask() | m_rxDma.GetTeMask() | m_rxDma.GetFeMask() | m_rxDma.GetDmeMask();
LL_DMA_EnableIT_TC(dma, streamRx);
LL_DMA_EnableIT_TE(dma, streamRx);
LL_DMA_EnableIT_TC(dma, streamTx);
LL_DMA_EnableIT_TE(dma, streamTx);
LL_USART_EnableIT_IDLE(usart);
LL_USART_EnableIT_ERROR(usart);
}
void UsartCore::UsartIsr()
{
if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
uint32_t status = m_usart->SR;
volatile uint32_t tmpreg = m_usart->DR; // clearing some of the error/status bits in the HW
(void) tmpreg;
if(LL_USART_IsEnabledIT_TC(m_usart) && LL_USART_IsActiveFlag_TC(m_usart)) { // transmission complete
LL_USART_DisableIT_TC(m_usart);
TransmissionComplete();
} else if(LL_USART_IsEnabledIT_ERROR(m_usart)) {
uint32_t status = m_usart->SR;
volatile uint32_t tmpreg = m_usart->DR; // clearing some of the error/status bits in the HW
(void) tmpreg;
if(status & USART_SR_IDLE) {
ReceiverIdle();
}
}
if(LL_USART_IsEnabledIT_IDLE(m_usart) && (status & USART_SR_IDLE)) {
ReceiverIdle();
}
if(LL_USART_IsEnabledIT_ERROR(m_usart)) {
if(status & USART_SR_FE) {
FramingError();
}

View file

@ -28,6 +28,7 @@ uint32_t GetDmeMask(uint32_t stream);
uint32_t GetTeMask(uint32_t stream);
uint32_t GetHtMask(uint32_t stream);
uint32_t GetTcMask(uint32_t stream);
uint32_t GetFeMask(uint32_t stream);
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream);

View file

@ -36,6 +36,11 @@ void InitUartStatus(
struct crcstatus_t *crcStatus,
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
{
uint32_t status = usart->SR;
volatile uint32_t tmpreg = usart->DR; // clearing some of the error/status bits in the USART
(void) tmpreg;
(void) status;
st->usart = usart;
InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
@ -60,6 +65,13 @@ void InitUartStatus(
AttachCrcTask(crcStatus, &st->crcSlot, st->crcTasks, 2);
memset(&st->stats, 0, sizeof(st->stats));
*GetIfcReg(dma, stream_rx) =
GetTcMask(stream_rx) | GetHtMask(stream_rx) |
GetTeMask(stream_rx) | GetFeMask(stream_rx) | GetDmeMask(stream_rx);
*GetIfcReg(dma, stream_tx) =
GetTcMask(stream_tx) | GetHtMask(stream_tx) |
GetTeMask(stream_tx) | GetFeMask(stream_tx) | GetDmeMask(stream_tx);
LL_DMA_EnableIT_TC(dma, stream_rx);
LL_DMA_EnableIT_TE(dma, stream_rx);
LL_DMA_EnableIT_TC(dma, stream_tx);
@ -98,16 +110,8 @@ uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length,
BuildHeader(&status->txBuffer, status->txSerial++, length);
uint16_t payloadLength = RoundUpTo4(length);
if(payload) {
#ifdef USART_USE_MEMCPY_DMA
if((uint32_t)payload & 3)
memcpy(status->txBuffer.packet.payload, payload, length);
else
MemcpyDma(status->txBuffer.packet.payload, payload, length);
#else
if(payload)
memcpy(status->txBuffer.packet.payload, payload, length);
#endif
}
status->txBuffer.requestedLength = sizeof(USARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
status->txBuffer.busy = 1;
status->txBuffer.error = 0;