removing prefix LL_ from class/struct names under f4ll namespace

2019-11-12 15:26:16 +01:00 · 2019-11-12 15:26:16 +01:00 · 7cdc79c2ac
commit 7cdc79c2ac
parent 180f2ef624
17 changed files with 184 additions and 183 deletions
--- a/components/f4ll/src/usartcore.cpp
+++ b/components/f4ll/src/usartcore.cpp
@ -0,0 +1,116 @@
+/*
+ * ll_dmadrivenusartcore.cpp
+ *
+ *  Created on: Nov 4, 2019
+ *      Author: abody
+ */
+
+#include "f4ll/usartcore.h"
+
+namespace f4ll {
+
+UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
+: m_usart(usart)
+, m_rxDma(dma, streamRx)
+, m_txDma(dma, streamTx)
+{
+	LL_DMA_EnableIT_TC(dma, streamRx);
+	LL_DMA_EnableIT_TE(dma, streamRx);
+	LL_DMA_EnableIT_TC(dma, streamTx);
+	LL_DMA_EnableIT_TE(dma, streamTx);
+	LL_USART_EnableIT_IDLE(usart);
+}
+
+void UsartCore::UsartIsr()
+{
+	if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) {	//	receiver idle
+		LL_USART_ClearFlag_IDLE(m_usart);
+		ReceiverIdle();
+	} else if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) {	// transmission complete
+		LL_USART_DisableIT_TC(m_usart);
+		TransmissionComplete();
+	}
+}
+
+
+void UsartCore::RxDmaIsr()
+{
+	if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
+		*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
+		if(m_rxDma.IsEnabledIt_TC())
+			RxDmaTransferComplete();
+	}
+	if(*m_rxDma.GetIsReg() & m_rxDma.GetHtMask()) {
+		*m_rxDma.GetIfcReg() = m_rxDma.GetHtMask();
+		if(m_rxDma.IsEnabledIt_HT())
+			RxDmaHalfTransfer();
+	}
+	if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
+		*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
+		if(m_rxDma.IsEnabledIt_TE())
+			RxDmaError(DmaHelper::DmaErrorType::Transfer);
+	}
+	if(*m_rxDma.GetIsReg() & m_rxDma.GetFeMask()) {
+		*m_rxDma.GetIfcReg() = m_rxDma.GetFeMask();
+		if(m_rxDma.IsEnabledIt_FE())
+			RxDmaError(DmaHelper::DmaErrorType::Fifo);
+	}
+	if(*m_rxDma.GetIsReg() & m_rxDma.GetDmeMask()) {
+		*m_rxDma.GetIfcReg() = m_rxDma.GetDmeMask();
+		if(m_rxDma.IsEnabledIt_DME())
+			RxDmaError(DmaHelper::DmaErrorType::DirectMode);
+	}
+}
+
+
+void UsartCore::TxDmaIsr()
+{
+	if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) {	// DMA transfer complete
+		*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
+		if(m_txDma.IsEnabledIt_TC())
+			TxDmaTransferComplete();
+	}
+	if(*m_txDma.GetIsReg() & m_txDma.GetHtMask()) {
+		*m_txDma.GetIfcReg() = m_txDma.GetHtMask();
+		if(m_txDma.IsEnabledIt_HT())
+			TxDmaHalfTransfer();
+	}
+	if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
+		*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
+		if(m_txDma.IsEnabledIt_TE())
+			TxDmaError(DmaHelper::DmaErrorType::Transfer);
+	}
+	if(*m_txDma.GetIsReg() & m_txDma.GetFeMask()) {
+		*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
+		if(m_txDma.IsEnabledIt_FE())
+			TxDmaError(DmaHelper::DmaErrorType::Fifo);
+	}
+	if(*m_txDma.GetIsReg() & m_txDma.GetDmeMask()) {
+		*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
+		if(m_txDma.IsEnabledIt_DME())
+			TxDmaError(DmaHelper::DmaErrorType::DirectMode);
+	}
+}
+
+
+void UsartCore::SetupTransmit(void const *buffer, uint16_t length)
+{
+	LL_DMA_ConfigAddresses(m_txDma.GetDma(), m_txDma.GetStream(), reinterpret_cast<uint32_t>(buffer),
+			LL_USART_DMA_GetRegAddr(m_usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+	LL_DMA_SetDataLength(m_txDma.GetDma(), m_txDma.GetStream(), length);
+	LL_USART_EnableDMAReq_TX(m_usart);
+	LL_DMA_EnableStream(m_txDma.GetDma(), m_txDma.GetStream());
+}
+
+
+void UsartCore::SetupReceive(void *buffer, uint16_t length)
+{
+	LL_DMA_ConfigAddresses(m_rxDma.GetDma(), m_rxDma.GetStream(), LL_USART_DMA_GetRegAddr(m_usart),
+			reinterpret_cast<uint32_t>(buffer), LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+	LL_DMA_SetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream(), length);
+	LL_USART_EnableDMAReq_RX(m_usart);
+	LL_USART_ClearFlag_ORE(m_usart);
+	LL_DMA_EnableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
+}
+
+} /* namespace f4ll */