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Reorganizing project

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This commit is contained in:
Attila Body 2019-11-08 11:47:49 +01:00
parent 2d6567b1b2
commit 76ba80db36
51 changed files with 139 additions and 266 deletions
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11
components/f4ll_c/component.mk Normal file
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#encoder
SELF_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
REL_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
ifeq ($(MKDBG), 1)
$(info >>> $(REL_DIR)/component.mk)
endif
$(eval C_INCLUDES += -I$(REL_DIR)/inc)
$(eval C_SOURCES += $(wildcard $(REL_DIR)/src/*.c))
ifeq ($(MKDBG), 1)
$(info <<<)
endif

19
components/f4ll_c/inc/console_handler.h Normal file
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/*
* interrupt.h
*
* Created on: Aug 29, 2019
* Author: abody
*/
#ifndef INTERRUPT_HANDLERS_H_
#define INTERRUPT_HANDLERS_H_
#include "usart.h"
#include "f4ll_c/dma_helper.h"
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart);
void HandleConsoleUsartIrq(USART_TypeDef *usart);
void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo);
#endif /* INTERRUPT_HANDLERS_H_ */

53
components/f4ll_c/inc/crc_handler.h Normal file
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/*
* interrupt.h
*
* Created on: Aug 29, 2019
* Author: abody
*/
#ifndef CRC_HANDLER_H_
#define CRC_HANDLER_H_
#include <inttypes.h>
#ifdef HAVE_CONFIG
#include "config.h"
#endif // HAVE_CONFIG
#include "f4ll_c/dma_helper.h"
#ifndef CRCTASKCOUNT
#define CRCTASKCOUNT 2
#endif
typedef struct {
DMAINFO dmaInfo;
volatile uint8_t activeSlot;
struct crctask_t {
void *address;
uint16_t wordCount;
void (*callback)(void*, uint32_t, uint8_t);
void *callbackParam;
} volatile crcTasks[CRCTASKCOUNT];
} CRCSTATUS;
void InitCrcStatus(CRCSTATUS *status, DMA_TypeDef *dma, uint32_t stream);
static inline uint8_t GetActiveSlot(CRCSTATUS *status) {
return status->activeSlot;
}
static inline uint8_t IsSlotQueued(CRCSTATUS *status, uint8_t slot) {
return status->crcTasks[slot].address != NULL;
}
static inline uint8_t IsSlotActive(CRCSTATUS *status, uint8_t slot) {
return status->crcTasks[slot].callback != NULL || status->crcTasks[slot].callbackParam != NULL;
}
uint8_t EnqueueCrcTask(CRCSTATUS *crcStatus, uint8_t slot, uint8_t *address, uint16_t len,
void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
void WaitCrcResults(CRCSTATUS *status, uint8_t slot);
uint32_t ComputeCrc(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len);
void ComputeCrcAsync(CRCSTATUS *status, uint8_t slot,
uint8_t *address, uint16_t len,
void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
void HandleCrcDmaIrq(CRCSTATUS *status);
#endif /* CRC_HANDLER_H_ */

34
components/f4ll_c/inc/dma_helper.h Normal file
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/*
* dma_helper.h
*
* Created on: Sep 18, 2019
* Author: abody
*/
#ifndef DMA_HELPER_H_
#define DMA_HELPER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
typedef struct {
DMA_TypeDef *dma;
uint32_t stream;
volatile uint32_t *isReg;
volatile uint32_t *ifcReg;
uint32_t feMask;
uint32_t dmeMask;
uint32_t teMask;
uint32_t htMask;
uint32_t tcMask;
} DMAINFO;
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream);
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream);
uint32_t GetDmeMask(uint32_t stream);
uint32_t GetTeMask(uint32_t stream);
uint32_t GetHtMask(uint32_t stream);
uint32_t GetTcMask(uint32_t stream);
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream);
#endif /* DMA_HELPER_H_ */

1
components/f4ll_c/inc/f4ll_c Symbolic link
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.

18
components/f4ll_c/inc/memcpy_dma.h Normal file
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/*
* memcpy_dma.h
*
* Created on: Oct 1, 2019
* Author: abody
*/
#ifndef MEMCPY_DMA_H_
#define MEMCPY_DMA_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream);
void * MemcpyDma(void *dst, void const *src, size_t length);
void HandleMemcpyDmaIrq();
#endif /* MEMCPY_DMA_H_ */

31
components/f4ll_c/inc/strutil.h Normal file
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/*
* strutil.h
*
* Created on: Feb 11, 2017
* Author: compi
*/
#ifndef _STM32PLUS_STRUTIL_H_
#define _STM32PLUS_STRUTIL_H_
#include <stddef.h>
#include <inttypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//////////////////////////////////////////////////////////////////////////////
size_t strcpy_ex(char *dst, char const *src);
size_t uitodec(char* buffer, uint32_t data);
size_t uitohex(char* buffer, uint32_t data, uint8_t chars);
size_t itodec(char* buffer, int data);
size_t itohex(char* buffer, int data);
void strrev(char *first, char *last);
char tochr(const uint8_t in, const uint8_t upper);
#ifdef __cplusplus
}
#endif
#endif /* _STM32PLUS_STRUTIL_H_ */

142
components/f4ll_c/inc/usart_handler.h Normal file
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/*
* usart_handler.h
*
* Created on: Sep 16, 2019
* Author: abody
*/
#ifndef USART_HANDLER_H_
#define USART_HANDLER_H_
#include <inttypes.h>
#include "f4ll_c/dma_helper.h"
#include "f4ll_c/crc_handler.h"
struct _usart_status;
typedef struct _usart_status USARTSTATUS;
struct usart_buffer;
typedef void (*PACKETRECEIVEDCALLBACK)(void *userParam, struct usart_buffer *buffer);
void InitUartStatus(
USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
uint32_t stream_rx, uint32_t stream_tx,
CRCSTATUS *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot,
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam);
uint8_t* GetTxBuffer(USARTSTATUS *status);
uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, CRCSTATUS *crcStatus);
void SetupReceive(USARTSTATUS *status);
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length);
void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex, CRCSTATUS *crcStatus);
void HandleUsartRxDmaIrq(USARTSTATUS *status);
void HandleUsartTxDmaIrq(USARTSTATUS *status);
void HandleUsartIrq(USARTSTATUS *status);
/******************************************************************************************
*
*
*
*/
struct usart_stats {
uint32_t overrun;
uint32_t hdrError;
uint32_t lastErrHdr;
uint32_t payloadErrror;
uint32_t pep1, pep2;
uint32_t dmaError;
uint32_t rcvd;
uint32_t premature_hdr;
uint32_t premature_payload;
uint32_t sent;
uint32_t skiped;
};
typedef struct {
uint8_t startByte;
uint8_t serial;
uint8_t payloadLength;
uint8_t hash;
} USARTPACKETHEADER;
typedef struct {
USARTPACKETHEADER header;
//!!! should start on word offset !!!
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned)) USARTPACKET;
struct usart_buffer {
USARTPACKET packet;
//transfer area ends here
volatile uint8_t busy;
volatile uint8_t error;
uint16_t requestedLength;
uint32_t errorInfo;
USARTSTATUS *usartStatus;
};
struct _usart_status {
USART_TypeDef *usart;
DMAINFO rxDmaInfo;
DMAINFO txDmaInfo;
CRCSTATUS *crcStatus;
uint8_t rxSerial;
uint8_t txSerial;
struct usart_stats stats;
uint8_t activeRxBuf;
uint8_t rxCrcSlot;
uint8_t txCrcSlot;
PACKETRECEIVEDCALLBACK packetReceivedCallback;
void *packetReceivedCallbacParam;
struct usart_buffer txBuffer;
struct usart_buffer rxBuffers[2];
};
#ifndef USART_STATS_DISABLED
static inline void StatsIncOverrun(struct usart_stats *s) {
++s->overrun;
}
static inline void StatsIncHdrError(struct usart_stats *s, uint32_t hdr) {
++s->hdrError;
s->lastErrHdr = hdr;
}
static inline void StatsIncPayloadError(struct usart_stats *s, uint32_t pep1, uint32_t pep2) {
++s->payloadErrror;
s->pep1 = pep1;
s->pep2 = pep2;
}
static inline void StatsIncDmaError(struct usart_stats *s) {
++s->dmaError;
}
static inline void StatsIncRcvd(struct usart_stats *s) {
++s->rcvd;
}
static inline void StatsIncPremature_hdr(struct usart_stats *s) {
++s->premature_hdr;
}
static inline void StatsIncPremature_payload(struct usart_stats *s) {
++s->premature_payload;
}
static inline void StatsIncSent(struct usart_stats *s) {
++s->sent;
}
static inline void StatsAddSkiped(struct usart_stats *s, uint8_t cnt) {
s->skiped += s->rcvd > 2 ? cnt : 0;
}
#else // USART_STATS_DISABLED
#define StatsIncOverrun(x)
#define StatsIncHdrError(x,y)
#define StatsIncPayloadError(x,y,z)
#define StatsIncDmaError(x)
#define StatsIncRcvd(x)
#define StatsIncPremature_hdr(x)
#define StatsIncPremature_payload(x)
#define StatsIncSent(x)
#define StatsAddSkiped(x)
#endif // USART_STATS_DISABLED
#endif /* UART_HANDLER_H_ */

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components/f4ll_c/src/console_handler.c Normal file
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/*
* interrupt.c
*
* Created on: Aug 29, 2019
* Author: abody
*/
#include "main.h"
#include "globals.h"
#include "f4ll_c/usart_handler.h"
#include "f4ll_c/strutil.h"
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart) // debug usart
{
DIAG_INTERRUPT_IN();
if(*info->isReg & info->tcMask) { // DMA transfer complete
*info->ifcReg = info->tcMask;
LL_USART_EnableIT_TC(usart);
LL_DMA_DisableStream(info->dma, info->stream);
}
DIAG_INTERRUPT_OUT();
}
void HandleConsoleUsartIrq(USART_TypeDef *usart)
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_TC(usart) && LL_USART_IsEnabledIT_TC(usart)) // transmission complete
LL_USART_DisableIT_TC(usart);
DIAG_INTERRUPT_OUT();
}
#define ADDINFO(b,s,u) \
b += strcpy_ex(b,s); \
b += uitodec(b,u);
void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo)
{
char ids[] = " : ";
char *bs = buffer;
ids[0] = id + '0';
buffer += strcpy_ex(buffer, ids);
ADDINFO(buffer, " s: ", stats->sent);
ADDINFO(buffer, " r: ", stats->rcvd);
ADDINFO(buffer, " sk: ", stats->skiped);
ADDINFO(buffer, " or: ", stats->overrun);
ADDINFO(buffer, " he: ", stats->hdrError);
buffer += strcpy_ex(buffer,",0x");
buffer += uitohex(buffer, stats->lastErrHdr, 8);
ADDINFO(buffer, " pe: ", stats->payloadErrror);
buffer += strcpy_ex(buffer,",0x");
buffer += uitohex(buffer, stats->pep1, 8);
buffer += strcpy_ex(buffer,",0x");
buffer += uitohex(buffer, stats->pep2, 8);
ADDINFO(buffer, " de: ", stats->dmaError);
ADDINFO(buffer, " pmh: ", stats->premature_hdr);
ADDINFO(buffer, " pmp: ", stats->premature_payload);
buffer += strcpy_ex(buffer, "\r\n");
SetupTransmit(usart, dmaInfo->dma, dmaInfo->stream, bs, buffer - bs + 1);
}

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components/f4ll_c/src/crc_handler.c Normal file
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/*
* interrupt.c
*
* Created on: Aug 29, 2019
* Author: abody
*/
#include <string.h>
#include <platform/crc_ll.h>
#include "diag.h"
#include "f4ll_c/dma_helper.h"
#include "f4ll_c/crc_handler.h"
#ifndef DIAG_CRC_CALC_START
# define DIAG_CRC_CALC_START()
#endif
#ifndef DIAG_CRC_CALC_END
# define DIAG_CRC_CALC_END()
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
void InitCrcStatus(CRCSTATUS *st, DMA_TypeDef *dma, uint32_t stream)
{
InitDmaInfo(&st->dmaInfo, dma, stream);
LL_DMA_EnableIT_TC(dma, stream);
LL_DMA_EnableIT_TE(dma, stream);
LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
st->activeSlot = 0xff;
memset((void*)st->crcTasks, 0, sizeof(st->crcTasks));
}
uint8_t EnqueueCrcTask(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len,
void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
{
uint32_t prim = __get_PRIMASK();
uint16_t need_start;
while(status->activeSlot == slot);
__disable_irq();
need_start = (status->activeSlot == 0xff);
status->crcTasks[slot].address = need_start ? NULL : address;
status->crcTasks[slot].wordCount = (len+3)/4;
status->crcTasks[slot].callback = callback;
status->crcTasks[slot].callbackParam = callbackParam;
if(need_start)
status->activeSlot = slot;
__set_PRIMASK(prim);
if(need_start) {
CRC->CR = 1;
LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)address);
LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, (len+3)/4);
DIAG_CRC_CALC_START();
LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
}
return need_start;
}
void WaitCrcResults(CRCSTATUS *status, uint8_t slot)
{
while(IsSlotQueued(status, slot));
while(GetActiveSlot(status) == slot);
}
uint32_t ComputeCrc(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len)
{
uint32_t result;
EnqueueCrcTask(status, slot, address, len, NULL, &result);
while(status->crcTasks[slot].callbackParam);
return result;
}
void StartNextCrcTask(CRCSTATUS *status)
{
uint16_t slot;
for(slot = 0; slot < CRCTASKCOUNT; ++slot)
if(status->crcTasks[slot].address) {
status->activeSlot = slot;
CRC->CR = 1;
LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)status->crcTasks[slot].address);
LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, status->crcTasks[slot].wordCount);
DIAG_CRC_CALC_START();
LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
status->crcTasks[slot].address = NULL; // marking as started
return;
}
status->activeSlot = 0xff;
}
void HandleCrcDmaIrq(CRCSTATUS *status)
{
DIAG_INTERRUPT_IN();
if(*status->dmaInfo.isReg & status->dmaInfo.tcMask) { // DMA transfer complete
*status->dmaInfo.ifcReg = status->dmaInfo.tcMask;
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
if(status->activeSlot != 0xff) {
struct crctask_t *tsk = (struct crctask_t *)&status->crcTasks[status->activeSlot];
if(tsk->callback)
tsk->callback(tsk->callbackParam, CRC->DR, 1);
else if(tsk->callbackParam)
*(uint32_t*)tsk->callbackParam = CRC->DR;
tsk->callback = tsk->callbackParam = NULL; // marking as inactive
DIAG_CRC_CALC_END();
StartNextCrcTask(status);
}
}
else if(*status->dmaInfo.isReg & status->dmaInfo.teMask) {
*status->dmaInfo.ifcReg = status->dmaInfo.teMask;
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
if(status->activeSlot != 0xff) {
struct crctask_t *tsk = (struct crctask_t *)&status->crcTasks[status->activeSlot];
if(tsk->callback)
tsk->callback(tsk->callbackParam, CRC->DR, 0);
else if(tsk->callbackParam)
*(uint32_t*)tsk->callbackParam = 0xffffffff;
tsk->callback = tsk->callbackParam = NULL; // marking as inactive
DIAG_CRC_CALC_END();
StartNextCrcTask(status);
}
}
DIAG_INTERRUPT_OUT();
}

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components/f4ll_c/src/dma_helper.c Normal file
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/*
* dma_helper.c
*
* Created on: Sep 18, 2019
* Author: abody
*/
#include "f4ll_c/dma_helper.h"
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream)
{
if(dma == DMA1)
return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR;
else
return (stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR;
}
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream)
{
if(dma == DMA1)
return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR;
else
return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR;
}
uint32_t GetFeMask(uint32_t stream)
{
static const uint32_t feMasks[8] = {
DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7
};
return feMasks[stream];
}
uint32_t GetDmeMask(uint32_t stream)
{
static const uint32_t dmeMasks[8] = {
DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7
};
return dmeMasks[stream];
}
uint32_t GetTeMask(uint32_t stream)
{
static const uint32_t teMasks[8] = {
DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7
};
return teMasks[stream];
}
uint32_t GetHtMask(uint32_t stream)
{
static const uint32_t htMasks[8] = {
DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7
};
return htMasks[stream];
}
uint32_t GetTcMask(uint32_t stream)
{
static const uint32_t tcMasks[8] = {
DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7
};
return tcMasks[stream];
}
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream)
{
info->dma = dma;
info->stream = stream;
info->isReg = GetIsReg(dma, stream);
info->ifcReg = GetIfcReg(dma, stream);
info->feMask = GetFeMask(stream);
info->dmeMask = GetDmeMask(stream);
info->teMask = GetTeMask(stream);
info->htMask = GetHtMask(stream);
info->tcMask = GetTcMask(stream);
}

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components/f4ll_c/src/memcpy_dma.c Normal file
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/*
* memcpy_dma.c
*
* Created on: Oct 1, 2019
* Author: abody
*/
#include "f4ll_c/memcpy_dma.h"
#include "f4ll_c/dma_helper.h"
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
volatile uint8_t g_memcpyDmaBusy = 0;
static DMAINFO g_memcpyDmaInfo;
void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream)
{
InitDmaInfo(&g_memcpyDmaInfo, dma, stream);
LL_DMA_EnableIT_TC(dma, stream);
}
void * MemcpyDma(void *dst, void const *src, size_t length)
{
LL_DMA_SetM2MSrcAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)src);
LL_DMA_SetM2MDstAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)dst);
LL_DMA_SetDataLength(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (length+3)/4 );
g_memcpyDmaBusy = 1;
LL_DMA_EnableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
while(g_memcpyDmaBusy);
return dst;
}
void HandleMemcpyDmaIrq()
{
DIAG_INTERRUPT_IN();
if(*g_memcpyDmaInfo.isReg & g_memcpyDmaInfo.tcMask) { // DMA transfer complete
*g_memcpyDmaInfo.ifcReg = g_memcpyDmaInfo.tcMask;
LL_DMA_DisableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
g_memcpyDmaBusy = 0;
}
DIAG_INTERRUPT_OUT();
}

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#include <stdint.h>
#include "f4ll_c/strutil.h"
//////////////////////////////////////////////////////////////////////////////
size_t strcpy_ex(char *dst, char const *src)
{
size_t ret = 0;
do {
*dst++ = *src;
++ret;
} while(*src++);
return ret - 1;
}
//////////////////////////////////////////////////////////////////////////////
void strrev(char *first, char *last)
{
char tmp;
while(last > first) {
tmp = *first;
*first++ = *last;
*last-- = tmp;
}
}
//////////////////////////////////////////////////////////////////////////////
char tochr(const uint8_t in, const uint8_t upper)
{
return in + ((in < 10) ? '0' : (upper ? 'A' : 'a') - 10);
}
//////////////////////////////////////////////////////////////////////////////
size_t uitodec(char* buffer, uint32_t data)
{
char *b2 = buffer;
if(!data) {
*b2++ = '0';
*b2 = '\0';
return 1;
}
while(data) {
*b2++ = (data % 10) + '0';
data /= 10;
}
size_t ret = b2 - buffer;
*b2-- = 0;
strrev(buffer, b2);
return ret;
}
//////////////////////////////////////////////////////////////////////////////
size_t uitohex(char* buffer, uint32_t data, uint8_t chars)
{
char *b2 = buffer;
size_t ret = 0;
if(chars == 0xff || !chars)
{
if(!data) {
*b2++ = '0';
*b2 = '\0';
return 1;
}
while(data) {
uint8_t curval = data & 0x0f;
*b2++ = tochr(curval, 1);
data >>= 4;
}
ret = b2 - buffer;
}
else
{
ret = chars;
for(uint8_t pos = 0; pos < (uint8_t)ret; ++pos) {
*b2++ = tochr(data & 0x0f, 1);
data >>= 4;
}
}
*b2-- = 0;
strrev(buffer, b2);
return ret;
}
//////////////////////////////////////////////////////////////////////////////
size_t itodec(char* buffer, int data)
{
if(data < 0) {
*buffer++ = '-';
return uitodec(buffer, -data) + 1;
}
return uitodec(buffer, data);
}
//////////////////////////////////////////////////////////////////////////////
size_t itohex(char* buffer, int data)
{
if(data < 0) {
*buffer++ = '-';
return uitohex(buffer, -data, 0) + 1;
}
return uitohex(buffer, data, 0);
}

258
components/f4ll_c/src/usart_handler.c Normal file
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/*
* usart_handler.c
*
* Created on: Sep 16, 2019
* Author: abody
*/
#include <string.h>
#include <platform/usart_ll.h>
#include "diag.h"
#include "f4ll_c/usart_handler.h"
#include "f4ll_c/dma_helper.h"
#include "f4ll_c/crc_handler.h"
#include "f4ll_c/memcpy_dma.h"
#ifndef DIAG_RX_BUFFER_SWITCH
# define DIAG_RX_BUFFER_SWITCH(x)
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
#define STARTMARKER 0x95
static inline uint32_t RoundUpTo4(uint32_t inp)
{
return (inp + 3) & 0xfffc;
}
void InitUartStatus(
USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
uint32_t stream_rx, uint32_t stream_tx,
CRCSTATUS *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot,
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
{
st->usart = usart;
InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
st->txBuffer.busy = 0;
st->txBuffer.error = 0;
st->txBuffer.requestedLength = 0;
st->rxBuffers[0].busy = 0;
st->rxBuffers[1].busy = 0;
st->rxBuffers[0].error = 0;
st->rxBuffers[1].error = 0;
st->rxBuffers[0].requestedLength = 0;
st->rxBuffers[1].requestedLength = 0;
st->txBuffer.usartStatus = st;
st->rxBuffers[0].usartStatus = st;
st->rxBuffers[1].usartStatus = st;
st->packetReceivedCallback = packetReceivedCallback;
st->packetReceivedCallbacParam = packetReceivedCallbackParam;
st->rxSerial = -1;
st->txSerial = 0;
st->activeRxBuf = 0;
st->crcStatus = crcStatus;
st->txCrcSlot = txCrcSlot;
st->rxCrcSlot = rxCrcSlot;
memset(&st->stats, 0, sizeof(st->stats));
LL_DMA_EnableIT_TC(dma, stream_rx);
LL_DMA_EnableIT_TE(dma, stream_rx);
LL_DMA_EnableIT_TC(dma, stream_tx);
LL_DMA_EnableIT_TE(dma, stream_tx);
LL_USART_EnableIT_IDLE(usart);
}
uint8_t* GetTxBuffer(USARTSTATUS *status)
{
return status->txBuffer.packet.payload;
}
static inline void BuildHeader(struct usart_buffer *buffer, uint8_t serial, uint8_t length)
{
uint8_t hash = STARTMARKER;
buffer->packet.header.startByte = STARTMARKER;
buffer->packet.header.serial = serial;
hash ^= serial;
buffer->packet.header.payloadLength = length - 1;
hash ^= length - 1;
buffer->packet.header.hash = hash;
}
static inline uint8_t CheckHeader(USARTPACKET *packet)
{
return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
}
uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, CRCSTATUS *crcStatus)
{
if(length > 256)
return 1;
BuildHeader(&status->txBuffer, status->txSerial++, length);
uint16_t payloadLength = RoundUpTo4(length);
if(payload) {
#ifdef USART_USE_MEMCPY_DMA
if((uint32_t)payload & 3)
memcpy(status->txBuffer.packet.payload, payload, length);
else
MemcpyDma(status->txBuffer.packet.payload, payload, length);
#else
memcpy(status->txBuffer.packet.payload, payload, length);
#endif
}
status->txBuffer.requestedLength = sizeof(USARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
status->txBuffer.busy = 1;
status->txBuffer.error = 0;
EnqueueCrcTask(crcStatus, status->txCrcSlot, status->txBuffer.packet.payload, length,
NULL, (uint32_t*)(status->txBuffer.packet.payload + payloadLength));
while(IsSlotQueued(crcStatus, status->txCrcSlot));
SetupTransmit(status->usart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
StatsIncSent(&status->stats);
return 0;
}
void SetupReceive(USARTSTATUS *status)
{
uint8_t packetIndex = status->activeRxBuf;
LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->usart), (uint32_t)&status->rxBuffers[packetIndex],
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
status->rxBuffers[packetIndex].requestedLength = sizeof(status->rxBuffers[packetIndex].packet);
LL_DMA_SetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream, status->rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
LL_USART_EnableDMAReq_RX(status->usart);
LL_USART_ClearFlag_ORE(status->usart);
LL_DMA_EnableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
}
void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex, CRCSTATUS *crcStatus)
{
struct usart_buffer *buffer = &status->rxBuffers[packetIndex];
if(buffer->busy) {
if(buffer->error)
StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + RoundUpTo4(buffer->packet.header.payloadLength + 1)));
else {
uint8_t diff = buffer->packet.header.serial - status->rxSerial;
if(diff > 1)
StatsAddSkiped(&status->stats, diff - 1);
status->rxSerial = buffer->packet.header.serial;
}
}
buffer->busy = buffer->error = 0;
}
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
{
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
LL_DMA_SetDataLength(dma, stream, length);
LL_USART_EnableDMAReq_TX(usart);
LL_DMA_EnableStream(dma, stream);
}
void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
{
struct usart_buffer *ub = (struct usart_buffer*) callbackParm;
if(!success)
ub->error = 1;
else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength + 1)) == calculatedCrc)
ub->busy = 1;
else {
ub->error = ub->busy = 1;
ub->errorInfo = calculatedCrc;
}
if(ub->usartStatus->packetReceivedCallback)
ub->usartStatus->packetReceivedCallback(ub->usartStatus->packetReceivedCallbacParam, ub);
}
void HandleUsartRxDmaIrq(USARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
StatsIncRcvd(&status->stats);
if(*status->rxDmaInfo.isReg & status->rxDmaInfo.tcMask) {
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.tcMask;
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet))
EnqueueCrcTask(status->crcStatus, status->rxCrcSlot,
status->rxBuffers[status->activeRxBuf].packet.payload,
status->rxBuffers[status->activeRxBuf].packet.header.payloadLength +1,
RxCrcComputedCallback, &status->rxBuffers[status->activeRxBuf]);
else {
StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
status->rxBuffers[status->activeRxBuf].error = 1;
}
} else if(*status->rxDmaInfo.isReg & status->rxDmaInfo.teMask) {
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.teMask;
status->rxBuffers[status->activeRxBuf].error = 1;
}
status->activeRxBuf ^= 1;
DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
if(status->rxBuffers[status->activeRxBuf].busy)
StatsIncOverrun(&status->stats);
SetupReceive(status);
DIAG_INTERRUPT_OUT();
}
void HandleUsartTxDmaIrq(USARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
LL_USART_EnableIT_TC(status->usart);
LL_DMA_DisableStream(status->txDmaInfo.dma, status->txDmaInfo.stream);
}
else if(*status->txDmaInfo.isReg & status->txDmaInfo.teMask) {
*status->txDmaInfo.ifcReg = status->txDmaInfo.teMask;
status->txBuffer.error = 1;
StatsIncDmaError(&status->stats);
}
if(*status->txDmaInfo.isReg & status->txDmaInfo.feMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.feMask;
if(*status->txDmaInfo.isReg & status->txDmaInfo.htMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.htMask;
if(*status->txDmaInfo.isReg & status->txDmaInfo.dmeMask)
*status->txDmaInfo.ifcReg = status->txDmaInfo.dmeMask;
DIAG_INTERRUPT_OUT();
}
void HandleUsartIrq(USARTSTATUS *status)
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
LL_USART_ClearFlag_IDLE(status->usart);
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
if(rcvdLen >= sizeof(USARTPACKETHEADER)) {
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
if(rcvdLen >= sizeof(USARTPACKETHEADER) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
else
StatsIncPremature_payload(&status->stats);
} else {
status->rxBuffers[status->activeRxBuf].error = 1;
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
}
} else
StatsIncPremature_hdr(&status->stats);
}
else if(LL_USART_IsActiveFlag_TC(status->usart) && LL_USART_IsEnabledIT_TC(status->usart)) { // transmission complete
LL_USART_DisableIT_TC(status->usart);
LL_USART_DisableDirectionTx(status->usart); // enforcing an idle frame
LL_USART_EnableDirectionTx(status->usart);
status->txBuffer.busy = 0;
}
DIAG_INTERRUPT_OUT();
}