Reorganizing project
This commit is contained in:
parent
2d6567b1b2
commit
76ba80db36
51 changed files with 139 additions and 266 deletions
11
components/f4ll/component.mk
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11
components/f4ll/component.mk
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#encoder
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SELF_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
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REL_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
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ifeq ($(MKDBG), 1)
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$(info >>> $(REL_DIR)/component.mk)
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endif
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$(eval C_INCLUDES += -I$(REL_DIR)/inc)
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$(eval CXX_SOURCES += $(wildcard $(REL_DIR)/src/*.cpp))
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ifeq ($(MKDBG), 1)
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$(info <<<)
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endif
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1
components/f4ll/inc/f4ll
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1
components/f4ll/inc/f4ll
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.
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43
components/f4ll/inc/ll_consolehandler.h
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43
components/f4ll/inc/ll_consolehandler.h
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/*
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* ll_consolehandler.h
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*
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* Created on: Nov 7, 2019
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* Author: abody
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*/
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#ifndef LL_CONSOLEHANDLER_H_
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#define LL_CONSOLEHANDLER_H_
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#include "f4ll/ll_hsusart.h"
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#include "singleton.h"
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namespace f4ll {
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class LL_ConsoleHandler: public LL_UsartCore, public Singleton<LL_ConsoleHandler>
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{
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friend class Singleton<LL_ConsoleHandler>;
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public:
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason);
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void PrintStats(uint8_t id, LL_HsUsart &usart);
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private:
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LL_ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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char m_buffer[128];
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uint16_t m_used = 0;
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};
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} /* namespace f4ll */
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#endif /* LL_CONSOLEHANDLER_H_ */
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89
components/f4ll/inc/ll_crchandler.h
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89
components/f4ll/inc/ll_crchandler.h
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/*
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* ll_crchandler.h
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*
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* Created on: Oct 26, 2019
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* Author: compi
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*/
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#ifndef LL_CRCHANDLER_H_
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#define LL_CRCHANDLER_H_
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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#include "f4ll/ll_dmahelper.h"
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#include "singleton.h"
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extern "C" void _HandleCrcDmaIrq(void);
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namespace f4ll {
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class LL_CrcHandler : public Singleton<LL_CrcHandler>
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{
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friend class Singleton<LL_CrcHandler>;
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public:
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struct ICallback
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{
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, int prio) = 0;
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, int prio) = 0;
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};
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class SlotBase
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{
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friend class LL_CrcHandler;
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public:
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struct CrcTask {
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void const * volatile m_address; // changed to nullptr when execution starts
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uint16_t volatile m_wordCount;
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LL_CrcHandler::ICallback *m_callback;
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uintptr_t m_callbackParam;
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};
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private:
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SlotBase *m_next = nullptr;
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uint8_t m_taskCount;
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virtual CrcTask& operator[](int index) = 0;
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protected:
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SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
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SlotBase() = delete;
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SlotBase(SlotBase const &other) = delete;
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};
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// DON't try this at home! we "extend" LL_CrcHandler::m_tasks this way
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template <uint8_t n> class Slot : public SlotBase
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{
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public:
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Slot() : SlotBase(n) {}
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virtual CrcTask& operator[](int index) { return m_tasks[index]; }
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private:
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Slot::CrcTask m_tasks[n];
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};
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void AttachSlot(SlotBase &slot);
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bool Enqueue(SlotBase &slot, uint8_t prio, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam);
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uint32_t Compute(SlotBase &slot, uint8_t prio, void const *address, uint16_t len);
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bool IsActive(SlotBase &slot, uint8_t prio) const;
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bool IsQueued(SlotBase &slot, uint8_t prio) const;
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bool IsRunning(SlotBase &slot, uint8_t prio) const;
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void DmaTransferCompleted(void);
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private:
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LL_CrcHandler(DMA_TypeDef *dma, uint32_t stream);
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friend void ::_HandleCrcDmaIrq(void);
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void StartNextTask(void);
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void WaitResults(SlotBase &slot, uint8_t prio) const;
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LL_DmaHelper m_dma;
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SlotBase * volatile m_firstSlot = nullptr;
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SlotBase * volatile m_activeSlot = nullptr;
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int volatile m_activePrio;
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};
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} // namespace f4ll
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#endif /* LL_CRCHANDLER_H_ */
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58
components/f4ll/inc/ll_dmahelper.h
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58
components/f4ll/inc/ll_dmahelper.h
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/*
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* ll_dmahelper.h
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*
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* Created on: Oct 25, 2019
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* Author: abody
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*/
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#ifndef LL_DMAHELPER_H_
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#define LL_DMAHELPER_H_
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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namespace f4ll {
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class LL_DmaHelper {
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public:
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LL_DmaHelper(DMA_TypeDef *dma, uint32_t stream);
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LL_DmaHelper(LL_DmaHelper const &base) = default;
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inline DMA_TypeDef* GetDma() const { return m_dma; }
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inline uint32_t GetStream() const { return m_stream; }
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inline volatile uint32_t* GetIsReg() const { return m_isReg; }
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inline volatile uint32_t* GetIfcReg() const { return m_ifcReg; }
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inline uint32_t GetFeMask() const { return m_FEMasks[m_stream]; }
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inline uint32_t GetDmeMask() const { return m_DMEMasks[m_stream]; }
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inline uint32_t GetTeMask() const { return m_TEMasks[m_stream]; }
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inline uint32_t GetHtMask() const { return m_HTMasks[m_stream]; }
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inline uint32_t GetTcMask() const { return m_TCMasks[m_stream]; }
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inline bool IsEnabledIt_HT() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TE() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TC() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_DME() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_FE() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
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enum class DmaErrorType {
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Transfer,
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DirectMode,
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Fifo
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};
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private:
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DMA_TypeDef *m_dma;
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uint32_t m_stream;
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volatile uint32_t *m_isReg;
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volatile uint32_t *m_ifcReg;
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static const uint32_t m_FEMasks[8];
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static const uint32_t m_DMEMasks[8];
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static const uint32_t m_TEMasks[8];
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static const uint32_t m_HTMasks[8];
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static const uint32_t m_TCMasks[8];
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};
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} /* namespace f4ll */
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#endif /* LL_DMAHELPER_H_ */
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111
components/f4ll/inc/ll_hsusart.h
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111
components/f4ll/inc/ll_hsusart.h
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/*
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* ll_HsUsart.h
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*
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* Created on: Oct 29, 2019
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* Author: abody
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*/
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#ifndef LL_HSUSART_H_
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#define LL_HSUSART_H_
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#include <platform/usart_ll.h>
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#include "f4ll/ll_usartcore.h"
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#include "f4ll/ll_crchandler.h"
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namespace f4ll {
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struct DMAINFO;
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class LL_HsUsart : public LL_CrcHandler::ICallback, public LL_UsartCore
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{
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public:
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LL_HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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struct PacketHeader { // !!! size should be multiple of 4 !!!
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uint8_t startByte;
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uint8_t serial;
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uint8_t payloadLength;
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uint8_t hash;
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};
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struct Packet {
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PacketHeader header;
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uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
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} __attribute__((aligned));
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struct Stats {
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uint32_t overrun = 0;
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uint32_t hdrError = 0;
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uint32_t payloadErrror = 0;
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uint32_t pep1 = 0;
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uint32_t pep2 = 0;
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uint32_t rxDmaError = 0;
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uint32_t txDmaError = 0;
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uint32_t rcvd = 0;
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uint32_t premature_hdr = 0;
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uint32_t premature_payload = 0;
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uint32_t sent = 0;
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uint32_t skiped = 0;
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};
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struct IHsUsartCallback {
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virtual bool PacketReceived(LL_HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
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};
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// LL_CRCHandler::ICallback interface functions
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, int prio);
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, int prio);
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason);
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void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
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void SetupReceive(void);
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void RxProcessed(bool second);
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uint8_t* GetTxPacketBuffer(void);
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USART_TypeDef* GetUsart(void);
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Stats const & GetStats(void);
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bool IsTxBusy(void);
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bool IsTxFailed(void);
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bool IsRxBusy(bool second);
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bool IsRxFailed(bool second);
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void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
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private:
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void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
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bool CheckHeader(PacketHeader &header);
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void SwitchRxBuffers(void);
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struct Buffer {
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Packet packet;
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//transfer area ends here
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volatile bool busy = 0;
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volatile bool error = 0;
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uint16_t requestedLength = 0;
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uint32_t errorInfo = 0;
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};
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static const uint8_t STARTMARKER = 0x95;
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uint8_t m_rxSerialNo = -1;
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uint8_t m_txSerialNo = -1;
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Stats m_stats;
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bool m_rxBufferSelector = false;
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LL_CrcHandler::Slot<2> m_crcSlot;
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IHsUsartCallback *m_userCallback = nullptr;
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uintptr_t m_userCallbackParam = 0;
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Buffer m_txBuffer;
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Buffer m_rxBuffers[2];
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};
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}
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#endif /* LL_HSUSART_H_ */
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28
components/f4ll/inc/ll_memcpydma.h
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28
components/f4ll/inc/ll_memcpydma.h
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/*
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* llmemcpydma.h
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*
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* Created on: Nov 4, 2019
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* Author: abody
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*/
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#ifndef LL_MEMCPY_DMA_H_
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#define LL_MEMCPY_DMA_H_
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#include "f4ll/ll_dmahelper.h"
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#include "singleton.h"
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namespace f4ll {
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class LL_MemcpyDma : public Singleton<LL_MemcpyDma>, private LL_DmaHelper
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{
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friend class Singleton<LL_MemcpyDma>;
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public:
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void* Copy(void *dst, void const *src, uint16_t length);
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void DmaTransferCompleted();
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private:
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LL_MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
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bool volatile m_busy = false;
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};
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} /* namespace f4ll */
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#endif /* LL_MEMCPY_DMA_H_ */
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51
components/f4ll/inc/ll_usartcore.h
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51
components/f4ll/inc/ll_usartcore.h
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/*
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* ll_dmadrivenusartcore.h
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*
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* Created on: Nov 4, 2019
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* Author: abody
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*/
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#ifndef LL_USARTCORE_H_
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#define LL_USARTCORE_H_
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#include <platform/usart_ll.h>
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#include "f4ll/ll_dmahelper.h"
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namespace f4ll {
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class LL_UsartCore
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{
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public:
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static inline void HandleUsartIrq(LL_UsartCore *_this) { _this->UsartIsr(); }
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static inline void HandleRxDmaIrq(LL_UsartCore *_this) { _this->RxDmaIsr(); }
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static inline void HandleTxDmaIrq(LL_UsartCore *_this) { _this->TxDmaIsr(); }
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protected:
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LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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virtual void ReceiverIdle() = 0;
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virtual void TransmissionComplete() = 0;
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virtual void RxDmaTransferComplete() = 0;
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virtual void RxDmaHalfTransfer() = 0;
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virtual void RxDmaError(LL_DmaHelper::DmaErrorType reason) = 0;
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virtual void TxDmaTransferComplete() = 0;
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virtual void TxDmaHalfTransfer() = 0;
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virtual void TxDmaError(LL_DmaHelper::DmaErrorType reason) = 0;
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void SetupTransmit(void const *buffer, uint16_t length);
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void SetupReceive(void *buffer, uint16_t length);
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void UsartIsr();
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void RxDmaIsr();
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void TxDmaIsr();
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USART_TypeDef *m_usart;
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LL_DmaHelper m_rxDma;
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LL_DmaHelper m_txDma;
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};
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} /* namespace f4ll */
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#endif /* LL_USARTCORE_H_ */
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65
components/f4ll/src/ll_consolehandler.cpp
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65
components/f4ll/src/ll_consolehandler.cpp
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/*
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* ll_consolehandler.cpp
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*
|
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* Created on: Nov 7, 2019
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* Author: abody
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*/
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#include "f4ll/ll_consolehandler.h"
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#include <f4ll_c/strutil.h>
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namespace f4ll {
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LL_ConsoleHandler::LL_ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
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: LL_UsartCore(usart, dma, streamRx, streamTx)
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{
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}
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void LL_ConsoleHandler::ReceiverIdle(void) {}
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void LL_ConsoleHandler::TransmissionComplete(void) {}
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void LL_ConsoleHandler::RxDmaTransferComplete(void) {}
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void LL_ConsoleHandler::RxDmaHalfTransfer(void) {}
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void LL_ConsoleHandler::RxDmaError(LL_DmaHelper::DmaErrorType reason) {}
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void LL_ConsoleHandler::TxDmaTransferComplete(void)
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{
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LL_USART_EnableIT_TC(m_usart);
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LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
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}
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void LL_ConsoleHandler::TxDmaHalfTransfer(void) {}
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void LL_ConsoleHandler::TxDmaError(LL_DmaHelper::DmaErrorType reason) {}
|
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#define ADDINFO(b,s,u) \
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b += strcpy_ex(b,s); \
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b += uitodec(b,u);
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|
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void LL_ConsoleHandler::PrintStats(uint8_t id, LL_HsUsart &usart)
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{
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char ids[] = " : ";
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char *buffer = m_buffer;
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LL_HsUsart::Stats const &stats(usart.GetStats());
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ids[0] = id + '0';
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buffer += strcpy_ex(buffer, ids);
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ADDINFO(buffer, " s: ", stats.sent);
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ADDINFO(buffer, " r: ", stats.rcvd);
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ADDINFO(buffer, " sk: ", stats.skiped);
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ADDINFO(buffer, " or: ", stats.overrun);
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ADDINFO(buffer, " he: ", stats.hdrError);
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ADDINFO(buffer, " pe: ", stats.payloadErrror);
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buffer += strcpy_ex(buffer,",0x");
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buffer += uitohex(buffer, stats.pep1, 8);
|
||||
buffer += strcpy_ex(buffer,",0x");
|
||||
buffer += uitohex(buffer, stats.pep2, 8);
|
||||
ADDINFO(buffer, " rde: ", stats.rxDmaError);
|
||||
ADDINFO(buffer, " tde: ", stats.txDmaError);
|
||||
ADDINFO(buffer, " pmh: ", stats.premature_hdr);
|
||||
ADDINFO(buffer, " pmp: ", stats.premature_payload);
|
||||
buffer += strcpy_ex(buffer, "\r\n");
|
||||
|
||||
SetupTransmit(m_buffer, buffer - m_buffer + 1);
|
||||
}
|
||||
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
156
components/f4ll/src/ll_crchandler.cpp
Normal file
156
components/f4ll/src/ll_crchandler.cpp
Normal file
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* ll_crchandler.cpp
|
||||
*
|
||||
* Created on: Oct 26, 2019
|
||||
* Author: compi
|
||||
*/
|
||||
#include "f4ll/ll_crchandler.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
LL_CrcHandler::LL_CrcHandler(DMA_TypeDef *dma, uint32_t stream)
|
||||
: m_dma(dma, stream)
|
||||
{
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
LL_DMA_EnableIT_TE(dma, stream);
|
||||
LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
|
||||
}
|
||||
|
||||
|
||||
void LL_CrcHandler::AttachSlot(SlotBase &slot)
|
||||
{
|
||||
for(unsigned int i = 0; i < slot.m_taskCount; ++i ) {
|
||||
auto &task(slot[i]);
|
||||
task.m_address = nullptr;
|
||||
task.m_wordCount = 0;
|
||||
task.m_callback = nullptr;
|
||||
task.m_callbackParam = 0;
|
||||
}
|
||||
slot.m_next = m_firstSlot;
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
m_firstSlot = &slot;
|
||||
__set_PRIMASK(prim);
|
||||
}
|
||||
|
||||
|
||||
bool LL_CrcHandler::Enqueue(SlotBase &slot, uint8_t prio, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam)
|
||||
{
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
bool immediate;
|
||||
|
||||
// TODO: do we need sanity check here? (is slot attached, is prio in range, etc...?)
|
||||
|
||||
while(IsActive(slot,prio));
|
||||
__disable_irq();
|
||||
immediate = m_activeSlot == nullptr;
|
||||
slot[prio].m_address = (!immediate) ? address : nullptr;
|
||||
slot[prio].m_wordCount = (len+3)/4;
|
||||
slot[prio].m_callback = cb;
|
||||
slot[prio].m_callbackParam = cbParam;
|
||||
if(immediate) {
|
||||
m_activeSlot = &slot;
|
||||
m_activePrio = prio;
|
||||
}
|
||||
__set_PRIMASK(prim);
|
||||
|
||||
if(immediate) {
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(), (uint32_t)address);
|
||||
LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), (len+3)/4);
|
||||
LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
|
||||
}
|
||||
return immediate;
|
||||
}
|
||||
|
||||
bool LL_CrcHandler::IsActive(SlotBase &slot, uint8_t prio) const
|
||||
{
|
||||
return prio < slot.m_taskCount && slot[prio].m_wordCount != 0;
|
||||
}
|
||||
|
||||
bool LL_CrcHandler::IsQueued(SlotBase &slot, uint8_t prio) const
|
||||
{
|
||||
return prio < slot.m_taskCount && slot[prio].m_address != nullptr;
|
||||
}
|
||||
|
||||
bool LL_CrcHandler::IsRunning(SlotBase &slot, uint8_t prio) const
|
||||
{
|
||||
return prio < slot.m_taskCount && slot[prio].m_wordCount && ! slot[prio].m_address;
|
||||
}
|
||||
|
||||
void LL_CrcHandler::DmaTransferCompleted(void)
|
||||
{
|
||||
if(* m_dma.GetIsReg() & m_dma.GetTcMask()) { // DMA transfer complete
|
||||
* m_dma.GetIfcReg() = m_dma.GetTcMask();
|
||||
LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
|
||||
if(m_activeSlot) {
|
||||
if((*m_activeSlot)[m_activePrio].m_callback)
|
||||
(*m_activeSlot)[m_activePrio].m_callback->CrcSucceeded((*m_activeSlot)[m_activePrio].m_callbackParam, CRC->DR, m_activePrio);
|
||||
else if((*m_activeSlot)[m_activePrio].m_callbackParam)
|
||||
*reinterpret_cast<uint32_t*>((*m_activeSlot)[m_activePrio].m_callbackParam) = CRC->DR;
|
||||
}
|
||||
}
|
||||
else if(*m_dma.GetIsReg() & m_dma.GetTeMask()) { // DMA transfer error
|
||||
*m_dma.GetIfcReg() = m_dma.GetTeMask();
|
||||
LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
|
||||
if(m_activeSlot) {
|
||||
if((*m_activeSlot)[m_activePrio].m_callback)
|
||||
(*m_activeSlot)[m_activePrio].m_callback->CrcFailed((*m_activeSlot)[m_activePrio].m_callbackParam, CRC->DR, m_activePrio);
|
||||
else if((*m_activeSlot)[m_activePrio].m_callbackParam)
|
||||
*reinterpret_cast<uint32_t*>((*m_activeSlot)[m_activePrio].m_callbackParam) = -1;
|
||||
}
|
||||
}
|
||||
(*m_activeSlot)[m_activePrio].m_callback = nullptr;
|
||||
(*m_activeSlot)[m_activePrio].m_callbackParam = 0;
|
||||
(*m_activeSlot)[m_activePrio].m_wordCount = 0;
|
||||
StartNextTask();
|
||||
}
|
||||
|
||||
|
||||
void LL_CrcHandler::StartNextTask(void)
|
||||
{
|
||||
bool stillMore;
|
||||
int index = 0;
|
||||
do {
|
||||
SlotBase *slot = m_firstSlot;
|
||||
stillMore = false;
|
||||
while(slot) {
|
||||
if(index < slot->m_taskCount) {
|
||||
if((*slot)[index].m_address) {
|
||||
m_activeSlot = slot;
|
||||
m_activePrio = index;
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(), reinterpret_cast<uint32_t>((*slot)[index].m_address));
|
||||
LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), (*slot)[index].m_wordCount);
|
||||
LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
|
||||
(*slot)[index].m_address = nullptr; // marking as started
|
||||
return;
|
||||
}
|
||||
if(index + 1 < slot->m_taskCount)
|
||||
stillMore = true;
|
||||
}
|
||||
slot = slot->m_next;
|
||||
}
|
||||
++index;
|
||||
} while(stillMore);
|
||||
m_activeSlot = nullptr;
|
||||
}
|
||||
|
||||
|
||||
void LL_CrcHandler::WaitResults(SlotBase &slot, uint8_t prio) const
|
||||
{
|
||||
while(IsQueued(slot, prio));
|
||||
while(IsActive(slot, prio));
|
||||
}
|
||||
|
||||
|
||||
uint32_t LL_CrcHandler::Compute(
|
||||
SlotBase &slot, uint8_t prio, void const *address, uint16_t len)
|
||||
{
|
||||
uint32_t result;
|
||||
Enqueue(slot, prio, address, len, nullptr, reinterpret_cast<uintptr_t>(&result));
|
||||
while(IsActive(slot, prio));
|
||||
return result;
|
||||
}
|
||||
|
||||
} // namespace f4ll
|
26
components/f4ll/src/ll_dmahelper.cpp
Normal file
26
components/f4ll/src/ll_dmahelper.cpp
Normal file
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
q * ll_dmahelper.cpp
|
||||
*
|
||||
* Created on: Oct 25, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#include "f4ll/ll_dmahelper.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
const uint32_t LL_DmaHelper::m_FEMasks[8] = {DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7};
|
||||
const uint32_t LL_DmaHelper::m_DMEMasks[8] = {DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7};
|
||||
const uint32_t LL_DmaHelper::m_TEMasks[8] = {DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7};
|
||||
const uint32_t LL_DmaHelper::m_HTMasks[8] = {DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7};
|
||||
const uint32_t LL_DmaHelper::m_TCMasks[8] = {DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7};
|
||||
|
||||
LL_DmaHelper::LL_DmaHelper(DMA_TypeDef *dma, uint32_t stream)
|
||||
: m_dma(dma)
|
||||
, m_stream(stream)
|
||||
, m_isReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR))
|
||||
, m_ifcReg((dma == DMA1) ? ((m_stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR) : ((m_stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR))
|
||||
{
|
||||
}
|
||||
|
||||
} /* namespace f4ll */
|
237
components/f4ll/src/ll_hsusart.cpp
Normal file
237
components/f4ll/src/ll_hsusart.cpp
Normal file
|
@ -0,0 +1,237 @@
|
|||
/*
|
||||
* ll_hsusart_impl.h
|
||||
*
|
||||
* Created on: Oct 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include <string.h>
|
||||
#include "f4ll/ll_hsusart.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
template<typename T> static inline T RoundUpTo4(T input)
|
||||
{
|
||||
return (input + 3) & (((T)-1) - 3);
|
||||
}
|
||||
|
||||
|
||||
LL_HsUsart::LL_HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
: LL_UsartCore(usart, dma, streamRx, streamTx)
|
||||
{
|
||||
LL_CrcHandler::Instance().AttachSlot(m_crcSlot);
|
||||
}
|
||||
|
||||
|
||||
uint8_t *LL_HsUsart::GetTxPacketBuffer(void)
|
||||
{
|
||||
return m_txBuffer.packet.payload;
|
||||
}
|
||||
|
||||
|
||||
USART_TypeDef* LL_HsUsart::GetUsart(void)
|
||||
{
|
||||
return m_usart;
|
||||
}
|
||||
|
||||
|
||||
LL_HsUsart::Stats const & LL_HsUsart::GetStats(void)
|
||||
{
|
||||
return m_stats;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::IsTxBusy()
|
||||
{
|
||||
return m_txBuffer.busy;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::IsTxFailed()
|
||||
{
|
||||
return m_txBuffer.error;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::IsRxBusy(bool second)
|
||||
{
|
||||
return m_rxBuffers[second].busy;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::IsRxFailed(bool second)
|
||||
{
|
||||
return m_rxBuffers[second].error;
|
||||
|
||||
}
|
||||
|
||||
void LL_HsUsart::RxProcessed(bool second)
|
||||
{
|
||||
m_rxBuffers[second].busy = false;
|
||||
m_rxBuffers[second].error = false;
|
||||
}
|
||||
|
||||
void LL_HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
|
||||
{
|
||||
m_userCallback = callback;
|
||||
m_userCallbackParam = callbackParam;
|
||||
}
|
||||
|
||||
void LL_HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
|
||||
{
|
||||
uint8_t hash = STARTMARKER;
|
||||
|
||||
packet.header.startByte = STARTMARKER;
|
||||
packet.header.serial = serialNo;
|
||||
hash ^= serialNo;
|
||||
packet.header.payloadLength = length;
|
||||
hash ^= length;
|
||||
packet.header.hash = hash;
|
||||
}
|
||||
|
||||
|
||||
bool LL_HsUsart::CheckHeader(PacketHeader &header)
|
||||
{
|
||||
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
|
||||
{
|
||||
uint16_t payloadLength = RoundUpTo4((uint16_t)length);
|
||||
|
||||
BuildHeader(m_txBuffer.packet, m_txSerialNo++, length);
|
||||
if(payload)
|
||||
memcpy(m_txBuffer.packet.payload, payload, length);
|
||||
m_txBuffer.requestedLength = sizeof(m_txBuffer.packet.header) + payloadLength + sizeof(uint32_t);
|
||||
m_txBuffer.busy = true;
|
||||
m_txBuffer.error = false;
|
||||
|
||||
LL_CrcHandler::Instance().Enqueue(m_crcSlot, 0, &m_txBuffer.packet, sizeof(PacketHeader) + payloadLength,
|
||||
nullptr, reinterpret_cast<uintptr_t>(m_txBuffer.packet.payload + payloadLength));
|
||||
|
||||
while(waitForCrcQueue && LL_CrcHandler::Instance().IsQueued(m_crcSlot, 0));
|
||||
|
||||
SetupTransmit(&m_txBuffer.packet, m_txBuffer.requestedLength);
|
||||
|
||||
++m_stats.sent;
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::SetupReceive()
|
||||
{
|
||||
m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
|
||||
LL_UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::ReceiverIdle(void)
|
||||
{
|
||||
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
if(rcvdLen >= sizeof(PacketHeader)) {
|
||||
if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
|
||||
if(rcvdLen >= sizeof(PacketHeader) +
|
||||
RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength)
|
||||
+ sizeof(uint32_t))
|
||||
LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
else
|
||||
++m_stats.premature_payload;
|
||||
} else {
|
||||
m_rxBuffers[m_rxBufferSelector].error = 1;
|
||||
LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
}
|
||||
} else
|
||||
++m_stats.premature_hdr;
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::TransmissionComplete(void)
|
||||
{
|
||||
LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(m_usart);
|
||||
m_txBuffer.busy = 0;
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::RxDmaTransferComplete(void)
|
||||
{
|
||||
if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
|
||||
LL_CrcHandler::Instance().Enqueue(m_crcSlot, 1,
|
||||
&m_rxBuffers[m_rxBufferSelector].packet,
|
||||
sizeof(PacketHeader) + RoundUpTo4((uint16_t)m_rxBuffers[m_rxBufferSelector].packet.header.payloadLength),
|
||||
this, m_rxBufferSelector);
|
||||
else {
|
||||
++m_stats.hdrError;
|
||||
m_rxBuffers[m_rxBufferSelector].error = true;
|
||||
}
|
||||
SwitchRxBuffers();
|
||||
}
|
||||
|
||||
void LL_HsUsart::RxDmaHalfTransfer(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::RxDmaError(LL_DmaHelper::DmaErrorType reason)
|
||||
{
|
||||
m_rxBuffers[m_rxBufferSelector].error = 1;
|
||||
++m_stats.rxDmaError;
|
||||
SwitchRxBuffers();
|
||||
}
|
||||
|
||||
void LL_HsUsart::TxDmaTransferComplete(void)
|
||||
{
|
||||
LL_USART_EnableIT_TC(m_usart);
|
||||
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::TxDmaHalfTransfer(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::TxDmaError(LL_DmaHelper::DmaErrorType reason)
|
||||
{
|
||||
m_txBuffer.error = 1;
|
||||
++m_stats.txDmaError;
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::SwitchRxBuffers(void)
|
||||
{
|
||||
++m_stats.rcvd;
|
||||
m_rxBufferSelector = !m_rxBufferSelector;
|
||||
|
||||
if(m_rxBuffers[m_rxBufferSelector].busy)
|
||||
++m_stats.overrun;
|
||||
SetupReceive();
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, int prio)
|
||||
{
|
||||
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
|
||||
|
||||
buf.busy = 1;
|
||||
if(*(uint32_t*) (buf.packet.payload + RoundUpTo4((uint16_t)buf.packet.header.payloadLength)) != crc) {
|
||||
buf.error = 1;
|
||||
buf.errorInfo = crc;
|
||||
++m_stats.payloadErrror;
|
||||
}
|
||||
if(m_userCallback)
|
||||
buf.busy = !m_userCallback->PacketReceived(this, m_userCallbackParam, buf.packet);
|
||||
}
|
||||
|
||||
|
||||
void LL_HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, int prio)
|
||||
{
|
||||
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
|
||||
buf.busy = buf.error = true;
|
||||
buf.errorInfo = 0;
|
||||
++m_stats.payloadErrror;
|
||||
if(m_userCallback)
|
||||
buf.busy = !m_userCallback->PacketReceived(this, m_userCallbackParam, buf.packet);
|
||||
}
|
||||
|
||||
|
||||
} // namespace f4ll
|
37
components/f4ll/src/ll_memcpydma.cpp
Normal file
37
components/f4ll/src/ll_memcpydma.cpp
Normal file
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* llmemcpydma.cpp
|
||||
*
|
||||
* Created on: Nov 4, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#include "f4ll/ll_memcpydma.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
LL_MemcpyDma::LL_MemcpyDma(DMA_TypeDef *dma, uint32_t stream)
|
||||
: LL_DmaHelper(dma, stream)
|
||||
{
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
}
|
||||
|
||||
void* LL_MemcpyDma::Copy(void *dst, void const *src, uint16_t length)
|
||||
{
|
||||
LL_DMA_SetM2MSrcAddress(GetDma(), GetStream(), (uint32_t)src);
|
||||
LL_DMA_SetM2MDstAddress(GetDma(), GetStream(), (uint32_t)dst);
|
||||
LL_DMA_SetDataLength(GetDma(), GetStream(), (length+3)/4 );
|
||||
m_busy = 1;
|
||||
LL_DMA_EnableStream(GetDma(), GetStream());
|
||||
while(m_busy);
|
||||
return dst;
|
||||
}
|
||||
|
||||
void LL_MemcpyDma::DmaTransferCompleted()
|
||||
{
|
||||
if(*GetIsReg() & GetTcMask()) { // DMA transfer complete
|
||||
*GetIfcReg() = GetTcMask();
|
||||
LL_DMA_DisableStream(GetDma(), GetStream());
|
||||
m_busy = 0;
|
||||
}
|
||||
}
|
||||
} /* namespace f4ll */
|
116
components/f4ll/src/ll_usartcore.cpp
Normal file
116
components/f4ll/src/ll_usartcore.cpp
Normal file
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* ll_dmadrivenusartcore.cpp
|
||||
*
|
||||
* Created on: Nov 4, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#include "f4ll/ll_usartcore.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
LL_UsartCore::LL_UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
|
||||
: m_usart(usart)
|
||||
, m_rxDma(dma, streamRx)
|
||||
, m_txDma(dma, streamTx)
|
||||
{
|
||||
LL_DMA_EnableIT_TC(dma, streamRx);
|
||||
LL_DMA_EnableIT_TE(dma, streamRx);
|
||||
LL_DMA_EnableIT_TC(dma, streamTx);
|
||||
LL_DMA_EnableIT_TE(dma, streamTx);
|
||||
LL_USART_EnableIT_IDLE(usart);
|
||||
}
|
||||
|
||||
void LL_UsartCore::UsartIsr()
|
||||
{
|
||||
if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(m_usart);
|
||||
ReceiverIdle();
|
||||
} else if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(m_usart);
|
||||
TransmissionComplete();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::RxDmaIsr()
|
||||
{
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
|
||||
if(m_rxDma.IsEnabledIt_TC())
|
||||
RxDmaTransferComplete();
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetHtMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetHtMask();
|
||||
if(m_rxDma.IsEnabledIt_HT())
|
||||
RxDmaHalfTransfer();
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
|
||||
if(m_rxDma.IsEnabledIt_TE())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::Transfer);
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetFeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetFeMask();
|
||||
if(m_rxDma.IsEnabledIt_FE())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::Fifo);
|
||||
}
|
||||
if(*m_rxDma.GetIsReg() & m_rxDma.GetDmeMask()) {
|
||||
*m_rxDma.GetIfcReg() = m_rxDma.GetDmeMask();
|
||||
if(m_rxDma.IsEnabledIt_DME())
|
||||
RxDmaError(LL_DmaHelper::DmaErrorType::DirectMode);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::TxDmaIsr()
|
||||
{
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
|
||||
if(m_txDma.IsEnabledIt_TC())
|
||||
TxDmaTransferComplete();
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetHtMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetHtMask();
|
||||
if(m_txDma.IsEnabledIt_HT())
|
||||
TxDmaHalfTransfer();
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
|
||||
if(m_txDma.IsEnabledIt_TE())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::Transfer);
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetFeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
|
||||
if(m_txDma.IsEnabledIt_FE())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::Fifo);
|
||||
}
|
||||
if(*m_txDma.GetIsReg() & m_txDma.GetDmeMask()) {
|
||||
*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
|
||||
if(m_txDma.IsEnabledIt_DME())
|
||||
TxDmaError(LL_DmaHelper::DmaErrorType::DirectMode);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::SetupTransmit(void const *buffer, uint16_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(m_txDma.GetDma(), m_txDma.GetStream(), reinterpret_cast<uint32_t>(buffer),
|
||||
LL_USART_DMA_GetRegAddr(m_usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_SetDataLength(m_txDma.GetDma(), m_txDma.GetStream(), length);
|
||||
LL_USART_EnableDMAReq_TX(m_usart);
|
||||
LL_DMA_EnableStream(m_txDma.GetDma(), m_txDma.GetStream());
|
||||
}
|
||||
|
||||
|
||||
void LL_UsartCore::SetupReceive(void *buffer, uint16_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(m_rxDma.GetDma(), m_rxDma.GetStream(), LL_USART_DMA_GetRegAddr(m_usart),
|
||||
reinterpret_cast<uint32_t>(buffer), LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
||||
LL_DMA_SetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream(), length);
|
||||
LL_USART_EnableDMAReq_RX(m_usart);
|
||||
LL_USART_ClearFlag_ORE(m_usart);
|
||||
LL_DMA_EnableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
|
||||
}
|
||||
|
||||
} /* namespace f4ll */
|
11
components/f4ll_c/component.mk
Normal file
11
components/f4ll_c/component.mk
Normal file
|
@ -0,0 +1,11 @@
|
|||
#encoder
|
||||
SELF_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
|
||||
REL_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
|
||||
ifeq ($(MKDBG), 1)
|
||||
$(info >>> $(REL_DIR)/component.mk)
|
||||
endif
|
||||
$(eval C_INCLUDES += -I$(REL_DIR)/inc)
|
||||
$(eval C_SOURCES += $(wildcard $(REL_DIR)/src/*.c))
|
||||
ifeq ($(MKDBG), 1)
|
||||
$(info <<<)
|
||||
endif
|
19
components/f4ll_c/inc/console_handler.h
Normal file
19
components/f4ll_c/inc/console_handler.h
Normal file
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* interrupt.h
|
||||
*
|
||||
* Created on: Aug 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef INTERRUPT_HANDLERS_H_
|
||||
#define INTERRUPT_HANDLERS_H_
|
||||
|
||||
#include "usart.h"
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
|
||||
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart);
|
||||
void HandleConsoleUsartIrq(USART_TypeDef *usart);
|
||||
|
||||
void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo);
|
||||
|
||||
#endif /* INTERRUPT_HANDLERS_H_ */
|
53
components/f4ll_c/inc/crc_handler.h
Normal file
53
components/f4ll_c/inc/crc_handler.h
Normal file
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* interrupt.h
|
||||
*
|
||||
* Created on: Aug 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef CRC_HANDLER_H_
|
||||
#define CRC_HANDLER_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#ifdef HAVE_CONFIG
|
||||
#include "config.h"
|
||||
#endif // HAVE_CONFIG
|
||||
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
|
||||
#ifndef CRCTASKCOUNT
|
||||
#define CRCTASKCOUNT 2
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
DMAINFO dmaInfo;
|
||||
volatile uint8_t activeSlot;
|
||||
struct crctask_t {
|
||||
void *address;
|
||||
uint16_t wordCount;
|
||||
void (*callback)(void*, uint32_t, uint8_t);
|
||||
void *callbackParam;
|
||||
} volatile crcTasks[CRCTASKCOUNT];
|
||||
} CRCSTATUS;
|
||||
|
||||
void InitCrcStatus(CRCSTATUS *status, DMA_TypeDef *dma, uint32_t stream);
|
||||
static inline uint8_t GetActiveSlot(CRCSTATUS *status) {
|
||||
return status->activeSlot;
|
||||
}
|
||||
static inline uint8_t IsSlotQueued(CRCSTATUS *status, uint8_t slot) {
|
||||
return status->crcTasks[slot].address != NULL;
|
||||
}
|
||||
static inline uint8_t IsSlotActive(CRCSTATUS *status, uint8_t slot) {
|
||||
return status->crcTasks[slot].callback != NULL || status->crcTasks[slot].callbackParam != NULL;
|
||||
}
|
||||
uint8_t EnqueueCrcTask(CRCSTATUS *crcStatus, uint8_t slot, uint8_t *address, uint16_t len,
|
||||
void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
|
||||
void WaitCrcResults(CRCSTATUS *status, uint8_t slot);
|
||||
uint32_t ComputeCrc(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len);
|
||||
void ComputeCrcAsync(CRCSTATUS *status, uint8_t slot,
|
||||
uint8_t *address, uint16_t len,
|
||||
void (*callback)(void*, uint32_t, uint8_t), void* callbackParam);
|
||||
void HandleCrcDmaIrq(CRCSTATUS *status);
|
||||
|
||||
#endif /* CRC_HANDLER_H_ */
|
34
components/f4ll_c/inc/dma_helper.h
Normal file
34
components/f4ll_c/inc/dma_helper.h
Normal file
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* dma_helper.h
|
||||
*
|
||||
* Created on: Sep 18, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef DMA_HELPER_H_
|
||||
#define DMA_HELPER_H_
|
||||
#include <inttypes.h>
|
||||
#include <platform/dma_ll.h>
|
||||
|
||||
typedef struct {
|
||||
DMA_TypeDef *dma;
|
||||
uint32_t stream;
|
||||
volatile uint32_t *isReg;
|
||||
volatile uint32_t *ifcReg;
|
||||
uint32_t feMask;
|
||||
uint32_t dmeMask;
|
||||
uint32_t teMask;
|
||||
uint32_t htMask;
|
||||
uint32_t tcMask;
|
||||
} DMAINFO;
|
||||
|
||||
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream);
|
||||
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream);
|
||||
uint32_t GetDmeMask(uint32_t stream);
|
||||
uint32_t GetTeMask(uint32_t stream);
|
||||
uint32_t GetHtMask(uint32_t stream);
|
||||
uint32_t GetTcMask(uint32_t stream);
|
||||
|
||||
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream);
|
||||
|
||||
#endif /* DMA_HELPER_H_ */
|
1
components/f4ll_c/inc/f4ll_c
Symbolic link
1
components/f4ll_c/inc/f4ll_c
Symbolic link
|
@ -0,0 +1 @@
|
|||
.
|
18
components/f4ll_c/inc/memcpy_dma.h
Normal file
18
components/f4ll_c/inc/memcpy_dma.h
Normal file
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* memcpy_dma.h
|
||||
*
|
||||
* Created on: Oct 1, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef MEMCPY_DMA_H_
|
||||
#define MEMCPY_DMA_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <platform/dma_ll.h>
|
||||
|
||||
void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream);
|
||||
void * MemcpyDma(void *dst, void const *src, size_t length);
|
||||
void HandleMemcpyDmaIrq();
|
||||
|
||||
#endif /* MEMCPY_DMA_H_ */
|
31
components/f4ll_c/inc/strutil.h
Normal file
31
components/f4ll_c/inc/strutil.h
Normal file
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* strutil.h
|
||||
*
|
||||
* Created on: Feb 11, 2017
|
||||
* Author: compi
|
||||
*/
|
||||
|
||||
#ifndef _STM32PLUS_STRUTIL_H_
|
||||
#define _STM32PLUS_STRUTIL_H_
|
||||
|
||||
#include <stddef.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t strcpy_ex(char *dst, char const *src);
|
||||
size_t uitodec(char* buffer, uint32_t data);
|
||||
size_t uitohex(char* buffer, uint32_t data, uint8_t chars);
|
||||
size_t itodec(char* buffer, int data);
|
||||
size_t itohex(char* buffer, int data);
|
||||
void strrev(char *first, char *last);
|
||||
char tochr(const uint8_t in, const uint8_t upper);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _STM32PLUS_STRUTIL_H_ */
|
142
components/f4ll_c/inc/usart_handler.h
Normal file
142
components/f4ll_c/inc/usart_handler.h
Normal file
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* usart_handler.h
|
||||
*
|
||||
* Created on: Sep 16, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef USART_HANDLER_H_
|
||||
#define USART_HANDLER_H_
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
#include "f4ll_c/crc_handler.h"
|
||||
|
||||
struct _usart_status;
|
||||
typedef struct _usart_status USARTSTATUS;
|
||||
struct usart_buffer;
|
||||
|
||||
typedef void (*PACKETRECEIVEDCALLBACK)(void *userParam, struct usart_buffer *buffer);
|
||||
|
||||
void InitUartStatus(
|
||||
USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
|
||||
uint32_t stream_rx, uint32_t stream_tx,
|
||||
CRCSTATUS *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot,
|
||||
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam);
|
||||
|
||||
uint8_t* GetTxBuffer(USARTSTATUS *status);
|
||||
|
||||
uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, CRCSTATUS *crcStatus);
|
||||
void SetupReceive(USARTSTATUS *status);
|
||||
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length);
|
||||
void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex, CRCSTATUS *crcStatus);
|
||||
|
||||
void HandleUsartRxDmaIrq(USARTSTATUS *status);
|
||||
void HandleUsartTxDmaIrq(USARTSTATUS *status);
|
||||
void HandleUsartIrq(USARTSTATUS *status);
|
||||
|
||||
/******************************************************************************************
|
||||
*
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
struct usart_stats {
|
||||
uint32_t overrun;
|
||||
uint32_t hdrError;
|
||||
uint32_t lastErrHdr;
|
||||
uint32_t payloadErrror;
|
||||
uint32_t pep1, pep2;
|
||||
uint32_t dmaError;
|
||||
uint32_t rcvd;
|
||||
uint32_t premature_hdr;
|
||||
uint32_t premature_payload;
|
||||
uint32_t sent;
|
||||
uint32_t skiped;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
uint8_t startByte;
|
||||
uint8_t serial;
|
||||
uint8_t payloadLength;
|
||||
uint8_t hash;
|
||||
} USARTPACKETHEADER;
|
||||
|
||||
typedef struct {
|
||||
USARTPACKETHEADER header;
|
||||
//!!! should start on word offset !!!
|
||||
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
|
||||
} __attribute__((aligned)) USARTPACKET;
|
||||
|
||||
struct usart_buffer {
|
||||
USARTPACKET packet;
|
||||
//transfer area ends here
|
||||
volatile uint8_t busy;
|
||||
volatile uint8_t error;
|
||||
uint16_t requestedLength;
|
||||
uint32_t errorInfo;
|
||||
USARTSTATUS *usartStatus;
|
||||
};
|
||||
|
||||
struct _usart_status {
|
||||
USART_TypeDef *usart;
|
||||
DMAINFO rxDmaInfo;
|
||||
DMAINFO txDmaInfo;
|
||||
CRCSTATUS *crcStatus;
|
||||
uint8_t rxSerial;
|
||||
uint8_t txSerial;
|
||||
struct usart_stats stats;
|
||||
uint8_t activeRxBuf;
|
||||
uint8_t rxCrcSlot;
|
||||
uint8_t txCrcSlot;
|
||||
PACKETRECEIVEDCALLBACK packetReceivedCallback;
|
||||
void *packetReceivedCallbacParam;
|
||||
struct usart_buffer txBuffer;
|
||||
struct usart_buffer rxBuffers[2];
|
||||
};
|
||||
|
||||
#ifndef USART_STATS_DISABLED
|
||||
static inline void StatsIncOverrun(struct usart_stats *s) {
|
||||
++s->overrun;
|
||||
}
|
||||
static inline void StatsIncHdrError(struct usart_stats *s, uint32_t hdr) {
|
||||
++s->hdrError;
|
||||
s->lastErrHdr = hdr;
|
||||
}
|
||||
static inline void StatsIncPayloadError(struct usart_stats *s, uint32_t pep1, uint32_t pep2) {
|
||||
++s->payloadErrror;
|
||||
s->pep1 = pep1;
|
||||
s->pep2 = pep2;
|
||||
}
|
||||
static inline void StatsIncDmaError(struct usart_stats *s) {
|
||||
++s->dmaError;
|
||||
}
|
||||
static inline void StatsIncRcvd(struct usart_stats *s) {
|
||||
++s->rcvd;
|
||||
}
|
||||
static inline void StatsIncPremature_hdr(struct usart_stats *s) {
|
||||
++s->premature_hdr;
|
||||
}
|
||||
static inline void StatsIncPremature_payload(struct usart_stats *s) {
|
||||
++s->premature_payload;
|
||||
}
|
||||
static inline void StatsIncSent(struct usart_stats *s) {
|
||||
++s->sent;
|
||||
}
|
||||
static inline void StatsAddSkiped(struct usart_stats *s, uint8_t cnt) {
|
||||
s->skiped += s->rcvd > 2 ? cnt : 0;
|
||||
}
|
||||
|
||||
#else // USART_STATS_DISABLED
|
||||
#define StatsIncOverrun(x)
|
||||
#define StatsIncHdrError(x,y)
|
||||
#define StatsIncPayloadError(x,y,z)
|
||||
#define StatsIncDmaError(x)
|
||||
#define StatsIncRcvd(x)
|
||||
#define StatsIncPremature_hdr(x)
|
||||
#define StatsIncPremature_payload(x)
|
||||
#define StatsIncSent(x)
|
||||
#define StatsAddSkiped(x)
|
||||
#endif // USART_STATS_DISABLED
|
||||
|
||||
#endif /* UART_HANDLER_H_ */
|
68
components/f4ll_c/src/console_handler.c
Normal file
68
components/f4ll_c/src/console_handler.c
Normal file
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* interrupt.c
|
||||
*
|
||||
* Created on: Aug 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include "main.h"
|
||||
#include "globals.h"
|
||||
#include "f4ll_c/usart_handler.h"
|
||||
#include "f4ll_c/strutil.h"
|
||||
|
||||
#ifndef DIAG_INTERRUPT_IN
|
||||
# define DIAG_INTERRUPT_IN()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_INTERRUPT_OUT
|
||||
# define DIAG_INTERRUPT_OUT()
|
||||
#endif
|
||||
|
||||
void HandleConsoleUsartTxDmaIrq(DMAINFO *info, USART_TypeDef *usart) // debug usart
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*info->isReg & info->tcMask) { // DMA transfer complete
|
||||
*info->ifcReg = info->tcMask;
|
||||
LL_USART_EnableIT_TC(usart);
|
||||
LL_DMA_DisableStream(info->dma, info->stream);
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleConsoleUsartIrq(USART_TypeDef *usart)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(LL_USART_IsActiveFlag_TC(usart) && LL_USART_IsEnabledIT_TC(usart)) // transmission complete
|
||||
LL_USART_DisableIT_TC(usart);
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
#define ADDINFO(b,s,u) \
|
||||
b += strcpy_ex(b,s); \
|
||||
b += uitodec(b,u);
|
||||
|
||||
void PrintStats(char *buffer, uint8_t id, struct usart_stats *stats, USART_TypeDef *usart, DMAINFO *dmaInfo)
|
||||
{
|
||||
char ids[] = " : ";
|
||||
char *bs = buffer;
|
||||
|
||||
ids[0] = id + '0';
|
||||
buffer += strcpy_ex(buffer, ids);
|
||||
ADDINFO(buffer, " s: ", stats->sent);
|
||||
ADDINFO(buffer, " r: ", stats->rcvd);
|
||||
ADDINFO(buffer, " sk: ", stats->skiped);
|
||||
ADDINFO(buffer, " or: ", stats->overrun);
|
||||
ADDINFO(buffer, " he: ", stats->hdrError);
|
||||
buffer += strcpy_ex(buffer,",0x");
|
||||
buffer += uitohex(buffer, stats->lastErrHdr, 8);
|
||||
ADDINFO(buffer, " pe: ", stats->payloadErrror);
|
||||
buffer += strcpy_ex(buffer,",0x");
|
||||
buffer += uitohex(buffer, stats->pep1, 8);
|
||||
buffer += strcpy_ex(buffer,",0x");
|
||||
buffer += uitohex(buffer, stats->pep2, 8);
|
||||
ADDINFO(buffer, " de: ", stats->dmaError);
|
||||
ADDINFO(buffer, " pmh: ", stats->premature_hdr);
|
||||
ADDINFO(buffer, " pmp: ", stats->premature_payload);
|
||||
buffer += strcpy_ex(buffer, "\r\n");
|
||||
|
||||
SetupTransmit(usart, dmaInfo->dma, dmaInfo->stream, bs, buffer - bs + 1);
|
||||
}
|
132
components/f4ll_c/src/crc_handler.c
Normal file
132
components/f4ll_c/src/crc_handler.c
Normal file
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* interrupt.c
|
||||
*
|
||||
* Created on: Aug 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include <string.h>
|
||||
#include <platform/crc_ll.h>
|
||||
#include "diag.h"
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
#include "f4ll_c/crc_handler.h"
|
||||
|
||||
#ifndef DIAG_CRC_CALC_START
|
||||
# define DIAG_CRC_CALC_START()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_CRC_CALC_END
|
||||
# define DIAG_CRC_CALC_END()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_INTERRUPT_IN
|
||||
# define DIAG_INTERRUPT_IN()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_INTERRUPT_OUT
|
||||
# define DIAG_INTERRUPT_OUT()
|
||||
#endif
|
||||
|
||||
|
||||
void InitCrcStatus(CRCSTATUS *st, DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
InitDmaInfo(&st->dmaInfo, dma, stream);
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
LL_DMA_EnableIT_TE(dma, stream);
|
||||
LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
|
||||
st->activeSlot = 0xff;
|
||||
memset((void*)st->crcTasks, 0, sizeof(st->crcTasks));
|
||||
}
|
||||
|
||||
uint8_t EnqueueCrcTask(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len,
|
||||
void (*callback)(void*, uint32_t, uint8_t), void* callbackParam)
|
||||
{
|
||||
uint32_t prim = __get_PRIMASK();
|
||||
uint16_t need_start;
|
||||
|
||||
while(status->activeSlot == slot);
|
||||
__disable_irq();
|
||||
need_start = (status->activeSlot == 0xff);
|
||||
status->crcTasks[slot].address = need_start ? NULL : address;
|
||||
status->crcTasks[slot].wordCount = (len+3)/4;
|
||||
status->crcTasks[slot].callback = callback;
|
||||
status->crcTasks[slot].callbackParam = callbackParam;
|
||||
if(need_start)
|
||||
status->activeSlot = slot;
|
||||
__set_PRIMASK(prim);
|
||||
|
||||
if(need_start) {
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)address);
|
||||
LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, (len+3)/4);
|
||||
DIAG_CRC_CALC_START();
|
||||
LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
|
||||
}
|
||||
return need_start;
|
||||
}
|
||||
|
||||
void WaitCrcResults(CRCSTATUS *status, uint8_t slot)
|
||||
{
|
||||
while(IsSlotQueued(status, slot));
|
||||
while(GetActiveSlot(status) == slot);
|
||||
}
|
||||
|
||||
uint32_t ComputeCrc(CRCSTATUS *status, uint8_t slot, uint8_t *address, uint16_t len)
|
||||
{
|
||||
uint32_t result;
|
||||
EnqueueCrcTask(status, slot, address, len, NULL, &result);
|
||||
while(status->crcTasks[slot].callbackParam);
|
||||
return result;
|
||||
}
|
||||
|
||||
void StartNextCrcTask(CRCSTATUS *status)
|
||||
{
|
||||
uint16_t slot;
|
||||
for(slot = 0; slot < CRCTASKCOUNT; ++slot)
|
||||
if(status->crcTasks[slot].address) {
|
||||
status->activeSlot = slot;
|
||||
CRC->CR = 1;
|
||||
LL_DMA_SetM2MSrcAddress(status->dmaInfo.dma, status->dmaInfo.stream, (uint32_t)status->crcTasks[slot].address);
|
||||
LL_DMA_SetDataLength(status->dmaInfo.dma, status->dmaInfo.stream, status->crcTasks[slot].wordCount);
|
||||
DIAG_CRC_CALC_START();
|
||||
LL_DMA_EnableStream(status->dmaInfo.dma, status->dmaInfo.stream);
|
||||
status->crcTasks[slot].address = NULL; // marking as started
|
||||
return;
|
||||
}
|
||||
|
||||
status->activeSlot = 0xff;
|
||||
}
|
||||
|
||||
void HandleCrcDmaIrq(CRCSTATUS *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*status->dmaInfo.isReg & status->dmaInfo.tcMask) { // DMA transfer complete
|
||||
*status->dmaInfo.ifcReg = status->dmaInfo.tcMask;
|
||||
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
|
||||
if(status->activeSlot != 0xff) {
|
||||
struct crctask_t *tsk = (struct crctask_t *)&status->crcTasks[status->activeSlot];
|
||||
if(tsk->callback)
|
||||
tsk->callback(tsk->callbackParam, CRC->DR, 1);
|
||||
else if(tsk->callbackParam)
|
||||
*(uint32_t*)tsk->callbackParam = CRC->DR;
|
||||
tsk->callback = tsk->callbackParam = NULL; // marking as inactive
|
||||
DIAG_CRC_CALC_END();
|
||||
StartNextCrcTask(status);
|
||||
}
|
||||
}
|
||||
else if(*status->dmaInfo.isReg & status->dmaInfo.teMask) {
|
||||
*status->dmaInfo.ifcReg = status->dmaInfo.teMask;
|
||||
LL_DMA_DisableStream(status->dmaInfo.dma, status->dmaInfo.stream);
|
||||
if(status->activeSlot != 0xff) {
|
||||
struct crctask_t *tsk = (struct crctask_t *)&status->crcTasks[status->activeSlot];
|
||||
if(tsk->callback)
|
||||
tsk->callback(tsk->callbackParam, CRC->DR, 0);
|
||||
else if(tsk->callbackParam)
|
||||
*(uint32_t*)tsk->callbackParam = 0xffffffff;
|
||||
tsk->callback = tsk->callbackParam = NULL; // marking as inactive
|
||||
DIAG_CRC_CALC_END();
|
||||
StartNextCrcTask(status);
|
||||
}
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
78
components/f4ll_c/src/dma_helper.c
Normal file
78
components/f4ll_c/src/dma_helper.c
Normal file
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* dma_helper.c
|
||||
*
|
||||
* Created on: Sep 18, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
|
||||
|
||||
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
if(dma == DMA1)
|
||||
return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR;
|
||||
else
|
||||
return (stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR;
|
||||
}
|
||||
|
||||
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
if(dma == DMA1)
|
||||
return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR;
|
||||
else
|
||||
return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR;
|
||||
}
|
||||
|
||||
uint32_t GetFeMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t feMasks[8] = {
|
||||
DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7
|
||||
};
|
||||
return feMasks[stream];
|
||||
}
|
||||
|
||||
uint32_t GetDmeMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t dmeMasks[8] = {
|
||||
DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7
|
||||
};
|
||||
return dmeMasks[stream];
|
||||
}
|
||||
|
||||
uint32_t GetTeMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t teMasks[8] = {
|
||||
DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7
|
||||
};
|
||||
return teMasks[stream];
|
||||
}
|
||||
|
||||
uint32_t GetHtMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t htMasks[8] = {
|
||||
DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7
|
||||
};
|
||||
return htMasks[stream];
|
||||
}
|
||||
|
||||
uint32_t GetTcMask(uint32_t stream)
|
||||
{
|
||||
static const uint32_t tcMasks[8] = {
|
||||
DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7
|
||||
};
|
||||
|
||||
return tcMasks[stream];
|
||||
}
|
||||
|
||||
void InitDmaInfo(DMAINFO *info, DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
info->dma = dma;
|
||||
info->stream = stream;
|
||||
info->isReg = GetIsReg(dma, stream);
|
||||
info->ifcReg = GetIfcReg(dma, stream);
|
||||
info->feMask = GetFeMask(stream);
|
||||
info->dmeMask = GetDmeMask(stream);
|
||||
info->teMask = GetTeMask(stream);
|
||||
info->htMask = GetHtMask(stream);
|
||||
info->tcMask = GetTcMask(stream);
|
||||
}
|
48
components/f4ll_c/src/memcpy_dma.c
Normal file
48
components/f4ll_c/src/memcpy_dma.c
Normal file
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* memcpy_dma.c
|
||||
*
|
||||
* Created on: Oct 1, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
#include "f4ll_c/memcpy_dma.h"
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
|
||||
#ifndef DIAG_INTERRUPT_IN
|
||||
# define DIAG_INTERRUPT_IN()
|
||||
#endif
|
||||
|
||||
#ifndef DIAG_INTERRUPT_OUT
|
||||
# define DIAG_INTERRUPT_OUT()
|
||||
#endif
|
||||
|
||||
volatile uint8_t g_memcpyDmaBusy = 0;
|
||||
|
||||
static DMAINFO g_memcpyDmaInfo;
|
||||
|
||||
void InitMemcpyDma(DMA_TypeDef *dma, uint32_t stream)
|
||||
{
|
||||
InitDmaInfo(&g_memcpyDmaInfo, dma, stream);
|
||||
LL_DMA_EnableIT_TC(dma, stream);
|
||||
}
|
||||
|
||||
void * MemcpyDma(void *dst, void const *src, size_t length)
|
||||
{
|
||||
LL_DMA_SetM2MSrcAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)src);
|
||||
LL_DMA_SetM2MDstAddress(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (uint32_t)dst);
|
||||
LL_DMA_SetDataLength(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream, (length+3)/4 );
|
||||
g_memcpyDmaBusy = 1;
|
||||
LL_DMA_EnableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
|
||||
while(g_memcpyDmaBusy);
|
||||
return dst;
|
||||
}
|
||||
|
||||
void HandleMemcpyDmaIrq()
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*g_memcpyDmaInfo.isReg & g_memcpyDmaInfo.tcMask) { // DMA transfer complete
|
||||
*g_memcpyDmaInfo.ifcReg = g_memcpyDmaInfo.tcMask;
|
||||
LL_DMA_DisableStream(g_memcpyDmaInfo.dma, g_memcpyDmaInfo.stream);
|
||||
g_memcpyDmaBusy = 0;
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
110
components/f4ll_c/src/strutil.c
Normal file
110
components/f4ll_c/src/strutil.c
Normal file
|
@ -0,0 +1,110 @@
|
|||
#include <stdint.h>
|
||||
#include "f4ll_c/strutil.h"
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t strcpy_ex(char *dst, char const *src)
|
||||
{
|
||||
size_t ret = 0;
|
||||
do {
|
||||
*dst++ = *src;
|
||||
++ret;
|
||||
} while(*src++);
|
||||
return ret - 1;
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
void strrev(char *first, char *last)
|
||||
{
|
||||
char tmp;
|
||||
while(last > first) {
|
||||
tmp = *first;
|
||||
*first++ = *last;
|
||||
*last-- = tmp;
|
||||
}
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
char tochr(const uint8_t in, const uint8_t upper)
|
||||
{
|
||||
return in + ((in < 10) ? '0' : (upper ? 'A' : 'a') - 10);
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t uitodec(char* buffer, uint32_t data)
|
||||
{
|
||||
char *b2 = buffer;
|
||||
if(!data) {
|
||||
*b2++ = '0';
|
||||
*b2 = '\0';
|
||||
return 1;
|
||||
}
|
||||
|
||||
while(data) {
|
||||
*b2++ = (data % 10) + '0';
|
||||
data /= 10;
|
||||
}
|
||||
size_t ret = b2 - buffer;
|
||||
|
||||
*b2-- = 0;
|
||||
|
||||
strrev(buffer, b2);
|
||||
return ret;
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t uitohex(char* buffer, uint32_t data, uint8_t chars)
|
||||
{
|
||||
char *b2 = buffer;
|
||||
size_t ret = 0;
|
||||
|
||||
if(chars == 0xff || !chars)
|
||||
{
|
||||
if(!data) {
|
||||
*b2++ = '0';
|
||||
*b2 = '\0';
|
||||
return 1;
|
||||
}
|
||||
|
||||
while(data) {
|
||||
uint8_t curval = data & 0x0f;
|
||||
*b2++ = tochr(curval, 1);
|
||||
data >>= 4;
|
||||
}
|
||||
ret = b2 - buffer;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = chars;
|
||||
for(uint8_t pos = 0; pos < (uint8_t)ret; ++pos) {
|
||||
*b2++ = tochr(data & 0x0f, 1);
|
||||
data >>= 4;
|
||||
}
|
||||
|
||||
}
|
||||
*b2-- = 0;
|
||||
strrev(buffer, b2);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t itodec(char* buffer, int data)
|
||||
{
|
||||
if(data < 0) {
|
||||
*buffer++ = '-';
|
||||
return uitodec(buffer, -data) + 1;
|
||||
}
|
||||
|
||||
return uitodec(buffer, data);
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t itohex(char* buffer, int data)
|
||||
{
|
||||
if(data < 0) {
|
||||
*buffer++ = '-';
|
||||
return uitohex(buffer, -data, 0) + 1;
|
||||
}
|
||||
return uitohex(buffer, data, 0);
|
||||
}
|
258
components/f4ll_c/src/usart_handler.c
Normal file
258
components/f4ll_c/src/usart_handler.c
Normal file
|
@ -0,0 +1,258 @@
|
|||
/*
|
||||
* usart_handler.c
|
||||
*
|
||||
* Created on: Sep 16, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <platform/usart_ll.h>
|
||||
#include "diag.h"
|
||||
#include "f4ll_c/usart_handler.h"
|
||||
#include "f4ll_c/dma_helper.h"
|
||||
#include "f4ll_c/crc_handler.h"
|
||||
#include "f4ll_c/memcpy_dma.h"
|
||||
|
||||
#ifndef DIAG_RX_BUFFER_SWITCH
|
||||
# define DIAG_RX_BUFFER_SWITCH(x)
|
||||
#endif
|
||||
#ifndef DIAG_INTERRUPT_IN
|
||||
# define DIAG_INTERRUPT_IN()
|
||||
#endif
|
||||
#ifndef DIAG_INTERRUPT_OUT
|
||||
# define DIAG_INTERRUPT_OUT()
|
||||
#endif
|
||||
|
||||
#define STARTMARKER 0x95
|
||||
|
||||
static inline uint32_t RoundUpTo4(uint32_t inp)
|
||||
{
|
||||
return (inp + 3) & 0xfffc;
|
||||
}
|
||||
|
||||
void InitUartStatus(
|
||||
USARTSTATUS *st, USART_TypeDef *usart, DMA_TypeDef *dma,
|
||||
uint32_t stream_rx, uint32_t stream_tx,
|
||||
CRCSTATUS *crcStatus, uint8_t rxCrcSlot, uint8_t txCrcSlot,
|
||||
PACKETRECEIVEDCALLBACK packetReceivedCallback, void * packetReceivedCallbackParam)
|
||||
{
|
||||
st->usart = usart;
|
||||
InitDmaInfo(&st->rxDmaInfo, dma, stream_rx);
|
||||
InitDmaInfo(&st->txDmaInfo, dma, stream_tx);
|
||||
st->txBuffer.busy = 0;
|
||||
st->txBuffer.error = 0;
|
||||
st->txBuffer.requestedLength = 0;
|
||||
st->rxBuffers[0].busy = 0;
|
||||
st->rxBuffers[1].busy = 0;
|
||||
st->rxBuffers[0].error = 0;
|
||||
st->rxBuffers[1].error = 0;
|
||||
st->rxBuffers[0].requestedLength = 0;
|
||||
st->rxBuffers[1].requestedLength = 0;
|
||||
st->txBuffer.usartStatus = st;
|
||||
st->rxBuffers[0].usartStatus = st;
|
||||
st->rxBuffers[1].usartStatus = st;
|
||||
st->packetReceivedCallback = packetReceivedCallback;
|
||||
st->packetReceivedCallbacParam = packetReceivedCallbackParam;
|
||||
st->rxSerial = -1;
|
||||
st->txSerial = 0;
|
||||
st->activeRxBuf = 0;
|
||||
st->crcStatus = crcStatus;
|
||||
st->txCrcSlot = txCrcSlot;
|
||||
st->rxCrcSlot = rxCrcSlot;
|
||||
memset(&st->stats, 0, sizeof(st->stats));
|
||||
|
||||
LL_DMA_EnableIT_TC(dma, stream_rx);
|
||||
LL_DMA_EnableIT_TE(dma, stream_rx);
|
||||
LL_DMA_EnableIT_TC(dma, stream_tx);
|
||||
LL_DMA_EnableIT_TE(dma, stream_tx);
|
||||
LL_USART_EnableIT_IDLE(usart);
|
||||
}
|
||||
|
||||
|
||||
uint8_t* GetTxBuffer(USARTSTATUS *status)
|
||||
{
|
||||
return status->txBuffer.packet.payload;
|
||||
}
|
||||
|
||||
|
||||
static inline void BuildHeader(struct usart_buffer *buffer, uint8_t serial, uint8_t length)
|
||||
{
|
||||
uint8_t hash = STARTMARKER;
|
||||
buffer->packet.header.startByte = STARTMARKER;
|
||||
buffer->packet.header.serial = serial;
|
||||
hash ^= serial;
|
||||
buffer->packet.header.payloadLength = length - 1;
|
||||
hash ^= length - 1;
|
||||
buffer->packet.header.hash = hash;
|
||||
}
|
||||
|
||||
static inline uint8_t CheckHeader(USARTPACKET *packet)
|
||||
{
|
||||
return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
|
||||
}
|
||||
|
||||
|
||||
uint8_t PostPacket(USARTSTATUS *status, uint8_t const *payload, uint16_t length, CRCSTATUS *crcStatus)
|
||||
{
|
||||
if(length > 256)
|
||||
return 1;
|
||||
|
||||
BuildHeader(&status->txBuffer, status->txSerial++, length);
|
||||
uint16_t payloadLength = RoundUpTo4(length);
|
||||
if(payload) {
|
||||
#ifdef USART_USE_MEMCPY_DMA
|
||||
if((uint32_t)payload & 3)
|
||||
memcpy(status->txBuffer.packet.payload, payload, length);
|
||||
else
|
||||
MemcpyDma(status->txBuffer.packet.payload, payload, length);
|
||||
#else
|
||||
memcpy(status->txBuffer.packet.payload, payload, length);
|
||||
#endif
|
||||
}
|
||||
status->txBuffer.requestedLength = sizeof(USARTPACKETHEADER) + payloadLength + sizeof(uint32_t); // +4 for the hash
|
||||
status->txBuffer.busy = 1;
|
||||
status->txBuffer.error = 0;
|
||||
EnqueueCrcTask(crcStatus, status->txCrcSlot, status->txBuffer.packet.payload, length,
|
||||
NULL, (uint32_t*)(status->txBuffer.packet.payload + payloadLength));
|
||||
while(IsSlotQueued(crcStatus, status->txCrcSlot));
|
||||
SetupTransmit(status->usart, status->txDmaInfo.dma, status->txDmaInfo.stream, &status->txBuffer.packet, status->txBuffer.requestedLength);
|
||||
|
||||
StatsIncSent(&status->stats);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void SetupReceive(USARTSTATUS *status)
|
||||
{
|
||||
uint8_t packetIndex = status->activeRxBuf;
|
||||
|
||||
LL_DMA_ConfigAddresses(status->rxDmaInfo.dma, status->rxDmaInfo.stream, LL_USART_DMA_GetRegAddr(status->usart), (uint32_t)&status->rxBuffers[packetIndex],
|
||||
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
||||
status->rxBuffers[packetIndex].requestedLength = sizeof(status->rxBuffers[packetIndex].packet);
|
||||
LL_DMA_SetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream, status->rxBuffers[packetIndex].requestedLength); // payload already have extra room for hash
|
||||
LL_USART_EnableDMAReq_RX(status->usart);
|
||||
LL_USART_ClearFlag_ORE(status->usart);
|
||||
LL_DMA_EnableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
}
|
||||
|
||||
|
||||
void ConsumePacket(USARTSTATUS *status, uint8_t packetIndex, CRCSTATUS *crcStatus)
|
||||
{
|
||||
struct usart_buffer *buffer = &status->rxBuffers[packetIndex];
|
||||
if(buffer->busy) {
|
||||
if(buffer->error)
|
||||
StatsIncPayloadError(&status->stats, buffer->errorInfo, *(uint32_t*) (buffer->packet.payload + RoundUpTo4(buffer->packet.header.payloadLength + 1)));
|
||||
else {
|
||||
uint8_t diff = buffer->packet.header.serial - status->rxSerial;
|
||||
if(diff > 1)
|
||||
StatsAddSkiped(&status->stats, diff - 1);
|
||||
status->rxSerial = buffer->packet.header.serial;
|
||||
}
|
||||
}
|
||||
|
||||
buffer->busy = buffer->error = 0;
|
||||
}
|
||||
|
||||
|
||||
void SetupTransmit(USART_TypeDef *usart, DMA_TypeDef* dma, uint32_t stream, void *buffer, uint32_t length)
|
||||
{
|
||||
LL_DMA_ConfigAddresses(dma, stream, (uint32_t)buffer, LL_USART_DMA_GetRegAddr(usart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_SetDataLength(dma, stream, length);
|
||||
LL_USART_EnableDMAReq_TX(usart);
|
||||
LL_DMA_EnableStream(dma, stream);
|
||||
}
|
||||
|
||||
void RxCrcComputedCallback(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
|
||||
{
|
||||
struct usart_buffer *ub = (struct usart_buffer*) callbackParm;
|
||||
if(!success)
|
||||
ub->error = 1;
|
||||
else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength + 1)) == calculatedCrc)
|
||||
ub->busy = 1;
|
||||
else {
|
||||
ub->error = ub->busy = 1;
|
||||
ub->errorInfo = calculatedCrc;
|
||||
}
|
||||
if(ub->usartStatus->packetReceivedCallback)
|
||||
ub->usartStatus->packetReceivedCallback(ub->usartStatus->packetReceivedCallbacParam, ub);
|
||||
}
|
||||
|
||||
void HandleUsartRxDmaIrq(USARTSTATUS *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
StatsIncRcvd(&status->stats);
|
||||
if(*status->rxDmaInfo.isReg & status->rxDmaInfo.tcMask) {
|
||||
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.tcMask;
|
||||
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet))
|
||||
EnqueueCrcTask(status->crcStatus, status->rxCrcSlot,
|
||||
status->rxBuffers[status->activeRxBuf].packet.payload,
|
||||
status->rxBuffers[status->activeRxBuf].packet.header.payloadLength +1,
|
||||
RxCrcComputedCallback, &status->rxBuffers[status->activeRxBuf]);
|
||||
else {
|
||||
StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
}
|
||||
} else if(*status->rxDmaInfo.isReg & status->rxDmaInfo.teMask) {
|
||||
*status->rxDmaInfo.ifcReg = status->rxDmaInfo.teMask;
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
}
|
||||
|
||||
status->activeRxBuf ^= 1;
|
||||
|
||||
DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
|
||||
if(status->rxBuffers[status->activeRxBuf].busy)
|
||||
StatsIncOverrun(&status->stats);
|
||||
SetupReceive(status);
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleUsartTxDmaIrq(USARTSTATUS *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.tcMask) { // DMA transfer complete
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.tcMask;
|
||||
LL_USART_EnableIT_TC(status->usart);
|
||||
LL_DMA_DisableStream(status->txDmaInfo.dma, status->txDmaInfo.stream);
|
||||
}
|
||||
else if(*status->txDmaInfo.isReg & status->txDmaInfo.teMask) {
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.teMask;
|
||||
status->txBuffer.error = 1;
|
||||
StatsIncDmaError(&status->stats);
|
||||
}
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.feMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.feMask;
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.htMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.htMask;
|
||||
if(*status->txDmaInfo.isReg & status->txDmaInfo.dmeMask)
|
||||
*status->txDmaInfo.ifcReg = status->txDmaInfo.dmeMask;
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
||||
void HandleUsartIrq(USARTSTATUS *status)
|
||||
{
|
||||
DIAG_INTERRUPT_IN();
|
||||
if(LL_USART_IsActiveFlag_IDLE(status->usart) && LL_USART_IsEnabledIT_IDLE(status->usart)) { // receiver idle
|
||||
LL_USART_ClearFlag_IDLE(status->usart);
|
||||
uint16_t rcvdLen = status->rxBuffers[status->activeRxBuf].requestedLength - LL_DMA_GetDataLength(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
if(rcvdLen >= sizeof(USARTPACKETHEADER)) {
|
||||
if(CheckHeader(&status->rxBuffers[status->activeRxBuf].packet)) {
|
||||
if(rcvdLen >= sizeof(USARTPACKETHEADER) + RoundUpTo4(status->rxBuffers[status->activeRxBuf].packet.header.payloadLength + 1) + sizeof(uint32_t))
|
||||
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
else
|
||||
StatsIncPremature_payload(&status->stats);
|
||||
} else {
|
||||
status->rxBuffers[status->activeRxBuf].error = 1;
|
||||
LL_DMA_DisableStream(status->rxDmaInfo.dma, status->rxDmaInfo.stream);
|
||||
}
|
||||
} else
|
||||
StatsIncPremature_hdr(&status->stats);
|
||||
}
|
||||
else if(LL_USART_IsActiveFlag_TC(status->usart) && LL_USART_IsEnabledIT_TC(status->usart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(status->usart);
|
||||
LL_USART_DisableDirectionTx(status->usart); // enforcing an idle frame
|
||||
LL_USART_EnableDirectionTx(status->usart);
|
||||
status->txBuffer.busy = 0;
|
||||
}
|
||||
DIAG_INTERRUPT_OUT();
|
||||
}
|
||||
|
Loading…
Add table
Add a link
Reference in a new issue