tmp 1

2025-06-08 14:17:59 +02:00 · 2025-06-08 14:17:59 +02:00 · 3957af107d
commit 3957af107d
parent bc01b1f0e8
235 changed files with 159562 additions and 189150 deletions
--- a/components/f4ll/src/crc_handler.cpp
+++ b/components/f4ll/src/crc_handler.cpp
@ -0,0 +1,158 @@
+/*
+ * ll_crchandler.cpp
+ *
+ *  Created on: Oct 26, 2019
+ *      Author: compi
+ */
+#include <f4ll/crc_handler.h>
+
+namespace f4ll {
+
+CrcHandler::CrcHandler(DMA_TypeDef *dma, uint32_t stream) : m_dma(dma, stream) {
+  LL_DMA_EnableIT_TC(dma, stream);
+  LL_DMA_EnableIT_TE(dma, stream);
+  LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&CRC->DR);
+}
+
+void CrcHandler::AttachSlot(SlotBase &slot) {
+  for (unsigned int i = 0; i < slot.m_taskCount; ++i) {
+    auto &task(slot[i]);
+    task.m_address = nullptr;
+    task.m_wordCount = 0;
+    task.m_callback = nullptr;
+    task.m_callbackParam = 0;
+  }
+  uint32_t prim = __get_PRIMASK();
+  __disable_irq();
+  slot.m_next = m_firstSlot;
+  m_firstSlot = &slot;
+  __set_PRIMASK(prim);
+}
+
+bool CrcHandler::Enqueue(SlotBase &slot, uint8_t task, void const *address,
+                         uint16_t len, ICallback *cb, uintptr_t cbParam) {
+  uint32_t prim = __get_PRIMASK();
+  bool immediate;
+
+  // TODO: do we need sanity check here? (is slot attached, is task in range,
+  // etc...?)
+
+  while (IsActive(slot, task))
+    ;
+  __disable_irq();
+  immediate = m_activeSlot == nullptr;
+  slot[task].m_address = (!immediate) ? address : nullptr;
+  slot[task].m_wordCount = (len + 3) / 4;
+  slot[task].m_callback = cb;
+  slot[task].m_callbackParam = cbParam;
+  if (immediate) {
+    m_activeSlot = &slot;
+    m_activeTask = task;
+  }
+  __set_PRIMASK(prim);
+
+  if (immediate) {
+    CRC->CR = 1;
+    LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(),
+                            (uint32_t)address);
+    LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), (len + 3) / 4);
+    LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
+  }
+  return immediate;
+}
+
+bool CrcHandler::IsActive(SlotBase &slot, uint8_t task) const {
+  return task < slot.m_taskCount && slot[task].m_wordCount != 0;
+}
+
+bool CrcHandler::IsQueued(SlotBase &slot, uint8_t task) const {
+  return task < slot.m_taskCount && slot[task].m_address != nullptr;
+}
+
+bool CrcHandler::IsRunning(SlotBase &slot, uint8_t task) const {
+  return task < slot.m_taskCount && slot[task].m_wordCount &&
+         !slot[task].m_address;
+}
+
+void CrcHandler::DmaTransferCompleted(void) {
+  if (*m_dma.GetIsReg() & m_dma.GetTcMask()) { // DMA transfer complete
+    *m_dma.GetIfcReg() = m_dma.GetTcMask();
+    LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
+    if (m_activeSlot) {
+      if ((*m_activeSlot)[m_activeTask].m_callback)
+        (*m_activeSlot)[m_activeTask].m_callback->CrcSucceeded(
+            (*m_activeSlot)[m_activeTask].m_callbackParam, CRC->DR,
+            m_activeTask);
+      else if ((*m_activeSlot)[m_activeTask].m_callbackParam)
+        *reinterpret_cast<uint32_t *>(
+            (*m_activeSlot)[m_activeTask].m_callbackParam) = CRC->DR;
+    }
+  } else if (*m_dma.GetIsReg() & m_dma.GetTeMask()) { // DMA transfer error
+    *m_dma.GetIfcReg() = m_dma.GetTeMask();
+    LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
+    if (m_activeSlot) {
+      if ((*m_activeSlot)[m_activeTask].m_callback)
+        (*m_activeSlot)[m_activeTask].m_callback->CrcFailed(
+            (*m_activeSlot)[m_activeTask].m_callbackParam, CRC->DR,
+            m_activeTask);
+      else if ((*m_activeSlot)[m_activeTask].m_callbackParam)
+        *reinterpret_cast<uint32_t *>(
+            (*m_activeSlot)[m_activeTask].m_callbackParam) = -1;
+    }
+  }
+  (*m_activeSlot)[m_activeTask].m_callback = nullptr;
+  (*m_activeSlot)[m_activeTask].m_callbackParam = 0;
+  (*m_activeSlot)[m_activeTask].m_wordCount = 0;
+  StartNextTask();
+}
+
+void CrcHandler::StartNextTask(void) {
+  bool moreTasks;
+  uint8_t index = 0;
+
+  do {
+    SlotBase volatile *slot = m_firstSlot;
+    moreTasks = false;
+    while (slot) {
+      if (index < slot->m_taskCount) {
+        if ((*slot)[index].m_address) {
+          m_activeSlot = slot;
+          m_activeTask = index;
+          CRC->CR = 1;
+          LL_DMA_SetM2MSrcAddress(
+              m_dma.GetDma(), m_dma.GetStream(),
+              reinterpret_cast<uint32_t>((*slot)[index].m_address));
+          LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(),
+                               (*slot)[index].m_wordCount);
+          LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
+          (*slot)[index].m_address = nullptr; // marking as started
+          return;
+        }
+        if (index + 1 < slot->m_taskCount)
+          moreTasks = true;
+      }
+      slot = slot->m_next;
+    }
+    ++index;
+  } while (moreTasks);
+  m_activeSlot = nullptr;
+}
+
+void CrcHandler::WaitResults(SlotBase &slot, uint8_t task) const {
+  while (IsQueued(slot, task))
+    ;
+  while (IsActive(slot, task))
+    ;
+}
+
+uint32_t CrcHandler::Compute(SlotBase &slot, uint8_t task, void const *address,
+                             uint16_t len) {
+  uint32_t result;
+  Enqueue(slot, task, address, len, nullptr,
+          reinterpret_cast<uintptr_t>(&result));
+  while (IsActive(slot, task))
+    ;
+  return result;
+}
+
+} // namespace f4ll