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This commit is contained in:
Attila Body 2025-06-08 14:17:59 +02:00
parent bc01b1f0e8
commit 3957af107d
Signed by: abody
GPG key ID: BD0C6214E68FB5CF
235 changed files with 159562 additions and 189150 deletions
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45
components/f4ll/inc/consolehandler.h
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/*
* ll_consolehandler.h
*
* Created on: Nov 7, 2019
* Author: abody
*/
#ifndef LL_CONSOLEHANDLER_H_
#define LL_CONSOLEHANDLER_H_
#include "f4ll/packetusart.h"
#include "singleton.h"
namespace f4ll {
class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
{
friend class Singleton<ConsoleHandler>;
public:
void PrintStats(uint8_t id, PacketUsart &usart);
private:
ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
// LL_UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void FramingError(void);
virtual void Overrun(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
char m_buffer[128];
uint16_t m_used = 0;
};
} /* namespace f4ll */
#endif /* LL_CONSOLEHANDLER_H_ */

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components/f4ll/inc/crchandler.h
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/*
* ll_crchandler.h
*
* Created on: Oct 26, 2019
* Author: compi
*/
#ifndef LL_CRCHANDLER_H_
#define LL_CRCHANDLER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
#include "f4ll/dmahelper.h"
#include "singleton.h"
extern "C" void _HandleCrcDmaIrq(void);
namespace f4ll {
class CrcHandler : public Singleton<CrcHandler>
{
friend class Singleton<CrcHandler>;
public:
struct ICallback
{
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
};
class SlotBase
{
friend class CrcHandler;
public:
struct CrcTask {
void const * m_address; // changed to nullptr when execution starts
uint16_t m_wordCount;
ICallback *m_callback;
uintptr_t m_callbackParam;
};
private:
SlotBase volatile *m_next = nullptr;
uint8_t m_taskCount;
virtual CrcTask volatile & operator[](int index) volatile = 0;
protected:
SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
SlotBase() = delete;
SlotBase(SlotBase const &other) = delete;
};
template <uint8_t n> class Slot : public SlotBase
{
public:
Slot() : SlotBase(n) {}
virtual CrcTask volatile & operator[](int index) volatile { return m_tasks[index]; }
private:
Slot::CrcTask m_tasks[n];
};
void AttachSlot(SlotBase &slot);
bool Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam);
uint32_t Compute(SlotBase &slot, uint8_t task, void const *address, uint16_t len);
bool IsActive(SlotBase &slot, uint8_t task) const;
bool IsQueued(SlotBase &slot, uint8_t task) const;
bool IsRunning(SlotBase &slot, uint8_t task) const;
void DmaTransferCompleted(void);
private:
CrcHandler(DMA_TypeDef *dma, uint32_t stream);
friend void ::_HandleCrcDmaIrq(void);
void StartNextTask(void);
void WaitResults(SlotBase &slot, uint8_t task) const;
DmaHelper m_dma;
SlotBase volatile *m_firstSlot = nullptr;
SlotBase volatile *m_activeSlot = nullptr;
int volatile m_activeTask;
};
} // namespace f4ll
#endif /* LL_CRCHANDLER_H_ */

58
components/f4ll/inc/dmahelper.h
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/*
* ll_dmahelper.h
*
* Created on: Oct 25, 2019
* Author: abody
*/
#ifndef LL_DMAHELPER_H_
#define LL_DMAHELPER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
namespace f4ll {
class DmaHelper {
public:
DmaHelper(DMA_TypeDef *dma, uint32_t stream);
DmaHelper(DmaHelper const &base) = default;
inline DMA_TypeDef* GetDma() const { return m_dma; }
inline uint32_t GetStream() const { return m_stream; }
inline volatile uint32_t* GetIsReg() const { return m_isReg; }
inline volatile uint32_t* GetIfcReg() const { return m_ifcReg; }
inline uint32_t GetFeMask() const { return m_FEMasks[m_stream]; }
inline uint32_t GetDmeMask() const { return m_DMEMasks[m_stream]; }
inline uint32_t GetTeMask() const { return m_TEMasks[m_stream]; }
inline uint32_t GetHtMask() const { return m_HTMasks[m_stream]; }
inline uint32_t GetTcMask() const { return m_TCMasks[m_stream]; }
inline bool IsEnabledIt_HT() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_TE() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_TC() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_DME() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_FE() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
enum class DmaErrorType {
Transfer,
DirectMode,
Fifo
};
private:
DMA_TypeDef *m_dma;
uint32_t m_stream;
volatile uint32_t *m_isReg;
volatile uint32_t *m_ifcReg;
static const uint32_t m_FEMasks[8];
static const uint32_t m_DMEMasks[8];
static const uint32_t m_TEMasks[8];
static const uint32_t m_HTMasks[8];
static const uint32_t m_TCMasks[8];
};
} /* namespace f4ll */
#endif /* LL_DMAHELPER_H_ */

1
components/f4ll/inc/f4ll
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.

44
components/f4ll/inc/f4ll/console_handler.h Normal file
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/*
* ll_consolehandler.h
*
* Created on: Nov 7, 2019
* Author: abody
*/
#ifndef LL_CONSOLEHANDLER_H_
#define LL_CONSOLEHANDLER_H_
#include <f4ll/packet_usart.h>
#include <f4ll/singleton.h>
namespace f4ll {
class console_handler : public usart_core, public singleton<console_handler>
{
friend class singleton<console_handler>;
public:
void PrintStats(uint8_t id, PacketUsart &usart);
private:
console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
// LL_UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void FramingError(void);
virtual void Overrun(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(dma_helper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(dma_helper::DmaErrorType reason);
char m_buffer[128];
uint16_t m_used = 0;
};
} /* namespace f4ll */
#endif /* LL_CONSOLEHANDLER_H_ */

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components/f4ll/inc/f4ll/crc_handler.h Normal file
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/*
* ll_crchandler.h
*
* Created on: Oct 26, 2019
* Author: compi
*/
#ifndef LL_CRCHANDLER_H_
#define LL_CRCHANDLER_H_
#include <f4ll/dma_helper.h>
#include <f4ll/singleton.h>
#include <inttypes.h>
#include <platform/dma_ll.h>
extern "C" void _HandleCrcDmaIrq(void);
namespace f4ll {
class CrcHandler : public singleton<CrcHandler>
{
friend class singleton<CrcHandler>;
public:
struct ICallback
{
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
};
class SlotBase
{
friend class CrcHandler;
public:
struct CrcTask
{
void const *m_address; // changed to nullptr when execution starts
uint16_t m_wordCount;
ICallback *m_callback;
uintptr_t m_callbackParam;
};
private:
SlotBase volatile *m_next = nullptr;
uint8_t m_taskCount;
virtual CrcTask volatile &operator[](int index) volatile = 0;
protected:
SlotBase(unsigned int taskCount)
: m_taskCount(taskCount)
{
}
SlotBase() = delete;
SlotBase(SlotBase const &other) = delete;
};
template <uint8_t n> class Slot : public SlotBase
{
public:
Slot()
: SlotBase(n)
{
}
virtual CrcTask volatile &operator[](int index) volatile { return m_tasks[index]; }
private:
Slot::CrcTask m_tasks[n];
};
void AttachSlot(SlotBase &slot);
bool Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam);
uint32_t Compute(SlotBase &slot, uint8_t task, void const *address, uint16_t len);
bool IsActive(SlotBase &slot, uint8_t task) const;
bool IsQueued(SlotBase &slot, uint8_t task) const;
bool IsRunning(SlotBase &slot, uint8_t task) const;
void DmaTransferCompleted(void);
private:
CrcHandler(DMA_TypeDef *dma, uint32_t stream);
friend void ::_HandleCrcDmaIrq(void);
void StartNextTask(void);
void WaitResults(SlotBase &slot, uint8_t task) const;
dma_helper m_dma;
SlotBase volatile *m_firstSlot = nullptr;
SlotBase volatile *m_activeSlot = nullptr;
int volatile m_activeTask;
};
} // namespace f4ll
#endif /* LL_CRCHANDLER_H_ */

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components/f4ll/inc/f4ll/dma_helper.h Normal file
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/*
* ll_dmahelper.h
*
* Created on: Oct 25, 2019
* Author: abody
*/
#ifndef LL_DMAHELPER_H_
#define LL_DMAHELPER_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
namespace f4ll {
class dma_helper
{
public:
dma_helper(DMA_TypeDef *dma, uint32_t stream);
dma_helper(dma_helper const &base) = default;
inline DMA_TypeDef *GetDma() const { return m_dma; }
inline uint32_t GetStream() const { return m_stream; }
inline volatile uint32_t *GetIsReg() const { return m_isReg; }
inline volatile uint32_t *GetIfcReg() const { return m_ifcReg; }
inline uint32_t GetFeMask() const { return m_FEMasks[m_stream]; }
inline uint32_t GetDmeMask() const { return m_DMEMasks[m_stream]; }
inline uint32_t GetTeMask() const { return m_TEMasks[m_stream]; }
inline uint32_t GetHtMask() const { return m_HTMasks[m_stream]; }
inline uint32_t GetTcMask() const { return m_TCMasks[m_stream]; }
inline bool IsEnabledIt_HT() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_TE() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_TC() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_DME() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
inline bool IsEnabledIt_FE() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
enum class DmaErrorType
{
Transfer,
DirectMode,
Fifo
};
private:
DMA_TypeDef *m_dma;
uint32_t m_stream;
volatile uint32_t *m_isReg;
volatile uint32_t *m_ifcReg;
static const uint32_t m_FEMasks[8];
static const uint32_t m_DMEMasks[8];
static const uint32_t m_TEMasks[8];
static const uint32_t m_HTMasks[8];
static const uint32_t m_TCMasks[8];
};
} /* namespace f4ll */
#endif /* LL_DMAHELPER_H_ */

0
components/f4ll/inc/fault.h → components/f4ll/inc/f4ll/fault.h
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0
components/f4ll/inc/irqlock.h → components/f4ll/inc/f4ll/irq_lock.h
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components/f4ll/inc/f4ll/memcpy_dma.h Normal file
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/*
* llmemcpydma.h
*
* Created on: Nov 4, 2019
* Author: abody
*/
#ifndef LL_MEMCPY_DMA_H_
#define LL_MEMCPY_DMA_H_
#include <f4ll/dma_helper.h>
#include <f4ll/singleton.h>
namespace f4ll {
class MemcpyDma : public singleton<MemcpyDma>, private dma_helper
{
friend class singleton<MemcpyDma>;
public:
void *Copy(void *dst, void const *src, uint16_t length);
void DmaTransferCompleted();
private:
MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
bool volatile m_busy = false;
};
} /* namespace f4ll */
#endif /* LL_MEMCPY_DMA_H_ */

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components/f4ll/inc/f4ll/packet_usart.h Normal file
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/*
* ll_HsUsart.h
*
* Created on: Oct 29, 2019
* Author: abody
*/
#ifndef LL_HSUSART_H_
#define LL_HSUSART_H_
#include <f4ll/crc_handler.h>
#include <f4ll/usart_core.h>
#include <platform/usart_ll.h>
namespace f4ll {
struct DMAINFO;
class PacketUsart : public CrcHandler::ICallback, public usart_core
{
// friend class UsartCore;
public:
PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
struct PacketHeader
{ // !!! size should be multiple of 4 !!!
uint8_t startByte;
uint8_t serial;
uint8_t payloadLength;
uint8_t hash;
};
struct Packet
{
PacketHeader header;
uint8_t payload[256 + sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned));
struct Stats
{
uint32_t overrun = 0;
uint32_t hdrError = 0;
uint32_t payloadErrror = 0;
uint32_t pep1 = 0;
uint32_t pep2 = 0;
uint32_t rxDmaError = 0;
uint32_t txDmaError = 0;
uint32_t rcvd = 0;
uint32_t premature_hdr = 0;
uint32_t premature_payload = 0;
uint32_t sent = 0;
uint32_t skiped = 0;
};
struct IHsUsartCallback
{
virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
};
// CRCHandler::ICallback interface functions
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
void SetupReceive(void);
void RxProcessed(bool second);
// Getters
uint8_t *GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
uint8_t const *GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
USART_TypeDef *GetUsart(void) const { return m_usart; }
Stats const &GetStats(void) const { return m_stats; }
inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
inline bool IsTxFailed(void) const { return m_txBuffer.error; }
inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
void SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam);
private:
void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
bool CheckHeader(PacketHeader &header);
void SwitchRxBuffers(void);
// UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void FramingError(void);
virtual void Overrun(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(dma_helper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(dma_helper::DmaErrorType reason);
struct Buffer
{
Packet packet;
// transfer area ends here
bool volatile busy = 0;
bool volatile error = 0;
uint16_t requestedLength = 0;
uint32_t errorInfo = 0;
};
static const uint8_t STARTMARKER = 0x95;
uint8_t m_rxSerialNo = -1;
uint8_t m_txSerialNo = -1;
Stats m_stats;
bool m_rxBufferSelector = false;
CrcHandler::Slot<2> m_crcSlot;
IHsUsartCallback *m_userCallback = nullptr;
uintptr_t m_userCallbackParam = 0;
Buffer m_txBuffer;
Buffer m_rxBuffers[2];
};
}
#endif /* LL_HSUSART_H_ */

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components/f4ll/inc/f4ll/singleton.h Normal file
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#ifndef SINGLETON_H_
#define SINGLETON_H_
#include <utility>
namespace f4ll {
template <typename T> class singleton
{
public:
static T &instance()
{
return *m_instance;
}
template <typename... args_t> static T &init(args_t &&...args)
{
static T instance{std::forward<args_t>(args)...};
m_instance = &instance;
return instance;
}
protected:
singleton() = default;
singleton(const singleton &) = delete;
singleton &operator=(const singleton &) = delete;
static T *m_instance;
};
template <typename T> T *singleton<T>::m_instance = nullptr;
} // namespace f1ll {
#endif /* SINGLETON_H_ */

0
components/f4ll/inc/strutil.h → components/f4ll/inc/f4ll/str_util.h
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components/f4ll/inc/f4ll/usart_core.h Normal file
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/*
* ll_dmadrivenusartcore.h
*
* Created on: Nov 4, 2019
* Author: abody
*/
#ifndef LL_USARTCORE_H_
#define LL_USARTCORE_H_
#include <platform/usart_ll.h>
#include <f4ll/dma_helper.h>
namespace f4ll {
class usart_core
{
public:
static inline void HandleUsartIrq(usart_core *_this) { _this->UsartIsr(); }
static inline void HandleRxDmaIrq(usart_core *_this) { _this->RxDmaIsr(); }
static inline void HandleTxDmaIrq(usart_core *_this) { _this->TxDmaIsr(); }
void SetupTransmit(void const *buffer, uint16_t length);
void SetupReceive(void *buffer, uint16_t length);
protected:
usart_core(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
USART_TypeDef *m_usart;
dma_helper m_rxDma;
dma_helper m_txDma;
private:
virtual void ReceiverIdle(void) = 0;
virtual void TransmissionComplete(void) = 0;
virtual void FramingError(void) = 0;
virtual void Overrun(void) = 0;
virtual void RxDmaTransferComplete(void) = 0;
virtual void RxDmaHalfTransfer(void) = 0;
virtual void RxDmaError(dma_helper::DmaErrorType reason) = 0;
virtual void TxDmaTransferComplete(void) = 0;
virtual void TxDmaHalfTransfer(void) = 0;
virtual void TxDmaError(dma_helper::DmaErrorType reason) = 0;
void UsartIsr();
void RxDmaIsr();
void TxDmaIsr();
};
} /* namespace f4ll */
#endif /* LL_USARTCORE_H_ */

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components/f4ll/inc/memcpydma.h
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/*
* llmemcpydma.h
*
* Created on: Nov 4, 2019
* Author: abody
*/
#ifndef LL_MEMCPY_DMA_H_
#define LL_MEMCPY_DMA_H_
#include "f4ll/dmahelper.h"
#include "singleton.h"
namespace f4ll {
class MemcpyDma : public Singleton<MemcpyDma>, private DmaHelper
{
friend class Singleton<MemcpyDma>;
public:
void* Copy(void *dst, void const *src, uint16_t length);
void DmaTransferCompleted();
private:
MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
bool volatile m_busy = false;
};
} /* namespace f4ll */
#endif /* LL_MEMCPY_DMA_H_ */

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components/f4ll/inc/packetusart.h
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/*
* ll_HsUsart.h
*
* Created on: Oct 29, 2019
* Author: abody
*/
#ifndef LL_HSUSART_H_
#define LL_HSUSART_H_
#include <platform/usart_ll.h>
#include "f4ll/usartcore.h"
#include "f4ll/crchandler.h"
namespace f4ll {
struct DMAINFO;
class PacketUsart : public CrcHandler::ICallback, public UsartCore
{
// friend class UsartCore;
public:
PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
struct PacketHeader { // !!! size should be multiple of 4 !!!
uint8_t startByte;
uint8_t serial;
uint8_t payloadLength;
uint8_t hash;
};
struct Packet {
PacketHeader header;
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned));
struct Stats {
uint32_t overrun = 0;
uint32_t hdrError = 0;
uint32_t payloadErrror = 0;
uint32_t pep1 = 0;
uint32_t pep2 = 0;
uint32_t rxDmaError = 0;
uint32_t txDmaError = 0;
uint32_t rcvd = 0;
uint32_t premature_hdr = 0;
uint32_t premature_payload = 0;
uint32_t sent = 0;
uint32_t skiped = 0;
};
struct IHsUsartCallback {
virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
};
// CRCHandler::ICallback interface functions
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
void SetupReceive(void);
void RxProcessed(bool second);
// Getters
uint8_t* GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
uint8_t const * GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
USART_TypeDef* GetUsart(void) const { return m_usart; }
Stats const & GetStats(void) const { return m_stats; }
inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
inline bool IsTxFailed(void) const { return m_txBuffer.error; }
inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
private:
void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
bool CheckHeader(PacketHeader &header);
void SwitchRxBuffers(void);
// UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void FramingError(void);
virtual void Overrun(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
struct Buffer {
Packet packet;
//transfer area ends here
bool volatile busy = 0;
bool volatile error = 0;
uint16_t requestedLength = 0;
uint32_t errorInfo = 0;
};
static const uint8_t STARTMARKER = 0x95;
uint8_t m_rxSerialNo = -1;
uint8_t m_txSerialNo = -1;
Stats m_stats;
bool m_rxBufferSelector = false;
CrcHandler::Slot<2> m_crcSlot;
IHsUsartCallback *m_userCallback = nullptr;
uintptr_t m_userCallbackParam = 0;
Buffer m_txBuffer;
Buffer m_rxBuffers[2];
};
}
#endif /* LL_HSUSART_H_ */

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components/f4ll/inc/usartcore.h
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/*
* ll_dmadrivenusartcore.h
*
* Created on: Nov 4, 2019
* Author: abody
*/
#ifndef LL_USARTCORE_H_
#define LL_USARTCORE_H_
#include <platform/usart_ll.h>
#include "f4ll/dmahelper.h"
namespace f4ll {
class UsartCore
{
public:
static inline void HandleUsartIrq(UsartCore *_this) { _this->UsartIsr(); }
static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
void SetupTransmit(void const *buffer, uint16_t length);
void SetupReceive(void *buffer, uint16_t length);
protected:
UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
USART_TypeDef *m_usart;
DmaHelper m_rxDma;
DmaHelper m_txDma;
private:
virtual void ReceiverIdle(void) = 0;
virtual void TransmissionComplete(void) = 0;
virtual void FramingError(void) = 0;
virtual void Overrun(void) = 0;
virtual void RxDmaTransferComplete(void) = 0;
virtual void RxDmaHalfTransfer(void) = 0;
virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
virtual void TxDmaTransferComplete(void) = 0;
virtual void TxDmaHalfTransfer(void) = 0;
virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
void UsartIsr();
void RxDmaIsr();
void TxDmaIsr();
};
} /* namespace f4ll */
#endif /* LL_USARTCORE_H_ */