tmp 1
This commit is contained in:
parent
bc01b1f0e8
commit
3957af107d
235 changed files with 159562 additions and 189150 deletions
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/*
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* ll_consolehandler.h
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*
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* Created on: Nov 7, 2019
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* Author: abody
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*/
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#ifndef LL_CONSOLEHANDLER_H_
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#define LL_CONSOLEHANDLER_H_
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#include "f4ll/packetusart.h"
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#include "singleton.h"
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namespace f4ll {
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class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
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{
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friend class Singleton<ConsoleHandler>;
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public:
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void PrintStats(uint8_t id, PacketUsart &usart);
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private:
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ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(DmaHelper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(DmaHelper::DmaErrorType reason);
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char m_buffer[128];
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uint16_t m_used = 0;
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};
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} /* namespace f4ll */
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#endif /* LL_CONSOLEHANDLER_H_ */
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@ -1,89 +0,0 @@
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/*
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* ll_crchandler.h
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*
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* Created on: Oct 26, 2019
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* Author: compi
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*/
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#ifndef LL_CRCHANDLER_H_
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#define LL_CRCHANDLER_H_
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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#include "f4ll/dmahelper.h"
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#include "singleton.h"
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extern "C" void _HandleCrcDmaIrq(void);
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namespace f4ll {
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class CrcHandler : public Singleton<CrcHandler>
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{
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friend class Singleton<CrcHandler>;
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public:
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struct ICallback
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{
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
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};
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class SlotBase
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{
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friend class CrcHandler;
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public:
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struct CrcTask {
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void const * m_address; // changed to nullptr when execution starts
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uint16_t m_wordCount;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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};
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private:
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SlotBase volatile *m_next = nullptr;
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uint8_t m_taskCount;
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virtual CrcTask volatile & operator[](int index) volatile = 0;
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protected:
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SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
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SlotBase() = delete;
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SlotBase(SlotBase const &other) = delete;
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};
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template <uint8_t n> class Slot : public SlotBase
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{
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public:
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Slot() : SlotBase(n) {}
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virtual CrcTask volatile & operator[](int index) volatile { return m_tasks[index]; }
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private:
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Slot::CrcTask m_tasks[n];
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};
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void AttachSlot(SlotBase &slot);
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bool Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam);
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uint32_t Compute(SlotBase &slot, uint8_t task, void const *address, uint16_t len);
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bool IsActive(SlotBase &slot, uint8_t task) const;
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bool IsQueued(SlotBase &slot, uint8_t task) const;
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bool IsRunning(SlotBase &slot, uint8_t task) const;
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void DmaTransferCompleted(void);
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private:
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CrcHandler(DMA_TypeDef *dma, uint32_t stream);
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friend void ::_HandleCrcDmaIrq(void);
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void StartNextTask(void);
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void WaitResults(SlotBase &slot, uint8_t task) const;
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DmaHelper m_dma;
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SlotBase volatile *m_firstSlot = nullptr;
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SlotBase volatile *m_activeSlot = nullptr;
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int volatile m_activeTask;
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};
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} // namespace f4ll
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#endif /* LL_CRCHANDLER_H_ */
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/*
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* ll_dmahelper.h
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*
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* Created on: Oct 25, 2019
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* Author: abody
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*/
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#ifndef LL_DMAHELPER_H_
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#define LL_DMAHELPER_H_
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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namespace f4ll {
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class DmaHelper {
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public:
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DmaHelper(DMA_TypeDef *dma, uint32_t stream);
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DmaHelper(DmaHelper const &base) = default;
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inline DMA_TypeDef* GetDma() const { return m_dma; }
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inline uint32_t GetStream() const { return m_stream; }
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inline volatile uint32_t* GetIsReg() const { return m_isReg; }
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inline volatile uint32_t* GetIfcReg() const { return m_ifcReg; }
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inline uint32_t GetFeMask() const { return m_FEMasks[m_stream]; }
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inline uint32_t GetDmeMask() const { return m_DMEMasks[m_stream]; }
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inline uint32_t GetTeMask() const { return m_TEMasks[m_stream]; }
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inline uint32_t GetHtMask() const { return m_HTMasks[m_stream]; }
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inline uint32_t GetTcMask() const { return m_TCMasks[m_stream]; }
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inline bool IsEnabledIt_HT() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TE() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TC() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_DME() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_FE() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
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enum class DmaErrorType {
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Transfer,
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DirectMode,
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Fifo
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};
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private:
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DMA_TypeDef *m_dma;
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uint32_t m_stream;
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volatile uint32_t *m_isReg;
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volatile uint32_t *m_ifcReg;
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static const uint32_t m_FEMasks[8];
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static const uint32_t m_DMEMasks[8];
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static const uint32_t m_TEMasks[8];
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static const uint32_t m_HTMasks[8];
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static const uint32_t m_TCMasks[8];
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};
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} /* namespace f4ll */
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#endif /* LL_DMAHELPER_H_ */
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.
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44
components/f4ll/inc/f4ll/console_handler.h
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44
components/f4ll/inc/f4ll/console_handler.h
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/*
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* ll_consolehandler.h
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*
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* Created on: Nov 7, 2019
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* Author: abody
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*/
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#ifndef LL_CONSOLEHANDLER_H_
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#define LL_CONSOLEHANDLER_H_
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#include <f4ll/packet_usart.h>
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#include <f4ll/singleton.h>
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namespace f4ll {
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class console_handler : public usart_core, public singleton<console_handler>
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{
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friend class singleton<console_handler>;
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public:
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void PrintStats(uint8_t id, PacketUsart &usart);
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private:
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console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
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// LL_UsartCore pure virtual function implementations
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virtual void ReceiverIdle(void);
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virtual void TransmissionComplete(void);
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virtual void FramingError(void);
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virtual void Overrun(void);
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virtual void RxDmaTransferComplete(void);
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virtual void RxDmaHalfTransfer(void);
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virtual void RxDmaError(dma_helper::DmaErrorType reason);
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virtual void TxDmaTransferComplete(void);
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virtual void TxDmaHalfTransfer(void);
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virtual void TxDmaError(dma_helper::DmaErrorType reason);
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char m_buffer[128];
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uint16_t m_used = 0;
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};
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} /* namespace f4ll */
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#endif /* LL_CONSOLEHANDLER_H_ */
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96
components/f4ll/inc/f4ll/crc_handler.h
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96
components/f4ll/inc/f4ll/crc_handler.h
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/*
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* ll_crchandler.h
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*
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* Created on: Oct 26, 2019
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* Author: compi
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*/
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#ifndef LL_CRCHANDLER_H_
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#define LL_CRCHANDLER_H_
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#include <f4ll/dma_helper.h>
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#include <f4ll/singleton.h>
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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extern "C" void _HandleCrcDmaIrq(void);
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namespace f4ll {
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class CrcHandler : public singleton<CrcHandler>
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{
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friend class singleton<CrcHandler>;
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public:
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struct ICallback
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{
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virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
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virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task) = 0;
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};
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class SlotBase
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{
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friend class CrcHandler;
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public:
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struct CrcTask
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{
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void const *m_address; // changed to nullptr when execution starts
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uint16_t m_wordCount;
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ICallback *m_callback;
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uintptr_t m_callbackParam;
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};
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private:
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SlotBase volatile *m_next = nullptr;
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uint8_t m_taskCount;
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virtual CrcTask volatile &operator[](int index) volatile = 0;
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protected:
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SlotBase(unsigned int taskCount)
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: m_taskCount(taskCount)
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{
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}
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SlotBase() = delete;
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SlotBase(SlotBase const &other) = delete;
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};
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template <uint8_t n> class Slot : public SlotBase
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{
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public:
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Slot()
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: SlotBase(n)
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{
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}
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virtual CrcTask volatile &operator[](int index) volatile { return m_tasks[index]; }
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private:
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Slot::CrcTask m_tasks[n];
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};
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void AttachSlot(SlotBase &slot);
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bool Enqueue(SlotBase &slot, uint8_t task, void const *address, uint16_t len, ICallback *cb, uintptr_t cbParam);
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uint32_t Compute(SlotBase &slot, uint8_t task, void const *address, uint16_t len);
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bool IsActive(SlotBase &slot, uint8_t task) const;
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bool IsQueued(SlotBase &slot, uint8_t task) const;
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bool IsRunning(SlotBase &slot, uint8_t task) const;
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void DmaTransferCompleted(void);
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private:
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CrcHandler(DMA_TypeDef *dma, uint32_t stream);
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friend void ::_HandleCrcDmaIrq(void);
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void StartNextTask(void);
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void WaitResults(SlotBase &slot, uint8_t task) const;
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dma_helper m_dma;
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SlotBase volatile *m_firstSlot = nullptr;
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SlotBase volatile *m_activeSlot = nullptr;
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int volatile m_activeTask;
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};
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} // namespace f4ll
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#endif /* LL_CRCHANDLER_H_ */
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60
components/f4ll/inc/f4ll/dma_helper.h
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60
components/f4ll/inc/f4ll/dma_helper.h
Normal file
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/*
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* ll_dmahelper.h
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*
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* Created on: Oct 25, 2019
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* Author: abody
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*/
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#ifndef LL_DMAHELPER_H_
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#define LL_DMAHELPER_H_
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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namespace f4ll {
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class dma_helper
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{
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public:
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dma_helper(DMA_TypeDef *dma, uint32_t stream);
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dma_helper(dma_helper const &base) = default;
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inline DMA_TypeDef *GetDma() const { return m_dma; }
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inline uint32_t GetStream() const { return m_stream; }
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inline volatile uint32_t *GetIsReg() const { return m_isReg; }
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inline volatile uint32_t *GetIfcReg() const { return m_ifcReg; }
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inline uint32_t GetFeMask() const { return m_FEMasks[m_stream]; }
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inline uint32_t GetDmeMask() const { return m_DMEMasks[m_stream]; }
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inline uint32_t GetTeMask() const { return m_TEMasks[m_stream]; }
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inline uint32_t GetHtMask() const { return m_HTMasks[m_stream]; }
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inline uint32_t GetTcMask() const { return m_TCMasks[m_stream]; }
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inline bool IsEnabledIt_HT() { return LL_DMA_IsEnabledIT_HT(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TE() { return LL_DMA_IsEnabledIT_TE(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_TC() { return LL_DMA_IsEnabledIT_TC(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_DME() { return LL_DMA_IsEnabledIT_DME(m_dma, m_stream) != 0; }
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inline bool IsEnabledIt_FE() { return LL_DMA_IsEnabledIT_FE(m_dma, m_stream) != 0; }
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enum class DmaErrorType
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{
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Transfer,
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DirectMode,
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Fifo
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};
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private:
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DMA_TypeDef *m_dma;
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uint32_t m_stream;
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volatile uint32_t *m_isReg;
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volatile uint32_t *m_ifcReg;
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static const uint32_t m_FEMasks[8];
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static const uint32_t m_DMEMasks[8];
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static const uint32_t m_TEMasks[8];
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static const uint32_t m_HTMasks[8];
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static const uint32_t m_TCMasks[8];
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};
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} /* namespace f4ll */
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#endif /* LL_DMAHELPER_H_ */
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30
components/f4ll/inc/f4ll/memcpy_dma.h
Normal file
30
components/f4ll/inc/f4ll/memcpy_dma.h
Normal file
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/*
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* llmemcpydma.h
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*
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* Created on: Nov 4, 2019
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* Author: abody
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*/
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#ifndef LL_MEMCPY_DMA_H_
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#define LL_MEMCPY_DMA_H_
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#include <f4ll/dma_helper.h>
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#include <f4ll/singleton.h>
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namespace f4ll {
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class MemcpyDma : public singleton<MemcpyDma>, private dma_helper
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{
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friend class singleton<MemcpyDma>;
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public:
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void *Copy(void *dst, void const *src, uint16_t length);
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void DmaTransferCompleted();
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private:
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MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
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bool volatile m_busy = false;
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};
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} /* namespace f4ll */
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#endif /* LL_MEMCPY_DMA_H_ */
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122
components/f4ll/inc/f4ll/packet_usart.h
Normal file
122
components/f4ll/inc/f4ll/packet_usart.h
Normal file
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/*
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* ll_HsUsart.h
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*
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* Created on: Oct 29, 2019
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* Author: abody
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*/
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#ifndef LL_HSUSART_H_
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#define LL_HSUSART_H_
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#include <f4ll/crc_handler.h>
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#include <f4ll/usart_core.h>
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#include <platform/usart_ll.h>
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namespace f4ll {
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struct DMAINFO;
|
||||
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class PacketUsart : public CrcHandler::ICallback, public usart_core
|
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{
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// friend class UsartCore;
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public:
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PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
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||||
|
||||
struct PacketHeader
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||||
{ // !!! size should be multiple of 4 !!!
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uint8_t startByte;
|
||||
uint8_t serial;
|
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uint8_t payloadLength;
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||||
uint8_t hash;
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||||
};
|
||||
|
||||
struct Packet
|
||||
{
|
||||
PacketHeader header;
|
||||
uint8_t payload[256 + sizeof(uint32_t)]; // extra room for crc32
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} __attribute__((aligned));
|
||||
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||||
struct Stats
|
||||
{
|
||||
uint32_t overrun = 0;
|
||||
uint32_t hdrError = 0;
|
||||
uint32_t payloadErrror = 0;
|
||||
uint32_t pep1 = 0;
|
||||
uint32_t pep2 = 0;
|
||||
uint32_t rxDmaError = 0;
|
||||
uint32_t txDmaError = 0;
|
||||
uint32_t rcvd = 0;
|
||||
uint32_t premature_hdr = 0;
|
||||
uint32_t premature_payload = 0;
|
||||
uint32_t sent = 0;
|
||||
uint32_t skiped = 0;
|
||||
};
|
||||
|
||||
struct IHsUsartCallback
|
||||
{
|
||||
virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
|
||||
};
|
||||
|
||||
// CRCHandler::ICallback interface functions
|
||||
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
|
||||
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
|
||||
|
||||
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
|
||||
void SetupReceive(void);
|
||||
|
||||
void RxProcessed(bool second);
|
||||
|
||||
// Getters
|
||||
uint8_t *GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
|
||||
uint8_t const *GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
|
||||
USART_TypeDef *GetUsart(void) const { return m_usart; }
|
||||
Stats const &GetStats(void) const { return m_stats; }
|
||||
inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
|
||||
inline bool IsTxFailed(void) const { return m_txBuffer.error; }
|
||||
inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
|
||||
inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
|
||||
|
||||
void SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam);
|
||||
|
||||
private:
|
||||
void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
|
||||
bool CheckHeader(PacketHeader &header);
|
||||
void SwitchRxBuffers(void);
|
||||
|
||||
// UsartCore pure virtual function implementations
|
||||
virtual void ReceiverIdle(void);
|
||||
virtual void TransmissionComplete(void);
|
||||
virtual void FramingError(void);
|
||||
virtual void Overrun(void);
|
||||
virtual void RxDmaTransferComplete(void);
|
||||
virtual void RxDmaHalfTransfer(void);
|
||||
virtual void RxDmaError(dma_helper::DmaErrorType reason);
|
||||
virtual void TxDmaTransferComplete(void);
|
||||
virtual void TxDmaHalfTransfer(void);
|
||||
virtual void TxDmaError(dma_helper::DmaErrorType reason);
|
||||
|
||||
struct Buffer
|
||||
{
|
||||
Packet packet;
|
||||
// transfer area ends here
|
||||
bool volatile busy = 0;
|
||||
bool volatile error = 0;
|
||||
uint16_t requestedLength = 0;
|
||||
uint32_t errorInfo = 0;
|
||||
};
|
||||
|
||||
static const uint8_t STARTMARKER = 0x95;
|
||||
|
||||
uint8_t m_rxSerialNo = -1;
|
||||
uint8_t m_txSerialNo = -1;
|
||||
Stats m_stats;
|
||||
bool m_rxBufferSelector = false;
|
||||
|
||||
CrcHandler::Slot<2> m_crcSlot;
|
||||
IHsUsartCallback *m_userCallback = nullptr;
|
||||
uintptr_t m_userCallbackParam = 0;
|
||||
Buffer m_txBuffer;
|
||||
Buffer m_rxBuffers[2];
|
||||
};
|
||||
|
||||
}
|
||||
#endif /* LL_HSUSART_H_ */
|
33
components/f4ll/inc/f4ll/singleton.h
Normal file
33
components/f4ll/inc/f4ll/singleton.h
Normal file
|
@ -0,0 +1,33 @@
|
|||
#ifndef SINGLETON_H_
|
||||
#define SINGLETON_H_
|
||||
|
||||
#include <utility>
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
template <typename T> class singleton
|
||||
{
|
||||
public:
|
||||
static T &instance()
|
||||
{
|
||||
return *m_instance;
|
||||
}
|
||||
template <typename... args_t> static T &init(args_t &&...args)
|
||||
{
|
||||
static T instance{std::forward<args_t>(args)...};
|
||||
m_instance = &instance;
|
||||
return instance;
|
||||
}
|
||||
|
||||
protected:
|
||||
singleton() = default;
|
||||
singleton(const singleton &) = delete;
|
||||
singleton &operator=(const singleton &) = delete;
|
||||
static T *m_instance;
|
||||
};
|
||||
|
||||
template <typename T> T *singleton<T>::m_instance = nullptr;
|
||||
|
||||
} // namespace f1ll {
|
||||
|
||||
#endif /* SINGLETON_H_ */
|
54
components/f4ll/inc/f4ll/usart_core.h
Normal file
54
components/f4ll/inc/f4ll/usart_core.h
Normal file
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* ll_dmadrivenusartcore.h
|
||||
*
|
||||
* Created on: Nov 4, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef LL_USARTCORE_H_
|
||||
#define LL_USARTCORE_H_
|
||||
#include <platform/usart_ll.h>
|
||||
|
||||
#include <f4ll/dma_helper.h>
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
class usart_core
|
||||
{
|
||||
public:
|
||||
static inline void HandleUsartIrq(usart_core *_this) { _this->UsartIsr(); }
|
||||
static inline void HandleRxDmaIrq(usart_core *_this) { _this->RxDmaIsr(); }
|
||||
static inline void HandleTxDmaIrq(usart_core *_this) { _this->TxDmaIsr(); }
|
||||
|
||||
void SetupTransmit(void const *buffer, uint16_t length);
|
||||
void SetupReceive(void *buffer, uint16_t length);
|
||||
|
||||
protected:
|
||||
usart_core(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
|
||||
|
||||
USART_TypeDef *m_usart;
|
||||
dma_helper m_rxDma;
|
||||
dma_helper m_txDma;
|
||||
|
||||
private:
|
||||
virtual void ReceiverIdle(void) = 0;
|
||||
virtual void TransmissionComplete(void) = 0;
|
||||
virtual void FramingError(void) = 0;
|
||||
virtual void Overrun(void) = 0;
|
||||
|
||||
virtual void RxDmaTransferComplete(void) = 0;
|
||||
virtual void RxDmaHalfTransfer(void) = 0;
|
||||
virtual void RxDmaError(dma_helper::DmaErrorType reason) = 0;
|
||||
|
||||
virtual void TxDmaTransferComplete(void) = 0;
|
||||
virtual void TxDmaHalfTransfer(void) = 0;
|
||||
virtual void TxDmaError(dma_helper::DmaErrorType reason) = 0;
|
||||
|
||||
void UsartIsr();
|
||||
void RxDmaIsr();
|
||||
void TxDmaIsr();
|
||||
};
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
||||
#endif /* LL_USARTCORE_H_ */
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* llmemcpydma.h
|
||||
*
|
||||
* Created on: Nov 4, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef LL_MEMCPY_DMA_H_
|
||||
#define LL_MEMCPY_DMA_H_
|
||||
#include "f4ll/dmahelper.h"
|
||||
#include "singleton.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
class MemcpyDma : public Singleton<MemcpyDma>, private DmaHelper
|
||||
{
|
||||
friend class Singleton<MemcpyDma>;
|
||||
public:
|
||||
void* Copy(void *dst, void const *src, uint16_t length);
|
||||
void DmaTransferCompleted();
|
||||
private:
|
||||
MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
|
||||
bool volatile m_busy = false;
|
||||
};
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
||||
#endif /* LL_MEMCPY_DMA_H_ */
|
|
@ -1,117 +0,0 @@
|
|||
/*
|
||||
* ll_HsUsart.h
|
||||
*
|
||||
* Created on: Oct 29, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef LL_HSUSART_H_
|
||||
#define LL_HSUSART_H_
|
||||
#include <platform/usart_ll.h>
|
||||
#include "f4ll/usartcore.h"
|
||||
#include "f4ll/crchandler.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
struct DMAINFO;
|
||||
|
||||
class PacketUsart : public CrcHandler::ICallback, public UsartCore
|
||||
{
|
||||
// friend class UsartCore;
|
||||
public:
|
||||
PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
|
||||
|
||||
struct PacketHeader { // !!! size should be multiple of 4 !!!
|
||||
uint8_t startByte;
|
||||
uint8_t serial;
|
||||
uint8_t payloadLength;
|
||||
uint8_t hash;
|
||||
};
|
||||
|
||||
struct Packet {
|
||||
PacketHeader header;
|
||||
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
|
||||
} __attribute__((aligned));
|
||||
|
||||
struct Stats {
|
||||
uint32_t overrun = 0;
|
||||
uint32_t hdrError = 0;
|
||||
uint32_t payloadErrror = 0;
|
||||
uint32_t pep1 = 0;
|
||||
uint32_t pep2 = 0;
|
||||
uint32_t rxDmaError = 0;
|
||||
uint32_t txDmaError = 0;
|
||||
uint32_t rcvd = 0;
|
||||
uint32_t premature_hdr = 0;
|
||||
uint32_t premature_payload = 0;
|
||||
uint32_t sent = 0;
|
||||
uint32_t skiped = 0;
|
||||
};
|
||||
|
||||
struct IHsUsartCallback {
|
||||
virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
|
||||
};
|
||||
|
||||
// CRCHandler::ICallback interface functions
|
||||
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
|
||||
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
|
||||
|
||||
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
|
||||
void SetupReceive(void);
|
||||
|
||||
void RxProcessed(bool second);
|
||||
|
||||
// Getters
|
||||
uint8_t* GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
|
||||
uint8_t const * GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
|
||||
USART_TypeDef* GetUsart(void) const { return m_usart; }
|
||||
Stats const & GetStats(void) const { return m_stats; }
|
||||
inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
|
||||
inline bool IsTxFailed(void) const { return m_txBuffer.error; }
|
||||
inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
|
||||
inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
|
||||
|
||||
void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
|
||||
|
||||
private:
|
||||
void BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length);
|
||||
bool CheckHeader(PacketHeader &header);
|
||||
void SwitchRxBuffers(void);
|
||||
|
||||
// UsartCore pure virtual function implementations
|
||||
virtual void ReceiverIdle(void);
|
||||
virtual void TransmissionComplete(void);
|
||||
virtual void FramingError(void);
|
||||
virtual void Overrun(void);
|
||||
virtual void RxDmaTransferComplete(void);
|
||||
virtual void RxDmaHalfTransfer(void);
|
||||
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
|
||||
virtual void TxDmaTransferComplete(void);
|
||||
virtual void TxDmaHalfTransfer(void);
|
||||
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
|
||||
|
||||
struct Buffer {
|
||||
Packet packet;
|
||||
//transfer area ends here
|
||||
bool volatile busy = 0;
|
||||
bool volatile error = 0;
|
||||
uint16_t requestedLength = 0;
|
||||
uint32_t errorInfo = 0;
|
||||
};
|
||||
|
||||
static const uint8_t STARTMARKER = 0x95;
|
||||
|
||||
uint8_t m_rxSerialNo = -1;
|
||||
uint8_t m_txSerialNo = -1;
|
||||
Stats m_stats;
|
||||
bool m_rxBufferSelector = false;
|
||||
|
||||
CrcHandler::Slot<2> m_crcSlot;
|
||||
IHsUsartCallback *m_userCallback = nullptr;
|
||||
uintptr_t m_userCallbackParam = 0;
|
||||
Buffer m_txBuffer;
|
||||
Buffer m_rxBuffers[2];
|
||||
};
|
||||
|
||||
}
|
||||
#endif /* LL_HSUSART_H_ */
|
|
@ -1,55 +0,0 @@
|
|||
/*
|
||||
* ll_dmadrivenusartcore.h
|
||||
*
|
||||
* Created on: Nov 4, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#ifndef LL_USARTCORE_H_
|
||||
#define LL_USARTCORE_H_
|
||||
#include <platform/usart_ll.h>
|
||||
|
||||
#include "f4ll/dmahelper.h"
|
||||
|
||||
namespace f4ll {
|
||||
|
||||
class UsartCore
|
||||
{
|
||||
public:
|
||||
static inline void HandleUsartIrq(UsartCore *_this) { _this->UsartIsr(); }
|
||||
static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
|
||||
static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
|
||||
|
||||
void SetupTransmit(void const *buffer, uint16_t length);
|
||||
void SetupReceive(void *buffer, uint16_t length);
|
||||
|
||||
protected:
|
||||
UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
|
||||
|
||||
USART_TypeDef *m_usart;
|
||||
DmaHelper m_rxDma;
|
||||
DmaHelper m_txDma;
|
||||
|
||||
private:
|
||||
virtual void ReceiverIdle(void) = 0;
|
||||
virtual void TransmissionComplete(void) = 0;
|
||||
virtual void FramingError(void) = 0;
|
||||
virtual void Overrun(void) = 0;
|
||||
|
||||
virtual void RxDmaTransferComplete(void) = 0;
|
||||
virtual void RxDmaHalfTransfer(void) = 0;
|
||||
virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
|
||||
|
||||
virtual void TxDmaTransferComplete(void) = 0;
|
||||
virtual void TxDmaHalfTransfer(void) = 0;
|
||||
virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
|
||||
|
||||
void UsartIsr();
|
||||
void RxDmaIsr();
|
||||
void TxDmaIsr();
|
||||
|
||||
};
|
||||
|
||||
} /* namespace f4ll */
|
||||
|
||||
#endif /* LL_USARTCORE_H_ */
|
Loading…
Add table
Add a link
Reference in a new issue