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HsUsart renamed to PacketUsart, volatile usage review

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This commit is contained in:
Attila Body 2019-11-13 15:24:01 +01:00
parent 7cdc79c2ac
commit 23a75f43c7
12 changed files with 179 additions and 171 deletions
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6
components/f4ll/src/consolehandler.cpp
View file

@ -17,6 +17,8 @@ ConsoleHandler::ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t
void ConsoleHandler::ReceiverIdle(void) {}
void ConsoleHandler::TransmissionComplete(void) {}
void ConsoleHandler::FramingError(void) {}
void ConsoleHandler::Overrun(void) {}
void ConsoleHandler::RxDmaTransferComplete(void) {}
void ConsoleHandler::RxDmaHalfTransfer(void) {}
void ConsoleHandler::RxDmaError(DmaHelper::DmaErrorType reason) {}
@ -33,11 +35,11 @@ void ConsoleHandler::TxDmaError(DmaHelper::DmaErrorType reason) {}
b += strcpy_ex(b,s); \
b += uitodec(b,u);
void ConsoleHandler::PrintStats(uint8_t id, HsUsart &usart)
void ConsoleHandler::PrintStats(uint8_t id, PacketUsart &usart)
{
char ids[] = " : ";
char *buffer = m_buffer;
HsUsart::Stats const &stats(usart.GetStats());
PacketUsart::Stats const &stats(usart.GetStats());
ids[0] = id + '0';
buffer += strcpy_ex(buffer, ids);

2
components/f4ll/src/crchandler.cpp
View file

@ -113,7 +113,7 @@ void CrcHandler::StartNextTask(void)
uint8_t index = 0;
do {
SlotBase *slot = m_firstSlot;
SlotBase volatile *slot = m_firstSlot;
moreTasks = false;
while(slot) {
if(index < slot->m_taskCount) {

132
components/f4ll/src/hsusart.cpp → components/f4ll/src/packetusart.cpp
View file

@ -5,7 +5,7 @@
* Author: abody
*/
#include <string.h>
#include "f4ll/hsusart.h"
#include "f4ll/packetusart.h"
namespace f4ll {
@ -15,87 +15,28 @@ template<typename T> static inline T RoundUpTo4(T input)
}
HsUsart::HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
PacketUsart::PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx)
: UsartCore(usart, dma, streamRx, streamTx)
{
CrcHandler::Instance().AttachSlot(m_crcSlot);
}
uint8_t* HsUsart::GetTxPacketBuffer(void)
{
return m_txBuffer.packet.payload;
}
USART_TypeDef* HsUsart::GetUsart(void)
{
return m_usart;
}
HsUsart::Stats const & HsUsart::GetStats(void)
{
return m_stats;
}
bool HsUsart::IsTxBusy()
{
return m_txBuffer.busy;
}
bool HsUsart::IsTxFailed()
{
return m_txBuffer.error;
}
bool HsUsart::IsRxBusy(bool second)
{
return m_rxBuffers[second].busy;
}
bool HsUsart::IsRxFailed(bool second)
{
return m_rxBuffers[second].error;
}
void HsUsart::RxProcessed(bool second)
void PacketUsart::RxProcessed(bool second)
{
m_rxBuffers[second].busy = false;
m_rxBuffers[second].error = false;
}
void HsUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
void PacketUsart::SetCallback(IHsUsartCallback *callback, uintptr_t callbackParam)
{
m_userCallback = callback;
m_userCallbackParam = callbackParam;
}
void HsUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
{
uint8_t hash = STARTMARKER;
packet.header.startByte = STARTMARKER;
packet.header.serial = serialNo;
hash ^= serialNo;
packet.header.payloadLength = length;
hash ^= length;
packet.header.hash = hash;
}
bool HsUsart::CheckHeader(PacketHeader &header)
{
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
}
void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
void PacketUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue)
{
uint16_t payloadLength = RoundUpTo4((uint16_t)length);
@ -117,16 +58,21 @@ void HsUsart::PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrc
}
void HsUsart::SetupReceive()
void PacketUsart::SetupReceive()
{
m_rxBuffers[m_rxBufferSelector].requestedLength = sizeof(m_rxBuffers[m_rxBufferSelector].packet);
UsartCore::SetupReceive(&m_rxBuffers[m_rxBufferSelector], sizeof(m_rxBuffers[m_rxBufferSelector].packet));
}
void HsUsart::ReceiverIdle(void)
//////////////////////////////////////
// UsartCore pure virtual functions //
//////////////////////////////////////
void PacketUsart::ReceiverIdle(void)
{
uint16_t rcvdLen = m_rxBuffers[m_rxBufferSelector].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
if(rcvdLen >= sizeof(PacketHeader)) {
if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header)) {
if(rcvdLen >= sizeof(PacketHeader) +
@ -144,7 +90,7 @@ void HsUsart::ReceiverIdle(void)
}
void HsUsart::TransmissionComplete(void)
void PacketUsart::TransmissionComplete(void)
{
LL_USART_DisableDirectionTx(m_usart); // enforcing an idle frame
LL_USART_EnableDirectionTx(m_usart);
@ -152,7 +98,13 @@ void HsUsart::TransmissionComplete(void)
}
void HsUsart::RxDmaTransferComplete(void)
void PacketUsart::FramingError(void) {}
void PacketUsart::Overrun(void) {}
void PacketUsart::RxDmaTransferComplete(void)
{
if(CheckHeader(m_rxBuffers[m_rxBufferSelector].packet.header))
CrcHandler::Instance().Enqueue(m_crcSlot, 1,
@ -166,38 +118,61 @@ void HsUsart::RxDmaTransferComplete(void)
SwitchRxBuffers();
}
void HsUsart::RxDmaHalfTransfer(void)
void PacketUsart::RxDmaHalfTransfer(void)
{
}
void HsUsart::RxDmaError(DmaHelper::DmaErrorType reason)
void PacketUsart::RxDmaError(DmaHelper::DmaErrorType reason)
{
m_rxBuffers[m_rxBufferSelector].error = 1;
++m_stats.rxDmaError;
SwitchRxBuffers();
}
void HsUsart::TxDmaTransferComplete(void)
void PacketUsart::TxDmaTransferComplete(void)
{
LL_USART_EnableIT_TC(m_usart);
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
}
void HsUsart::TxDmaHalfTransfer(void)
void PacketUsart::TxDmaHalfTransfer(void)
{
}
void HsUsart::TxDmaError(DmaHelper::DmaErrorType reason)
void PacketUsart::TxDmaError(DmaHelper::DmaErrorType reason)
{
m_txBuffer.error = 1;
++m_stats.txDmaError;
}
void HsUsart::SwitchRxBuffers(void)
///////////////////////
// Private functions //
///////////////////////
void PacketUsart::BuildHeader(Packet &packet, uint8_t serialNo, uint8_t length)
{
uint8_t hash = STARTMARKER;
packet.header.startByte = STARTMARKER;
packet.header.serial = serialNo;
hash ^= serialNo;
packet.header.payloadLength = length;
hash ^= length;
packet.header.hash = hash;
}
bool PacketUsart::CheckHeader(PacketHeader &header)
{
return header.startByte == STARTMARKER && (header.startByte ^ header.serial ^ header.payloadLength) == header.hash;
}
void PacketUsart::SwitchRxBuffers(void)
{
++m_stats.rcvd;
m_rxBufferSelector = !m_rxBufferSelector;
@ -207,8 +182,11 @@ void HsUsart::SwitchRxBuffers(void)
SetupReceive();
}
///////////////////////////
// CrcHandler::ICallback //
///////////////////////////
void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
void PacketUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
{
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
@ -223,7 +201,7 @@ void HsUsart::CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task)
}
void HsUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
void PacketUsart::CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task)
{
Buffer &buf(m_rxBuffers[static_cast<int>(callbackParam)]);
buf.busy = buf.error = true;

21
components/f4ll/src/usartcore.cpp
View file

@ -19,16 +19,29 @@ UsartCore::UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx,
LL_DMA_EnableIT_TC(dma, streamTx);
LL_DMA_EnableIT_TE(dma, streamTx);
LL_USART_EnableIT_IDLE(usart);
LL_USART_EnableIT_ERROR(usart);
}
void UsartCore::UsartIsr()
{
if(LL_USART_IsActiveFlag_IDLE(m_usart) && LL_USART_IsEnabledIT_IDLE(m_usart)) { // receiver idle
LL_USART_ClearFlag_IDLE(m_usart);
ReceiverIdle();
} else if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
if(LL_USART_IsActiveFlag_TC(m_usart) && LL_USART_IsEnabledIT_TC(m_usart)) { // transmission complete
LL_USART_DisableIT_TC(m_usart);
TransmissionComplete();
} else if(LL_USART_IsEnabledIT_ERROR(m_usart)) {
uint32_t status = m_usart->SR;
volatile uint32_t tmpreg = m_usart->DR; // clearing some of the error/status bits in the HW
(void) tmpreg;
if(status & USART_SR_IDLE) {
ReceiverIdle();
}
if(status & USART_SR_FE) {
FramingError();
}
if(status & USART_SR_ORE) {
Overrun();
}
}
}