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HsUsart renamed to PacketUsart, volatile usage review

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This commit is contained in:
Attila Body 2019-11-13 15:24:01 +01:00
parent 7cdc79c2ac
commit 23a75f43c7
12 changed files with 179 additions and 171 deletions
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14
components/f4ll/inc/consolehandler.h
View file

@ -8,7 +8,7 @@
#ifndef LL_CONSOLEHANDLER_H_
#define LL_CONSOLEHANDLER_H_
#include "f4ll/hsusart.h"
#include "f4ll/packetusart.h"
#include "singleton.h"
@ -19,9 +19,16 @@ class ConsoleHandler: public UsartCore, public Singleton<ConsoleHandler>
friend class Singleton<ConsoleHandler>;
public:
void PrintStats(uint8_t id, PacketUsart &usart);
private:
ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
// LL_UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void FramingError(void);
virtual void Overrun(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
@ -29,11 +36,6 @@ public:
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
void PrintStats(uint8_t id, HsUsart &usart);
private:
ConsoleHandler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
char m_buffer[128];
uint16_t m_used = 0;
};

24
components/f4ll/inc/crchandler.h
View file

@ -32,17 +32,17 @@ public:
friend class CrcHandler;
public:
struct CrcTask {
void const * volatile m_address; // changed to nullptr when execution starts
uint16_t volatile m_wordCount;
ICallback *m_callback;
uintptr_t m_callbackParam;
void const * m_address; // changed to nullptr when execution starts
uint16_t m_wordCount;
ICallback *m_callback;
uintptr_t m_callbackParam;
};
private:
SlotBase *m_next = nullptr;
SlotBase volatile *m_next = nullptr;
uint8_t m_taskCount;
virtual CrcTask& operator[](int index) = 0;
virtual CrcTask volatile & operator[](int index) volatile = 0;
protected:
SlotBase(unsigned int taskCount) : m_taskCount(taskCount) {}
@ -54,7 +54,7 @@ public:
{
public:
Slot() : SlotBase(n) {}
virtual CrcTask& operator[](int index) { return m_tasks[index]; }
virtual CrcTask volatile & operator[](int index) volatile { return m_tasks[index]; }
private:
Slot::CrcTask m_tasks[n];
@ -68,7 +68,7 @@ public:
bool IsQueued(SlotBase &slot, uint8_t task) const;
bool IsRunning(SlotBase &slot, uint8_t task) const;
void DmaTransferCompleted(void);
void DmaTransferCompleted(void);
private:
CrcHandler(DMA_TypeDef *dma, uint32_t stream);
@ -77,10 +77,10 @@ private:
void StartNextTask(void);
void WaitResults(SlotBase &slot, uint8_t task) const;
DmaHelper m_dma;
SlotBase * volatile m_firstSlot = nullptr;
SlotBase * volatile m_activeSlot = nullptr;
int volatile m_activeTask;
DmaHelper m_dma;
SlotBase volatile *m_firstSlot = nullptr;
SlotBase volatile *m_activeSlot = nullptr;
int volatile m_activeTask;
};

74
components/f4ll/inc/hsusart.h → components/f4ll/inc/packetusart.h
View file

@ -15,10 +15,11 @@ namespace f4ll {
struct DMAINFO;
class HsUsart : public CrcHandler::ICallback, public UsartCore
class PacketUsart : public CrcHandler::ICallback, public UsartCore
{
// friend class UsartCore;
public:
HsUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
PacketUsart(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
struct PacketHeader { // !!! size should be multiple of 4 !!!
uint8_t startByte;
@ -33,49 +34,42 @@ public:
} __attribute__((aligned));
struct Stats {
uint32_t overrun = 0;
uint32_t hdrError = 0;
uint32_t payloadErrror = 0;
uint32_t pep1 = 0;
uint32_t pep2 = 0;
uint32_t rxDmaError = 0;
uint32_t txDmaError = 0;
uint32_t rcvd = 0;
uint32_t premature_hdr = 0;
uint32_t overrun = 0;
uint32_t hdrError = 0;
uint32_t payloadErrror = 0;
uint32_t pep1 = 0;
uint32_t pep2 = 0;
uint32_t rxDmaError = 0;
uint32_t txDmaError = 0;
uint32_t rcvd = 0;
uint32_t premature_hdr = 0;
uint32_t premature_payload = 0;
uint32_t sent = 0;
uint32_t skiped = 0;
uint32_t sent = 0;
uint32_t skiped = 0;
};
struct IHsUsartCallback {
virtual bool PacketReceived(HsUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
virtual bool PacketReceived(PacketUsart *caller, uintptr_t userParam, Packet const &packet) = 0;
};
// CRCHandler::ICallback interface functions
virtual void CrcSucceeded(uintptr_t callbackParam, uint32_t crc, uint8_t task);
virtual void CrcFailed(uintptr_t callbackParam, uint32_t crc, uint8_t task);
// UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
void PostPacket(uint8_t const *payload, uint8_t length, bool waitForCrcQueue = true);
void SetupReceive(void);
void RxProcessed(bool second);
uint8_t* GetTxPacketBuffer(void);
USART_TypeDef* GetUsart(void);
Stats const & GetStats(void);
bool IsTxBusy(void);
bool IsTxFailed(void);
bool IsRxBusy(bool second);
bool IsRxFailed(bool second);
// Getters
uint8_t* GetTxPacketBuffer(void) { return m_txBuffer.packet.payload; }
uint8_t const * GetRxPacketBuffer(bool second) { return m_rxBuffers[second].packet.payload; }
USART_TypeDef* GetUsart(void) const { return m_usart; }
Stats const & GetStats(void) const { return m_stats; }
inline bool IsTxBusy(void) const { return m_txBuffer.busy; }
inline bool IsTxFailed(void) const { return m_txBuffer.error; }
inline bool IsRxBusy(bool second) const { return m_rxBuffers[second].busy; }
inline bool IsRxFailed(bool second) const { return m_rxBuffers[second].error; }
void SetCallback(IHsUsartCallback* callback, uintptr_t callbackParam);
@ -84,13 +78,25 @@ private:
bool CheckHeader(PacketHeader &header);
void SwitchRxBuffers(void);
// UsartCore pure virtual function implementations
virtual void ReceiverIdle(void);
virtual void TransmissionComplete(void);
virtual void FramingError(void);
virtual void Overrun(void);
virtual void RxDmaTransferComplete(void);
virtual void RxDmaHalfTransfer(void);
virtual void RxDmaError(DmaHelper::DmaErrorType reason);
virtual void TxDmaTransferComplete(void);
virtual void TxDmaHalfTransfer(void);
virtual void TxDmaError(DmaHelper::DmaErrorType reason);
struct Buffer {
Packet packet;
//transfer area ends here
volatile bool busy = 0;
volatile bool error = 0;
bool volatile busy = 0;
bool volatile error = 0;
uint16_t requestedLength = 0;
uint32_t errorInfo = 0;
uint32_t errorInfo = 0;
};
static const uint8_t STARTMARKER = 0x95;

28
components/f4ll/inc/usartcore.h
View file

@ -20,30 +20,34 @@ public:
static inline void HandleRxDmaIrq(UsartCore *_this) { _this->RxDmaIsr(); }
static inline void HandleTxDmaIrq(UsartCore *_this) { _this->TxDmaIsr(); }
void SetupTransmit(void const *buffer, uint16_t length);
void SetupReceive(void *buffer, uint16_t length);
protected:
UsartCore(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t streamRx, uint32_t streamTx);
virtual void ReceiverIdle() = 0;
virtual void TransmissionComplete() = 0;
USART_TypeDef *m_usart;
DmaHelper m_rxDma;
DmaHelper m_txDma;
virtual void RxDmaTransferComplete() = 0;
virtual void RxDmaHalfTransfer() = 0;
private:
virtual void ReceiverIdle(void) = 0;
virtual void TransmissionComplete(void) = 0;
virtual void FramingError(void) = 0;
virtual void Overrun(void) = 0;
virtual void RxDmaTransferComplete(void) = 0;
virtual void RxDmaHalfTransfer(void) = 0;
virtual void RxDmaError(DmaHelper::DmaErrorType reason) = 0;
virtual void TxDmaTransferComplete() = 0;
virtual void TxDmaHalfTransfer() = 0;
virtual void TxDmaTransferComplete(void) = 0;
virtual void TxDmaHalfTransfer(void) = 0;
virtual void TxDmaError(DmaHelper::DmaErrorType reason) = 0;
void SetupTransmit(void const *buffer, uint16_t length);
void SetupReceive(void *buffer, uint16_t length);
void UsartIsr();
void RxDmaIsr();
void TxDmaIsr();
USART_TypeDef *m_usart;
DmaHelper m_rxDma;
DmaHelper m_txDma;
};
} /* namespace f4ll */